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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xpufOzph+/xiAzd915jLBgo4M8irj3ScZHfTAI67nKE=; b=jVNkd3rsyCWeTh6fTxrPo+xiGvZqLihO3K0AaN+5Um9AQHYPlq9qr0usC1OvXnifhi s2lumrovBtluyGt5/LI0mddQQAcaM7CbqxVY/EcwiKHMD//gvNjxdYyQSfJRSyUqwmpw Jgqi7/dqC57R3JIkRvfIGCm9N+xLqeWJOZRmg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xpufOzph+/xiAzd915jLBgo4M8irj3ScZHfTAI67nKE=; b=mWhQuCH1A3o6PvrlQD3ArA6tjEPMgk9HNP8BDxO/BLe6ZN30XpAkb5/OnEF0JPxWgF 53BG9xzxbYGBIx1F/5fMOFCxbdiq2foNSVwoX4FuN2/N0Z1zd+QlOxbXKr33e6YZxRUo oxoW7RqPMUbnUmbc8hdQl0DxlpamiQhWHRY+fn5qOzxQWGrs2LDeZChcPccZJdtjMtIu 4Fl/r7/uIC/YnS0UdPBXnFAweKz+vMBZkE/yK7ifmciuiANT3r0CV7/dpCRzTlK4Cjpp RE7y2EEkX8CaNasEZe6acLFxYsopp8P9p8Os1rn6gfw3mPwtKAxSm+oLQ2+NkGe8HFZq zw6Q== X-Gm-Message-State: AHQUAuZoQ1hwFr1JX+Z/+wxaDwl+aSf2T7FqeRA9/NA345q5CMauIywO rvMTaaLgIqsgw4tzjLdQJExx91KiWuG65A== X-Google-Smtp-Source: AHgI3IZm0+/A5gdwL8slXQlwK9cU/dxoC4N/6HYqyNIyfDS5671460ZyfQl5SE5Dmma+83j6nMgbFg== X-Received: by 2002:a5d:4c82:: with SMTP id z2mr1061132wrs.252.1549037243593; Fri, 01 Feb 2019 08:07:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:27 +0000 Message-Id: <20190201160653.13829-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-21-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 961dbb3032a..3914e8e4bf2 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/armsse-cpuid.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -153,6 +154,8 @@ typedef struct ARMSSE { UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 + ARMSSECPUID cpuid[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9c111ac6a40..eb691faf720 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -34,6 +34,7 @@ struct ARMSSEInfo { bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; + bool has_cpuid; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -47,6 +48,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_ppus =3D false, .has_cachectrl =3D false, .has_cpusecctrl =3D false, + .has_cpuid =3D false, }, }; =20 @@ -314,6 +316,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpuid%d", i); + + sysbus_init_child_obj(obj, name, &s->cpuid[i], + sizeof(s->cpuid[i]), + TYPE_ARMSSE_CPUID); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -864,6 +876,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); + object_property_set_bool(OBJECT(&s->cpuid[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1