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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E4P/DANVH+5Z6S+WjRPWQLWvgWJCHbarYaKHzSG3E00=; b=eSYSWXBpmDs/KwWu8GuUHaaDQRMceYtaNoHxjFSVPZmi45oCM4wQsuvwcZO9dNK/Hn HWkol1xDPGOfjhlRkqh4DKXukhzKssZ0XNe15fBDdaKzL4P4pFOG+WVcE+bl3tqF0Pup mlIKrF/PY4+mg6qNwmG5HqOfwSYFdilBDTIb4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E4P/DANVH+5Z6S+WjRPWQLWvgWJCHbarYaKHzSG3E00=; b=ekr75bEH3yWI715HTgKZLmOIkqqzrzpKkHRyl8phpN1Xvo67T+y25b23n+SyDz3Sch Q5HPUVgEK6Y5x4KdjdyxHX6rSLGBuCjQ/1K++XNKUk5iknILY7zVpcGrxowTHxM2UITd Cmm/8kcNTw1Xgdp9BqHSe0VqxBYFe72WhYW/QskIZhPFUxruMHU3s/sbjGWJxuZJueJ5 WSAhrYOwmqO/WdAsWTDCyz8PWtSbsd29k14LNZ9hXhNAvaYpEtrhy9SHUrGiVHFu325p EiroVVGdNntJFjE/t8Pi9LXc/mKvyH4pEH7XNL6pa/97c2t3/5Oy9rYcjEIxo5mm8qRm tJ7Q== X-Gm-Message-State: AHQUAubcj/6ujWZi3ZJnAWoW6CUwyo8pCdLU/KvNaMHVI7JtsPOPLdN0 lbwkwUTBPcHYvm7ESn5hq5dQVTbQ4v9meQ== X-Google-Smtp-Source: AHgI3IYINwObjCLP/7A631G+LGiCuobJQkoGEUfCJXW9yWhgTwtLDUhL5Ii/Gyg1+FTlBauBz+17Cg== X-Received: by 2002:a1c:ac85:: with SMTP id v127mr2768761wme.62.1549037241075; Fri, 01 Feb 2019 08:07:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:25 +0000 Message-Id: <20190201160653.13829-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 19/47] hw/arm/armsse: Add unimplemented-device stub for CPU local control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-19-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9d830057d5c..961dbb3032a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -151,6 +151,7 @@ typedef struct ARMSSE { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; + UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 41e4a781e11..9c111ac6a40 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -33,6 +33,7 @@ struct ARMSSEInfo { bool has_mhus; bool has_ppus; bool has_cachectrl; + bool has_cpusecctrl; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -45,6 +46,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_mhus =3D false, .has_ppus =3D false, .has_cachectrl =3D false, + .has_cpusecctrl =3D false, }, }; =20 @@ -302,6 +304,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpusecctrl%d", i); + + sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], + sizeof(s->cpusecctrl[i]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -833,6 +845,25 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50010000, = mr); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPUSECCTRL%d", i); + MemoryRegion *mr; + + qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); + g_free(name); + qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000= ); + object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]= ), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1