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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n6sm2847250wmk.9.2019.02.01.08.07.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Feb 2019 08:07:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3GaEQBaYcD8tQevBwUkxpvEoMQwGTWbLDSGLaXKqALg=; b=cn5/p2/mcyq7x8TKagbJlk0LmP1H/+Xb4F7zgEXjrmcytk6k5/J3/zJ+ctVkxEn64C ywl5NTmLAfpAdzxMMCSyxl5sIgIpD8+etuOagXC5nQMO/521Qlp+OQVOzhuYfWVaxlhB Avkm9NpKko0QzDcOtCvmT9sOqzMhF9H2Oke0M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3GaEQBaYcD8tQevBwUkxpvEoMQwGTWbLDSGLaXKqALg=; b=rl9bmYQrxzr2POs6IP0/cCoj5voNtpgkfFflf5sQsS/DyhgLynilwVye4sM7olkH4s CKaocZVb2tPsdWZcXdKLt32tIKaU46ApKVzEcyYBzyDkjIHBAuz3RheVQOUMJuJLKp/b WvWY2v08mjSZ6E+sxsOjuNwS2fOMRIWDBAvfdygU91mnfRSQAMS0UL4v2QsM+Ywy8euN JFj00a/hS2bwitc5AGa+RpCL8Wlorv5Ty9fovgeP+lzDk39RetrZZuo6lxCIkcOUrVZ0 1MDSqi+u3V0C1Xj0gA+RWQTuRqAO/7hAT6Cb3z62JH/XjB0OCrgX5dQYsukZDOhePDia CgqQ== X-Gm-Message-State: AHQUAuYEpHNmFPiZpaQRswAgI+Zhi0PJDb+9RKnThWpG1KHy4L3pGg+z ZrWa7phpeZxJgcFiyOC+j/a5QJ6f25jGgw== X-Google-Smtp-Source: AHgI3IYoxbEkJWNTGdKhTSTtllg6e3q2UoA3B3ptJNruzkPhxUjWoA3IjksXRFCVlTzj0KG+DFWiIg== X-Received: by 2002:a7b:c04f:: with SMTP id u15mr2957236wmc.49.1549037238599; Fri, 01 Feb 2019 08:07:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 1 Feb 2019 16:06:23 +0000 Message-Id: <20190201160653.13829-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org> References: <20190201160653.13829-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 17/47] hw/arm/armsse: Add unimplemented-device stubs for PPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190121185118.18550-17-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 11 ++++++++ hw/arm/armsse.c | 58 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index dbfcb280605..9855ec5f269 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -106,6 +106,16 @@ =20 #define SSE_MAX_CPUS 2 =20 +/* These define what each PPU in the ppu[] index is for */ +#define CPU0CORE_PPU 0 +#define CPU1CORE_PPU 1 +#define DBG_PPU 2 +#define RAM0_PPU 3 +#define RAM1_PPU 4 +#define RAM2_PPU 5 +#define RAM3_PPU 6 +#define NUM_PPUS 7 + typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -139,6 +149,7 @@ typedef struct ARMSSE { IoTKitSysCtl sysinfo; =20 UnimplementedDeviceState mhu[2]; + UnimplementedDeviceState ppu[NUM_PPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1f3dc89c8e8..280ba5c78be 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -31,6 +31,7 @@ struct ARMSSEInfo { uint32_t sys_version; SysConfigFormat sys_config_format; bool has_mhus; + bool has_ppus; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -41,6 +42,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sys_version =3D 0x41743, .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, + .has_ppus =3D false, }, }; =20 @@ -265,6 +267,29 @@ static void armsse_init(Object *obj) sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), TYPE_UNIMPLEMENTED_DEVICE); } + if (info->has_ppus) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); + int ppuidx =3D CPU0CORE_PPU + i; + + sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], + sizeof(s->ppu[ppuidx]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], + sizeof(s->ppu[DBG_PPU]), + TYPE_UNIMPLEMENTED_DEVICE); + for (i =3D 0; i < info->sram_banks; i++) { + char *name =3D g_strdup_printf("RAM%d_PPU", i); + int ppuidx =3D RAM0_PPU + i; + + sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], + sizeof(s->ppu[ppuidx]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -329,6 +354,17 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, in= t irqno) } } =20 +static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) +{ + /* Map a PPU unimplemented device stub */ + DeviceState *dev =3D DEVICE(&s->ppu[ppuidx]); + + qdev_prop_set_string(dev, "name", name); + qdev_prop_set_uint64(dev, "size", 0x1000); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); +} + static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARMSSE(dev); @@ -833,6 +869,28 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); =20 + if (info->has_ppus) { + /* CPUnCORE_PPU for each CPU */ + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); + + map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); + /* + * We don't support CPU debug so don't create the + * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. + */ + g_free(name); + } + map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); + + for (i =3D 0; i < info->sram_banks; i++) { + char *name =3D g_strdup_printf("RAM%d_PPU", i); + + map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); + g_free(name); + } + } + /* This OR gate wires together outputs from the secure watchdogs to NM= I */ object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); if (err) { --=20 2.20.1