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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id h16sm9719135wrb.62.2019.01.31.05.07.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Jan 2019 05:07:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=0JO8RPLDHt6vVAFDC7iq+vX8nhpxSiNaD91+Ug+YDzk=; b=Nb59Kl0v+3p6tkbJR2PCaO7QajeT/VOjszk2uOVfvYEaTN1/eBZi4yzvOUsoZgcDoD n7ULiHkFqCf/bf6AuwkRTXFpiYbW7nI+7NvjiWV2/XAB5j5NMfIm09AR2lgLHADIYpWo eFtYVxu+hFXftyNmbM0wQUuL0AaDsgOPk5G4o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=0JO8RPLDHt6vVAFDC7iq+vX8nhpxSiNaD91+Ug+YDzk=; b=iRzGDsiJJ/gc4GdRbQjvzgOnq4dqciA9MdjIWKH59BVgYpTnvH6H9eef7zS2AV+TeN IZ3j4BoZZ0VFx1B9Mz2Y7weBAQrNvHIqkEXgatHc+QRbd2+lMKXJRTgdyz+G59LXB9qY muZVpaVNjrAhCkpD1ECHNDAaZvAIOnKJcVAunw1VKdnq1vb3KVuDHlGXpANM6tzEXL7v xsJ98wE8gdgwOo81P0k6tShb/i3x0MI+M858mcPheuEZwZeqSxiioACkvpgnqp2jpo9W fd1LR4dgO7DlcZ/vQTz4i3zz2/IcX9LLgfoIBeNJ2QUq+bsokoZwp7k4y6G25+s2HOeJ 80Og== X-Gm-Message-State: AJcUukf9Cdth0cRJSRRtaVIc69IQks4bBLykl8oHO7v3LbBUYODUu4fq Kwa/ub+hPDCd0ky7rO93heYbmg== X-Google-Smtp-Source: ALg8bN663aFQFpmhJVK2NWA433AsYkaQjSzlBTPLhzB3ODp+vimAeB4gPi+/cHZtbRps9RS5XRkb2w== X-Received: by 2002:a7b:c7c7:: with SMTP id z7mr31420339wmk.74.1548940022914; Thu, 31 Jan 2019 05:07:02 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 31 Jan 2019 13:07:00 +0000 Message-Id: <20190131130700.28392-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Husemann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for enabling trapped IEEE floating point exceptions (where IEEE exception conditions cause a CPU exception rather than updating the FPSR status bits). QEMU doesn't implement this (and nor does the hardware we're modelling), but for implementations which don't implement trapped exception handling these control bits are supposed to be RAZ/WI. This allows guest code to test for whether the feature is present by trying to write to the bit and checking whether it sticks. QEMU is incorrectly making these bits read as written. Make them RAZ/WI as the architecture requires. In particular this was causing problems for the NetBSD automatic test suite. Reported-by: Martin Husemann Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Martin: this is a different fix to the one I suggested you test, because I realized we need to make these bits RAZ/WI in the aarch32 FPSCR as well as the aarch64 FPCR, but it should have the same effect. General note: the difference between "RAZ/WI" and "RES0" is a bit subtle (see the Arm ARM glossary), but the main distinction is that RES0 bits can often be implemented as reads-as-written whilst RAZ/WI bits never can. --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b8161cb6d73..15e1464460f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1404,6 +1404,12 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07ff9f00 =20 +#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable= */ +#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ +#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ +#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ +#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ +#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 66faebea8ec..c5f10ddbe92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12508,6 +12508,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint3= 2_t val) val &=3D ~FPCR_FZ16; } =20 + /* + * We don't implement trapped exception handling, so the + * trap enable bits are all RAZ/WI (not RES0!) + */ + val &=3D ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR= _IOE); + changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; env->vfp.xregs[ARM_VFP_FPSCR] =3D (val & 0xffc8ffff); env->vfp.vec_len =3D (val >> 16) & 7; --=20 2.20.1