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Cota" To: qemu-devel@nongnu.org Date: Tue, 29 Jan 2019 19:47:21 -0500 Message-Id: <20190130004811.27372-24-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190130004811.27372-1-cota@braap.org> References: <20190130004811.27372-1-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v6 23/73] mips: convert to cpu_halted X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Aleksandar Markovic , Aurelien Jarno , James Hogan Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: James Hogan Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- hw/mips/cps.c | 2 +- hw/misc/mips_itu.c | 4 ++-- target/mips/kvm.c | 2 +- target/mips/op_helper.c | 8 ++++---- target/mips/translate.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index fc97f59af4..57f3c9e5fc 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -49,7 +49,7 @@ static void main_cpu_reset(void *opaque) cpu_reset(cs); =20 /* All VPs are halted on reset. Leave powering up to CPC. */ - cs->halted =3D 1; + cpu_halted_set(cs, 1); } =20 static bool cpu_mips_itu_supported(CPUMIPSState *env) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 1257d8fce6..1fab14d332 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -181,7 +181,7 @@ static void wake_blocked_threads(ITCStorageCell *c) { CPUState *cs; CPU_FOREACH(cs) { - if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { + if (cpu_halted(cs) && (c->blocked_threads & (1ULL << cs->cpu_index= ))) { cpu_interrupt(cs, CPU_INTERRUPT_WAKE); } } @@ -191,7 +191,7 @@ static void wake_blocked_threads(ITCStorageCell *c) static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) { c->blocked_threads |=3D 1ULL << current_cpu->cpu_index; - current_cpu->halted =3D 1; + cpu_halted_set(current_cpu, 1); current_cpu->exception_index =3D EXCP_HLT; cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc); } diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 8e72850962..0b177a7577 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -156,7 +156,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_r= un *run) =20 int kvm_arch_process_async_events(CPUState *cs) { - return cs->halted; + return cpu_halted(cs); } =20 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index aebad24ed6..0b8104c27f 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -649,7 +649,7 @@ static bool mips_vpe_is_wfi(MIPSCPU *c) =20 /* If the VPE is halted but otherwise active, it means it's waiting for an interrupt. */ - return cpu->halted && mips_vpe_active(env); + return cpu_halted(cpu) && mips_vpe_active(env); } =20 static bool mips_vp_is_wfi(MIPSCPU *c) @@ -657,7 +657,7 @@ static bool mips_vp_is_wfi(MIPSCPU *c) CPUState *cpu =3D CPU(c); CPUMIPSState *env =3D &c->env; =20 - return cpu->halted && mips_vp_active(env); + return cpu_halted(cpu) && mips_vp_active(env); } =20 static inline void mips_vpe_wake(MIPSCPU *c) @@ -674,7 +674,7 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu) =20 /* The VPE was shut off, really go to bed. Reset any old _WAKE requests. */ - cs->halted =3D 1; + cpu_halted_set(cs, 1); cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); } =20 @@ -2669,7 +2669,7 @@ void helper_wait(CPUMIPSState *env) { CPUState *cs =3D CPU(mips_env_get_cpu(env)); =20 - cs->halted =3D 1; + cpu_halted_set(cs, 1); cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); /* Last instruction in the block, PC was updated before - no need to recover PC and icount */ diff --git a/target/mips/translate.c b/target/mips/translate.c index e9b5d1d860..3e20ce9f1d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -30044,7 +30044,7 @@ void cpu_state_reset(CPUMIPSState *env) env->tcs[i].CP0_TCHalt =3D 1; } env->active_tc.CP0_TCHalt =3D 1; - cs->halted =3D 1; + cpu_halted_set(cs, 1); =20 if (cs->cpu_index =3D=3D 0) { /* VPE0 starts up enabled. */ @@ -30052,7 +30052,7 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_VPEConf0 |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VP= A); =20 /* TC0 starts up unhalted. */ - cs->halted =3D 0; + cpu_halted_set(cs, 0); env->active_tc.CP0_TCHalt =3D 0; env->tcs[0].CP0_TCHalt =3D 0; /* With thread 0 active. */ --=20 2.17.1