From nobody Wed Oct 1 12:05:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548764381217373.31012716252917; Tue, 29 Jan 2019 04:19:41 -0800 (PST) Received: from localhost ([127.0.0.1]:48317 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goSMd-0003xS-Ok for importer@patchew.org; Tue, 29 Jan 2019 07:19:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46931) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goSLf-0003SQ-UM for qemu-devel@nongnu.org; Tue, 29 Jan 2019 07:18:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goSLe-0003An-7G for qemu-devel@nongnu.org; Tue, 29 Jan 2019 07:18:39 -0500 Received: from smtp58.i.mail.ru ([217.69.128.38]:48732) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1goSLc-00039A-88 for qemu-devel@nongnu.org; Tue, 29 Jan 2019 07:18:37 -0500 Received: by smtp58.i.mail.ru with esmtpa (envelope-from ) id 1goSLS-0000Nw-Ql; Tue, 29 Jan 2019 15:18:27 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject:Cc:To:From; bh=TbNqHjy/WkbV3aW9sXK6M8smn8BvuyHdyAq58HFB4zk=; b=eyMnondJR2YeSLGyo3vQFKYeFArxmRLFO4wVqXjQmmRgUe4vU8zkwhKQQW0k0B/VH5sY1jpIScaL6flwBGBx9nK9Px+FEsh2SptDJ/ga0dkr77XCAMcIGYijDLzuMjaqBQY0iBv3Tdm3Ogtzpuv7hWL81+VUBa9qTLOo9RRjg/8=; To: qemu-devel@nongnu.org Date: Tue, 29 Jan 2019 15:18:17 +0300 Message-Id: <20190129121817.7109-1-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Authentication-Results: smtp58.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-77F55803: 3FFC80838138E3AB5A78504BD2AC2941D8BD2B4607DED84BBFB15F1A05FCB9A4CAA19320FED72A67FABD0A681AC46374 X-7FA49CB5: 0D63561A33F958A562D4B5C2F9725D4796E6B82AF9D9FCBAF4F8E67133DF0DA68941B15DA834481FA18204E546F3947CEDCF5861DED71B2F389733CBF5DBD5E9C8A9BA7A39EFB7666BA297DBC24807EA117882F44604297287769387670735209ECD01F8117BC8BEA471835C12D1D977C4224003CC8364767815B9869FA544D8D32BA5DBAC0009BE9E8FC8737B5C2249006F265BD8B56D553AA81AA40904B5D9CF19DD082D7633A0E7DDDDC251EA7DABD81D268191BDAD3D78DA827A17800CE7E652162C2C37A454CD04E86FAF290E2D40A5AABA2AD3711975ECD9A6C639B01B78DA827A17800CE7D26A93F9BDF81FCE2A2BE498C6DE14B775ECD9A6C639B01B4E70A05D1297E1BBC6867C52282FAC8518D57E64F6AADFC527F269C8F02392CD5571747095F342E88FB05168BE4CE3AF X-Mailru-Sender: CC07D204AB7BD32F3BE87068C2BB4672786D1FD4CFA7CEC63AA88455965CE9618C7764B41FF7EAAB342D7E53901C55FD6F53C80213D1719C4487B406A59785443329DBF425CF03A167EA787935ED9F1B X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 217.69.128.38 Subject: [Qemu-devel] [PATCH] arm: Clarify the logic of set_pc() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Julia Suvorova , Stefan Hajnoczi Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Until now, the set_pc logic was unclear, which raised questions about whether it should be used directly, applying a value to PC or adding additional checks, for example, set the Thumb bit in Arm cpu. Let's set the set_pc logic for =E2=80=9CConfigure the PC, as was done in the ELF file= =E2=80=9D and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec. Signed-off-by: Julia Suvorova Acked-by: Stefan Hajnoczi --- hw/arm/boot.c | 4 ---- include/qom/cpu.h | 16 ++++++++++++++-- target/arm/arm-powerctl.c | 3 --- target/arm/cpu.c | 26 +++++++++++++++++++++++++- target/arm/cpu64.c | 15 --------------- 5 files changed, 39 insertions(+), 25 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index c7a67af7a9..05762d0fc1 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -697,10 +697,6 @@ static void do_cpu_reset(void *opaque) g_assert_not_reached(); } =20 - if (!env->aarch64) { - env->thumb =3D info->entry & 1; - entry &=3D 0xfffffffe; - } cpu_set_pc(cs, entry); } else { /* If we are booting Linux then we need to check whether we are diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 16bbed1ae0..deb92c414f 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -103,9 +103,21 @@ struct TranslationBlock; * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @get_memory_mapping: Callback for obtaining the memory mappings. - * @set_pc: Callback for setting the Program Counter register. + * @set_pc: Callback for setting the Program Counter register. This + * should have the semantics used by the target architecture when + * setting the PC from a source such as an ELF file entry point; + * for example on Arm it will also set the Thumb mode bit based + * on the least significant bit of the new PC value. + * If the target behaviour here is anything other than "set + * the PC register to the value passed in" then the target must + * also implement the synchronize_from_tb hook. * @synchronize_from_tb: Callback for synchronizing state from a TCG - * #TranslationBlock. + * #TranslationBlock. This is called when we abandon execution + * of a TB before starting it, and must set all parts of the CPU + * state which the previous TB in the chain may not have updated. + * This always includes at least the program counter; some targets + * will need to do more. If this hook is not implemented then the + * default is to call @set_pc(tb->pc). * @handle_mmu_fault: Callback for handling an MMU fault. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 2b856930fb..f9de5164e5 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -120,11 +120,8 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, =20 if (info->target_aa64) { target_cpu->env.xregs[0] =3D info->context_id; - target_cpu->env.thumb =3D false; } else { target_cpu->env.regs[0] =3D info->context_id; - target_cpu->env.thumb =3D info->entry & 1; - info->entry &=3D 0xfffffffe; } =20 /* Start the new CPU at the requested address */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e1f3dd637..2e7bdde9f5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -40,8 +40,31 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + env->pc =3D value; + env->thumb =3D 0; + } else { + env->regs[15] =3D value & ~1; + env->thumb =3D value & 1; + } +} =20 - cpu->env.regs[15] =3D value; +static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb->pc; + } else { + env->regs[15] =3D tb->pc; + } } =20 static bool arm_cpu_has_work(CPUState *cs) @@ -2088,6 +2111,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; + cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e9bc461c36..8653cecd03 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -480,20 +480,6 @@ static void aarch64_cpu_finalizefn(Object *obj) { } =20 -static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - /* It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - * (Otherwise we would need to use synchronize_from_tb instead.) - */ - if (is_a64(&cpu->env)) { - cpu->env.pc =3D value; - } else { - cpu->env.regs[15] =3D value; - } -} - static gchar *aarch64_gdb_arch_name(CPUState *cs) { return g_strdup("aarch64"); @@ -504,7 +490,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, voi= d *data) CPUClass *cc =3D CPU_CLASS(oc); =20 cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; - cc->set_pc =3D aarch64_cpu_set_pc; cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; --=20 2.17.1