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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ori3cO87FQgSnTdpKDHLNY2jwd5cT8Lr+GZNSeVH0Ck=; b=bDIzp6OGG0DR79uU7qH9JOn9Y6dhOZ32wyZyfYgMqvehiS9B1OwDRRTa/3OHDx0t6h Gva76ZPqCIx59q5FyOszF6H558QgVgXr24LGaAFy5STpoycQUUexrMACwQL7cQDPxkYx svSx4ixVpgCAwzC7E//Yk8OJtBcQD2ttu+Y8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ori3cO87FQgSnTdpKDHLNY2jwd5cT8Lr+GZNSeVH0Ck=; b=tUdXWx15Kz3BnGbPuf1OnViAPUCbt2lKJvBQBkQ4SVjrUY96nljQDh3z8Yxsv0OYRX onF8g4MkaRWhVXKBqOV4ioejYpLbvrzSMB7c2MO5W4BId8Xk8V17iq+kM1SMIadidjFj RbtmZTAD8cqlmzd4v54BEpmRfskd2gffF7q+KJ4ACR+mmEsQ0V4Ad/ALhCEsY2Z78WxH gfVekALA7GorBNyAj6G/XEHtWgW2obCg7mOFz5NHrBWQzpA28PB7d6b5OY+zgnqvDhT1 r5dGveLAJNSF1dKayPqnlR857ey58Y+hmBreuzXgkomQGfHFLuNx0/1cl3wDyrAqiEzu UKug== X-Gm-Message-State: AJcUukcEQZ2f7C/2vDv2EOHQG29CNMijnx1/P/z8TNtAKJinaw+0dc+7 Mzho2Jf99uoE98Gvc4gwRM/wrBew4+2Vew== X-Google-Smtp-Source: ALg8bN4QNTYXlP0CwVaJLr1qhjfXr+AuPwGEkwFGGQ6yvW3A0fDo9GrazcKs9v9fKyC8gEv7O+n4AA== X-Received: by 2002:a1c:4c10:: with SMTP id z16mr18812215wmf.117.1548699061051; Mon, 28 Jan 2019 10:11:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:30 +0000 Message-Id: <20190128181047.20781-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 09/26] target/arm: Don't clear supported PMU events when initializing PMCEID1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay OS A bug was introduced during a respin of: commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20190123195814.29253-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 +++++------ target/arm/cpu.c | 3 +-- target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 22 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff81db420d5..b8161cb6d73 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1012,14 +1012,13 @@ void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 /* - * get_pmceid - * @env: CPUARMState - * @which: which PMCEID register to return (0 or 1) + * pmu_init + * @cpu: ARMCPU * - * Return the PMCEID[01]_EL0 register values corresponding to the counters - * which are supported given the current configuration + * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal s= tate + * for the current configuration */ -uint64_t get_pmceid(CPUARMState *env, unsigned which); +void pmu_init(ARMCPU *cpu); =20 /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e1f3dd637a..d6da3f4fed3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1039,8 +1039,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - cpu->pmceid0 =3D get_pmceid(&cpu->env, 0); - cpu->pmceid1 =3D get_pmceid(&cpu->env, 1); + pmu_init(cpu); =20 if (!kvm_enabled()) { arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); diff --git a/target/arm/helper.c b/target/arm/helper.c index 676059cb386..66faebea8ec 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1090,22 +1090,24 @@ static const pm_event pm_events[] =3D { static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 /* - * Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicat= ed by - * 'which'). We also use it to build a map of ARM event numbers to indices= in - * our pm_events array. + * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map + * of ARM event numbers to indices in our pm_events array. * * Note: Events in the 0x40XX range are not currently supported. */ -uint64_t get_pmceid(CPUARMState *env, unsigned which) +void pmu_init(ARMCPU *cpu) { - uint64_t pmceid =3D 0; unsigned int i; =20 - assert(which <=3D 1); - + /* + * Empty supported_event_map and cpu->pmceid[01] before adding support= ed + * events to them + */ for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { supported_event_map[i] =3D UNSUPPORTED_EVENT; } + cpu->pmceid0 =3D 0; + cpu->pmceid1 =3D 0; =20 for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { const pm_event *cnt =3D &pm_events[i]; @@ -1113,13 +1115,16 @@ uint64_t get_pmceid(CPUARMState *env, unsigned whic= h) /* We do not currently support events in the 0x40xx range */ assert(cnt->number <=3D 0x3f); =20 - if ((cnt->number & 0x20) =3D=3D (which << 6) && - cnt->supported(env)) { - pmceid |=3D (1 << (cnt->number & 0x1f)); + if (cnt->supported(&cpu->env)) { supported_event_map[cnt->number] =3D i; + uint64_t event_mask =3D 1 << (cnt->number & 0x1f); + if (cnt->number & 0x20) { + cpu->pmceid1 |=3D event_mask; + } else { + cpu->pmceid0 |=3D event_mask; + } } } - return pmceid; } =20 /* --=20 2.20.1