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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dzqOBgB1v6gsOex139U1WEoQboBpRHnuWTjE6bnEP1Y=; b=ghfvYoTN/PoXSrCWNXnjyQvmwqR5Rr9miQGLoKLdoipwdI8tkZmFf/14LQIXucaaLZ azsWA504I9azTVdKOjkudAO/3hIL7uwdD3FO+riEP7BKfz9pq9QFnW8kUn7Lzk0ELQa0 fKEZehUIwm7XcvKtnVxwsHhDdqpqnvaqrFPbA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dzqOBgB1v6gsOex139U1WEoQboBpRHnuWTjE6bnEP1Y=; b=J2E8M86eGgiSZ7jxUquBn7lMg9Unu5rgUwTi5A+PpMTXiEQvrJ+unw81w3UCTy2XDK nFmNM4zTo7m7gQiR1kMCleo4uNKXjBJJQptz4Cjh0vHdR8u2hW+qGSffU7GR2yB91Sop 1p4+8dZaPRiGSJE1kJYnO3NWM3gDUF+CqvGmqqvEl7ZC5cTlvXa0RUscEn0K9cp94nYn sGlhGySldjdxbHS07YxoLfBusgfyL3SIBCIfxrqA7LGhiuRioe/OW8z/iGpgx7Fu6+Hy 8f8wpJ+7+cq2dkp2pFktav7J/SI3Adltm2LYW7bxMk+9NYeVa5TVW85eyTKlosN/cMFI Xlbw== X-Gm-Message-State: AJcUukf6Saz4LEVSOjBTBxEvpoLcZsSbRRErkrj/lFMWq53FGOqzcwqF ZcYglWVVxraYKa539B256dtgfAcwMPu71w== X-Google-Smtp-Source: ALg8bN5zxHfy128Qy+ZVioAbcY2Tj0KZ2do+Gjm9ahxWBIdqVg3lFk8ttd8/E3WQnMCNFwkjLGlCDg== X-Received: by 2002:a5d:548d:: with SMTP id h13mr21662725wrv.80.1548699051609; Mon, 28 Jan 2019 10:10:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:22 +0000 Message-Id: <20190128181047.20781-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 01/26] target/arm: Fix validation of 32-bit address spaces for aa32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson When tsz =3D=3D 0, aarch32 selects the address space via exclusion, and there are no "top_bits" remaining that require validation. Fixes: ba97be9f4a4 Reported-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190125184913.5970-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92666e52085..e24689f7677 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10447,7 +10447,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; uint32_t tableattrs; - target_ulong page_size, top_bits; + target_ulong page_size; uint32_t attrs; int32_t stride; int addrsize, inputsize; @@ -10487,12 +10487,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, * We determined the region when collecting the parameters, but we * have not yet validated that the address is valid for the region. * Extract the top bits and verify that they all match select. + * + * For aa32, if inputsize =3D=3D addrsize, then we have selected the + * region by exclusion in aa32_va_parameters and there is no more + * validation to do here. */ - top_bits =3D sextract64(address, inputsize, addrsize - inputsize); - if (-top_bits !=3D param.select || (param.select && !ttbr1_valid)) { - /* In the gap between the two regions, this is a Translation fault= */ - fault_type =3D ARMFault_Translation; - goto do_fault; + if (inputsize < addrsize) { + target_ulong top_bits =3D sextract64(address, inputsize, + addrsize - inputsize); + if (-top_bits !=3D param.select || (param.select && !ttbr1_valid))= { + /* The gap between the two regions is a Translation fault */ + fault_type =3D ARMFault_Translation; + goto do_fault; + } } =20 if (param.using64k) { --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548699951867546.1490073647199; Mon, 28 Jan 2019 10:25:51 -0800 (PST) Received: from localhost ([127.0.0.1]:36580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBbL-0005zM-R0 for importer@patchew.org; Mon, 28 Jan 2019 13:25:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN7-0002cf-3g for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN5-0008Ha-3a for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:00 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN1-00089I-O7 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:10:57 -0500 Received: by mail-wr1-x441.google.com with SMTP id l9so19087392wrt.13 for ; Mon, 28 Jan 2019 10:10:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ksbbs4eq/TMj7Xsvipvw1RXYQf1Zrz8wpVuGlt97Emk=; b=dkifgWUr8YxNfUtnzfF03ZvDpu8e+hawmPGgyo3iqNbchuTo5aHGkaO7ZDIsrLxCo6 1W5vZ/YwY5T1SzdQuB4K5npiktwdimFTZUrcMJTCdh2y70zrXnoqTR3KT27IYZcKRgez 55+0gs5P+jcdUazqOloYT7j1nExnKLbZ0Gq0M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ksbbs4eq/TMj7Xsvipvw1RXYQf1Zrz8wpVuGlt97Emk=; b=DQJhM1mMGHec/gEeF4cu9g4AT2gY+nEX/vrB0ujlfcw59NBIzMFxw696Zb3rdAJxmt Uz+NURL1jU5UsJp4S/IFGm9Es3LRpfOYPBdEAGlOEenb6JG9V+mVksXf63kCB9xQ7IfK izBWCWhshMlz95su9jatV1M+lH0kjPgnP+C9xDc+fEsuKO5h6yK7JXVZHGSZ5h0CAZ/E A1teqYkduzqXaIetu1V65lVc9NNVmVrtvHZmXhJKhFghLnJ6N68ZbpYtxXvf59N02Cby h09L8n54br0GxXU9yfyqPxv+DFSGS5UwK4Spmnm9IjI68mvF4q/zuoGm9l6flr89CzVb nvEQ== X-Gm-Message-State: AJcUuke7x1zgGxUeQxAqGvhu11MVtcPc1LIrFcKeblT6IA+GBX2fYGlt +ipZYgZ/1U36nB9wWmPcZZpEmHoSnwA9dQ== X-Google-Smtp-Source: ALg8bN7snab4WOx41fjvFIfv/0FMAV2xkZMfv4VLatnUHU365pKFmfLC2efY+yZ5IodPOXiztOKUlg== X-Received: by 2002:adf:9361:: with SMTP id 88mr22179424wro.204.1548699052783; Mon, 28 Jan 2019 10:10:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:23 +0000 Message-Id: <20190128181047.20781-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 02/26] target/arm: v8m: Ensure IDAU is respected if SAU is disabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Thomas Roth The current behavior of v8m_security_lookup in helper.c only checks whether= the IDAU specifies a higher security if the SAU is enabled. If SAU.ALLNS is set= to 1, this will lead to addresses being treated as non-secure, even though the IDAU indicates that they must be secure. This patch changes the behavior to also check the IDAU if the SAU is curren= tly disabled. (This brings the behaviour here into line with the v8M Arm ARM SecurityCheck() pseudocode.) Signed-off-by: Thomas Roth Message-id: CAGGekkuc+-tvp5RJP7CM+Jy_hJF7eiRHZ96132sb=3DhPPCappKg@mail.gmai= l.com Reviewed-by: Peter Maydell [PMM: added pseudocode ref to the commit message, fixed comment style] Signed-off-by: Peter Maydell --- target/arm/helper.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e24689f7677..676059cb386 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11078,18 +11078,19 @@ static void v8m_security_lookup(CPUARMState *env,= uint32_t address, } } } - - /* The IDAU will override the SAU lookup results if it specifies - * higher security than the SAU does. - */ - if (!idau_ns) { - if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { - sattrs->ns =3D false; - sattrs->nsc =3D idau_nsc; - } - } break; } + + /* + * The IDAU will override the SAU lookup results if it specifies + * higher security than the SAU does. + */ + if (!idau_ns) { + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { + sattrs->ns =3D false; + sattrs->nsc =3D idau_nsc; + } + } } =20 static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548699872880534.4486505102946; Mon, 28 Jan 2019 10:24:32 -0800 (PST) Received: from localhost ([127.0.0.1]:36542 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBa6-0004hf-QC for importer@patchew.org; Mon, 28 Jan 2019 13:24:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN3-0002Zq-Sz for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:10:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN1-0008Dy-QY for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:10:57 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:35825) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN1-0008BL-Jf for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:10:55 -0500 Received: by mail-wm1-x341.google.com with SMTP id t200so15071697wmt.0 for ; Mon, 28 Jan 2019 10:10:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g1+1iU25RO4b9+GWllKtnX6ssOKxW8r9jeqFWVW6jf4=; b=Fqv6oFNV1U7huHW9yy1c4MYzG7K1oAoxgfFjMq+eSPt9giWVIzE4mRHU5VGnSe+O8H AB2sPSfEjlfOY7IoiN6Xp/Y/v808KHnwOVbLOr/CDXT2mngWrb3tbeozTtakb2qyHDPN 1p9J+iIZZgU/Vu77i5XD9zjeWnxzmTD/t/onA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g1+1iU25RO4b9+GWllKtnX6ssOKxW8r9jeqFWVW6jf4=; b=PsaQ4dhMcOc6JWxJ0MQI9YqdJQu2xm0QO3eQ54zYgO680braxJNqB+lpD+po/S+zzY rnpQqim1c8F/P9YoCr5l0rlX97ToiSZDWvNf28SvL47FGorB5svdpgml+4pVjXfHK+Y/ 5Uo1UBPJ0vdKc8wBuDY/Y9nIyP1Cq8t1wrHSYcFvEcLqHdTp9cJkWMOH+Lw7kZ9QZ8JK BtW5ATBNnaI/95unGHCzGtor25s03puTKORc29x2GWkCEITOxcNWVuIHdZAzXeWiYxkW oQI6IY/Od1Ew/9nG5Kwpr4NmrgRT5E0bqaeNrSUBR0i2q3yrK4MOBw5uFJ6PZD+nezAP J/zw== X-Gm-Message-State: AJcUukfxgya/iMSor82yByaKe/UzV5FQms9MxqE6Vwzt1qMLGDOxlCRG WLGigQs5sPCVX6wsZA6J2PzJUB76gNt9SQ== X-Google-Smtp-Source: ALg8bN5XZEZ+By56A802omDXr7kaLhPs2Ge+b8g4oFWO6i2ZePTugbkX89/m056HHXu3ErqqSD+UlQ== X-Received: by 2002:a1c:9806:: with SMTP id a6mr17773164wme.114.1548699053877; Mon, 28 Jan 2019 10:10:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:24 +0000 Message-Id: <20190128181047.20781-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 03/26] gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luc Michel a TID or PID value means "any thread" (resp. "any process"). This commit fixes the different combinations when at least one value is 0. When both are 0, the function now returns the first attached CPU, instead of the CPU with TID 1, which is not necessarily attached or even existent. When PID is specified but TID is 0, the function returns the first CPU in the process, or NULL if the process does not exist or is not attached. In other cases, it returns the corresponding CPU, while ignoring the PID check when PID is 0. Reported-by: Peter Maydell Signed-off-by: Luc Michel Reviewed-by: Peter Maydell Message-id: 20190119140000.11767-1-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- gdbstub.c | 72 +++++++++++++++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 29 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index bfc7afb5096..d4cc6ecf99b 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -756,35 +756,6 @@ static CPUState *gdb_next_cpu_in_process(const GDBStat= e *s, CPUState *cpu) return cpu; } =20 -static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) -{ - GDBProcess *process; - CPUState *cpu; - - if (!tid) { - /* 0 means any thread, we take the first one */ - tid =3D 1; - } - - cpu =3D find_cpu(tid); - - if (cpu =3D=3D NULL) { - return NULL; - } - - process =3D gdb_get_cpu_process(s, cpu); - - if (process->pid !=3D pid) { - return NULL; - } - - if (!process->attached) { - return NULL; - } - - return cpu; -} - /* Return the cpu following @cpu, while ignoring unattached processes. */ static CPUState *gdb_next_attached_cpu(const GDBState *s, CPUState *cpu) { @@ -814,6 +785,49 @@ static CPUState *gdb_first_attached_cpu(const GDBState= *s) return cpu; } =20 +static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid) +{ + GDBProcess *process; + CPUState *cpu; + + if (!pid && !tid) { + /* 0 means any process/thread, we take the first attached one */ + return gdb_first_attached_cpu(s); + } else if (pid && !tid) { + /* any thread in a specific process */ + process =3D gdb_get_process(s, pid); + + if (process =3D=3D NULL) { + return NULL; + } + + if (!process->attached) { + return NULL; + } + + return get_first_cpu_in_process(s, process); + } else { + /* a specific thread */ + cpu =3D find_cpu(tid); + + if (cpu =3D=3D NULL) { + return NULL; + } + + process =3D gdb_get_cpu_process(s, cpu); + + if (pid && process->pid !=3D pid) { + return NULL; + } + + if (!process->attached) { + return NULL; + } + + return cpu; + } +} + static const char *get_feature_xml(const GDBState *s, const char *p, const char **newp, GDBProcess *process) { --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700912800160.89012153330088; Mon, 28 Jan 2019 10:41:52 -0800 (PST) Received: from localhost ([127.0.0.1]:36822 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBqu-0002XS-Hz for importer@patchew.org; Mon, 28 Jan 2019 13:41:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN9-0002fk-Uj for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN7-0008Me-NN for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:03 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:34154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN6-0008EN-A6 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:01 -0500 Received: by mail-wm1-x343.google.com with SMTP id y185so11062339wmd.1 for ; Mon, 28 Jan 2019 10:10:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.53 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5SVy/G+rudPF28WchmM63tosFhBQDHRZR1pK9+PXPTA=; b=MJ00YpRUkLxVWvTR41lbjs3o8qPaeP026KflJIyRPh6iOkjBNLZpu27PoWSX9D2EOh K6jv4Oq2NeFaFe+zipDxepsAN4aGu77A7rQ+NltxhM2dIk8MTAdzipAeeYEHf5nCkPMn VD2QSXt6kEguvBQDzzkcBBKebGs1YjN2TNnB0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5SVy/G+rudPF28WchmM63tosFhBQDHRZR1pK9+PXPTA=; b=lxUS4WflUL37slx7dillKnytxMh3nG6omX/PjH4UbOcPr1pNZaIbun3ekbW+ek+KE4 loRYkWR47eTd/uVA1lR71+s4ndC6WAbFfLy010B1x5d/VP3bxDqRYD2ONQDJaTHE70vw oB52kSEz/iD3y8CIdJ8HBY8HO4hennQCcrNZiiABMrYOHGHwk/2R28S237c+0wJ0WCDx 1P5sF2Heg/ya3ouo5FwYrZ/r83J1G3v1RAlbwyYL5zMfaAXp8rLmpWo+2baGjA79BnEq de9gWr0Bi7JmrfgfTG6gl+O1yOX0LDKqkuoEJ7YQ5InMC2K2gvgBCrMuLMRwK5b5afbp bnlg== X-Gm-Message-State: AJcUukeRnql5x8by8i35ourNrepHFWKy4nIpw50lUUf1wsyj4zwKy+WW fN57/QC43FuBFsvqWdf9fUAQWs10t0LXYw== X-Google-Smtp-Source: ALg8bN4fsWuQGKxQP3Xerh9X0P9n+RFa0H3jIoY4YlUwhw03+g9qWcZ16XT+WLT7KEttjbS+BOUYAQ== X-Received: by 2002:a1c:bbd6:: with SMTP id l205mr16997971wmf.97.1548699055064; Mon, 28 Jan 2019 10:10:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:25 +0000 Message-Id: <20190128181047.20781-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 04/26] arm: Stub out NRF51 TWI magnetometer/accelerometer detection X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen G=C3=B6rtz Signed-off-by: Stefan Hajnoczi Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell [PMM: fixed comment style] Signed-off-by: Peter Maydell --- hw/i2c/Makefile.objs | 1 + include/hw/arm/nrf51.h | 2 + include/hw/arm/nrf51_soc.h | 1 + include/hw/i2c/microbit_i2c.h | 42 +++++++++++ hw/arm/microbit.c | 16 +++++ hw/i2c/microbit_i2c.c | 127 ++++++++++++++++++++++++++++++++++ 6 files changed, 189 insertions(+) create mode 100644 include/hw/i2c/microbit_i2c.h create mode 100644 hw/i2c/microbit_i2c.c diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs index 37cacde9788..82e747e1cd1 100644 --- a/hw/i2c/Makefile.objs +++ b/hw/i2c/Makefile.objs @@ -7,5 +7,6 @@ common-obj-$(CONFIG_BITBANG_I2C) +=3D bitbang_i2c.o common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_i2c.o common-obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_i2c.o +common-obj-$(CONFIG_NRF51_SOC) +=3D microbit_i2c.o obj-$(CONFIG_OMAP) +=3D omap_i2c.o obj-$(CONFIG_PPC4XX) +=3D ppc4xx_i2c.o diff --git a/include/hw/arm/nrf51.h b/include/hw/arm/nrf51.h index 175bb6c301e..1008fee6c93 100644 --- a/include/hw/arm/nrf51.h +++ b/include/hw/arm/nrf51.h @@ -25,6 +25,8 @@ #define NRF51_IOMEM_SIZE 0x20000000 =20 #define NRF51_UART_BASE 0x40002000 +#define NRF51_TWI_BASE 0x40003000 +#define NRF51_TWI_SIZE 0x00001000 #define NRF51_TIMER_BASE 0x40008000 #define NRF51_TIMER_SIZE 0x00001000 #define NRF51_RNG_BASE 0x4000D000 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index e06f0304b48..fbdefc07e4d 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -39,6 +39,7 @@ typedef struct NRF51State { MemoryRegion sram; MemoryRegion flash; MemoryRegion clock; + MemoryRegion twi; =20 uint32_t sram_size; uint32_t flash_size; diff --git a/include/hw/i2c/microbit_i2c.h b/include/hw/i2c/microbit_i2c.h new file mode 100644 index 00000000000..aad636127ea --- /dev/null +++ b/include/hw/i2c/microbit_i2c.h @@ -0,0 +1,42 @@ +/* + * Microbit stub for Nordic Semiconductor nRF51 SoC Two-Wire Interface + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2019 Red Hat, Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef MICROBIT_I2C_H +#define MICROBIT_I2C_H + +#include "hw/sysbus.h" +#include "hw/arm/nrf51.h" + +#define NRF51_TWI_TASK_STARTRX 0x000 +#define NRF51_TWI_TASK_STARTTX 0x008 +#define NRF51_TWI_TASK_STOP 0x014 +#define NRF51_TWI_EVENT_STOPPED 0x104 +#define NRF51_TWI_EVENT_RXDREADY 0x108 +#define NRF51_TWI_EVENT_TXDSENT 0x11c +#define NRF51_TWI_REG_ENABLE 0x500 +#define NRF51_TWI_REG_RXD 0x518 +#define NRF51_TWI_REG_TXD 0x51c +#define NRF51_TWI_REG_ADDRESS 0x588 + +#define TYPE_MICROBIT_I2C "microbit.i2c" +#define MICROBIT_I2C(obj) \ + OBJECT_CHECK(MicrobitI2CState, (obj), TYPE_MICROBIT_I2C) + +#define MICROBIT_I2C_NREGS (NRF51_TWI_SIZE / sizeof(uint32_t)) + +typedef struct { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint32_t regs[MICROBIT_I2C_NREGS]; + uint32_t read_idx; +} MicrobitI2CState; + +#endif /* MICROBIT_I2C_H */ diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index a734e7f650e..da67bf6d9d1 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -16,11 +16,13 @@ #include "exec/address-spaces.h" =20 #include "hw/arm/nrf51_soc.h" +#include "hw/i2c/microbit_i2c.h" =20 typedef struct { MachineState parent; =20 NRF51State nrf51; + MicrobitI2CState i2c; } MicrobitMachineState; =20 #define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit") @@ -32,7 +34,9 @@ static void microbit_init(MachineState *machine) { MicrobitMachineState *s =3D MICROBIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mr; Object *soc =3D OBJECT(&s->nrf51); + Object *i2c =3D OBJECT(&s->i2c); =20 sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51), TYPE_NRF51_SOC); @@ -41,6 +45,18 @@ static void microbit_init(MachineState *machine) &error_fatal); object_property_set_bool(soc, true, "realized", &error_fatal); =20 + /* + * Overlap the TWI stub device into the SoC. This is a microbit-speci= fic + * hack until we implement the nRF51 TWI controller properly and the + * magnetometer/accelerometer devices. + */ + sysbus_init_child_obj(OBJECT(machine), "microbit.twi", i2c, + sizeof(s->i2c), TYPE_MICROBIT_I2C); + object_property_set_bool(i2c, true, "realized", &error_fatal); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(i2c), 0); + memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BAS= E, + mr, -1); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, NRF51_SOC(soc)->flash_size); } diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c new file mode 100644 index 00000000000..793f1b0f8ba --- /dev/null +++ b/hw/i2c/microbit_i2c.c @@ -0,0 +1,127 @@ +/* + * Microbit stub for Nordic Semiconductor nRF51 SoC Two-Wire Interface + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * This is a microbit-specific stub for the TWI controller on the nRF51 So= C. + * We don't emulate I2C devices but the firmware probes the + * accelerometer/magnetometer on startup and panics if they are not found. + * Therefore we stub out the probing. + * + * In the future this file could evolve into a full nRF51 TWI controller + * device. + * + * Copyright 2018 Steffen G=C3=B6rtz + * Copyright 2019 Red Hat, Inc. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/i2c/microbit_i2c.h" + +static const uint32_t twi_read_sequence[] =3D {0x5A, 0x5A, 0x40}; + +static uint64_t microbit_i2c_read(void *opaque, hwaddr addr, unsigned int = size) +{ + MicrobitI2CState *s =3D opaque; + uint64_t data =3D 0x00; + + switch (addr) { + case NRF51_TWI_EVENT_STOPPED: + data =3D 0x01; + break; + case NRF51_TWI_EVENT_RXDREADY: + data =3D 0x01; + break; + case NRF51_TWI_EVENT_TXDSENT: + data =3D 0x01; + break; + case NRF51_TWI_REG_RXD: + data =3D twi_read_sequence[s->read_idx]; + if (s->read_idx < G_N_ELEMENTS(twi_read_sequence)) { + s->read_idx++; + } + break; + default: + data =3D s->regs[addr / sizeof(s->regs[0])]; + break; + } + + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u] =3D %" PRIx32 "\= n", + __func__, addr, size, (uint32_t)data); + + + return data; +} + +static void microbit_i2c_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + MicrobitI2CState *s =3D opaque; + + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]= \n", + __func__, addr, data, size); + s->regs[addr / sizeof(s->regs[0])] =3D data; +} + +static const MemoryRegionOps microbit_i2c_ops =3D { + .read =3D microbit_i2c_read, + .write =3D microbit_i2c_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, +}; + +static const VMStateDescription microbit_i2c_vmstate =3D { + .name =3D TYPE_MICROBIT_I2C, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MicrobitI2CState, MICROBIT_I2C_NREGS), + VMSTATE_UINT32(read_idx, MicrobitI2CState), + }, +}; + +static void microbit_i2c_reset(DeviceState *dev) +{ + MicrobitI2CState *s =3D MICROBIT_I2C(dev); + + memset(s->regs, 0, sizeof(s->regs)); + s->read_idx =3D 0; +} + +static void microbit_i2c_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + MicrobitI2CState *s =3D MICROBIT_I2C(dev); + + memory_region_init_io(&s->iomem, OBJECT(s), µbit_i2c_ops, s, + "microbit.twi", NRF51_TWI_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void microbit_i2c_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D µbit_i2c_vmstate; + dc->reset =3D microbit_i2c_reset; + dc->realize =3D microbit_i2c_realize; + dc->desc =3D "Microbit I2C controller"; +} + +static const TypeInfo microbit_i2c_info =3D { + .name =3D TYPE_MICROBIT_I2C, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MicrobitI2CState), + .class_init =3D microbit_i2c_class_init, +}; + +static void microbit_i2c_register_types(void) +{ + type_register_static(µbit_i2c_info); +} + +type_init(microbit_i2c_register_types) --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700213026752.8632642207011; Mon, 28 Jan 2019 10:30:13 -0800 (PST) Received: from localhost ([127.0.0.1]:36625 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBfV-0001Bb-TH for importer@patchew.org; Mon, 28 Jan 2019 13:30:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN9-0002fH-Ft for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN8-0008O0-6M for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:03 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:56061) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN7-0008FY-Rf for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:01 -0500 Received: by mail-wm1-x329.google.com with SMTP id y139so14912860wmc.5 for ; Mon, 28 Jan 2019 10:10:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HVtry8pW5gd4EFWPYzQSKt6Lm5EYVqOWAnwCAHgbRU8=; b=Kjz385sA+AFbqrQFTwI6b4y5jpg4SrUQatXpAwap2twCR7COOTwOhtqdnuj5HRmgqS R2r+YYfhGnV84AK3fPVHkxfJTJt6K2zC6oogHpFTIpPNNRwA56S6f07axXCVPIVa+l/l MnNCe7l2MGLb7OV2ygjdBYiahiHSIA6i/fJcU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HVtry8pW5gd4EFWPYzQSKt6Lm5EYVqOWAnwCAHgbRU8=; b=bBS0N4+bRKEvYl+jv+ynouTT91yuJ180BSgJQCFDQ1jDpvuk8Tmsn6etQX9+ut+qiw s9OU4WHQ/5bj77ssN5GxbWiUb+7oz4Wui9RPsytKDAbIki5Q4qWYfAhv0Gi2Ye/n7/Lq K7Ss+EDxgV8kzr+k8JMJLNhaP3TJrnYL+bNRYdM5BAzvDMw8HwmZkmMgC9obVZXj3daB Yr67PtDLeEc0dTWZhANgoZi6+vfyfnqVoRlAzUBeAy7Mgmx1l5bxsEdB98AD87cEoig1 cteNl3u+rx1sY6rwirYCY9soegbuLV/vuDMMk/vd0bKY5c+480Pbleh74EsXHyF2dVu0 F/aA== X-Gm-Message-State: AJcUukeKbVUtE3p92tPGVd7K+Agtr2T/d5FCXTIHlzfnwY4Jx/gAyxOq Qs5iYuc0LzcrKThDQOkLG0nRbrvsBh/QpA== X-Google-Smtp-Source: ALg8bN7kNiGK1Lq6L+Z6lHeJLzO2OSV8oupYZHSR1WBztsOefgV0xpYSblFMEAcNP68/TaLKMtCnmg== X-Received: by 2002:a1c:c543:: with SMTP id v64mr17240613wmf.123.1548699056286; Mon, 28 Jan 2019 10:10:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:26 +0000 Message-Id: <20190128181047.20781-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 Subject: [Qemu-devel] [PULL 05/26] tests/microbit-test: add TWI stub device test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stefan Hajnoczi This test verifies that we read back the expected I2C WHO_AM_I register values for the accelerometer/magnetometer. Signed-off-by: Stefan Hajnoczi Message-id: 20190110094020.18354-3-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/microbit-test.c | 44 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index 0c125535f64..dcdc0cd41a5 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -21,6 +21,49 @@ #include "hw/arm/nrf51.h" #include "hw/gpio/nrf51_gpio.h" #include "hw/timer/nrf51_timer.h" +#include "hw/i2c/microbit_i2c.h" + +/* Read a byte from I2C device at @addr from register @reg */ +static uint32_t i2c_read_byte(uint32_t addr, uint32_t reg) +{ + uint32_t val; + + writel(NRF51_TWI_BASE + NRF51_TWI_REG_ADDRESS, addr); + writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STARTTX, 1); + writel(NRF51_TWI_BASE + NRF51_TWI_REG_TXD, reg); + val =3D readl(NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); + g_assert_cmpuint(val, =3D=3D, 1); + writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); + + writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STARTRX, 1); + val =3D readl(NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); + g_assert_cmpuint(val, =3D=3D, 1); + val =3D readl(NRF51_TWI_BASE + NRF51_TWI_REG_RXD); + writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); + + return val; +} + +static void test_microbit_i2c(void) +{ + uint32_t val; + + /* We don't program pins/irqs but at least enable the device */ + writel(NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 5); + + /* MMA8653 magnetometer detection */ + val =3D i2c_read_byte(0x3A, 0x0D); + g_assert_cmpuint(val, =3D=3D, 0x5A); + + val =3D i2c_read_byte(0x3A, 0x0D); + g_assert_cmpuint(val, =3D=3D, 0x5A); + + /* LSM303 accelerometer detection */ + val =3D i2c_read_byte(0x3C, 0x4F); + g_assert_cmpuint(val, =3D=3D, 0x40); + + writel(NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 0); +} =20 static void test_nrf51_gpio(void) { @@ -247,6 +290,7 @@ int main(int argc, char **argv) =20 qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); + qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); =20 ret =3D g_test_run(); =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700110563253.90389980894952; Mon, 28 Jan 2019 10:28:30 -0800 (PST) Received: from localhost ([127.0.0.1]:36603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBdz-0008G6-H7 for importer@patchew.org; Mon, 28 Jan 2019 13:28:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN8-0002eY-Rb for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN7-0008MW-N9 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:02 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:36631) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN5-0008H2-Om for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:00 -0500 Received: by mail-wr1-x429.google.com with SMTP id u4so19163413wrp.3 for ; Mon, 28 Jan 2019 10:10:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=168FJ/UByMoqmKTqzxbvuPaUazSmh6HplX+UPK0CMJE=; b=T21C3PQI5GmJ71sQUU52I0ZIR/bNwOYnXyzk1q6NsUEf7IRxwIMK8KNfmSYf5dKN2d gtGZC8H0vcgkTefXswY7KIDmk0ql1QSCZqD+bnp316P98P1rGRtUeoNpp656VdMvri0E MjuaeIayzYgv1wdlrRLtlcvALroKj+QOr3HQg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=168FJ/UByMoqmKTqzxbvuPaUazSmh6HplX+UPK0CMJE=; b=X+jk26GfTNy7nPxdqaQ3jyHL/g+7bl5LhDQapdd6YoZm2IohBFMbtwR0UtCTOSFLYr yM+FwUSUd1/PRi4j6M6wdflRol8RccU5OStpg7S8gDGK+wjSlN2fWMvdk97zhT0el4mx kfUkTKaRAkcb2e74gV/9QSN2pqDhhn1Z7lTbHP9A/cgxz5ODOc0eNq5G7oK0g76ocfPa vlRpMk885/snkO/cVw33nUMdybSsdwxvsqN4L7S9PBC/C96ZcfEwAWG88aLRwmfFrNWL GratCT49xuHOHIOBoJ0klpvw2OudVByBE5yCcMpFJedMZ1wCGRl3B9EA7EsexeRVndm7 BAZw== X-Gm-Message-State: AJcUuke1T4nVzUf/79HFD1SxeEDbgIjmzTSJ6SfHRi8/vGUoFnPbVQqK EuyeCreeRGICbYuQVN6CWfoK9aBPWrIgSQ== X-Google-Smtp-Source: ALg8bN5GsmqbulUItRzVrvMHLdkdIYh0irRk3ZL0q4uVB1cPLQ8Yp9DSzYNGtlnbRF3AoRFoyxLVuw== X-Received: by 2002:adf:82a4:: with SMTP id 33mr21482734wrc.252.1548699057443; Mon, 28 Jan 2019 10:10:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:27 +0000 Message-Id: <20190128181047.20781-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 06/26] exec.c: Use correct attrs in cpu_memory_rw_debug() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) In the softmmu version of cpu_memory_rw_debug(), we ask the CPU for the attributes to use for the virtual memory access, and we correctly use those to identify the address space index. However, we were not passing them in to the address_space_write_rom() and address_space_rw() functions. The effect of this was that a memory access from the gdbstub to a device which had behaviour that was sensitive to the memory attributes (such as some ARMv8M NVIC registers) was incorrectly always performed as if non-secure, rather than using the right security state for the CPU's current state. Fixes: https://bugs.launchpad.net/qemu/+bug/1812091 Signed-off-by: Peter Maydell Reviewed-by: Stefano Garzarella Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190117133834.7480-1-peter.maydell@linaro.org --- exec.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/exec.c b/exec.c index 895449f9261..9557a4e523c 100644 --- a/exec.c +++ b/exec.c @@ -3882,12 +3882,10 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong= addr, phys_addr +=3D (addr & ~TARGET_PAGE_MASK); if (is_write) { address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, - MEMTXATTRS_UNSPECIFIED, - buf, l); + attrs, buf, l); } else { address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, - MEMTXATTRS_UNSPECIFIED, - buf, l, 0); + attrs, buf, l, 0); } len -=3D l; buf +=3D l; --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701140741383.92701450563527; Mon, 28 Jan 2019 10:45:40 -0800 (PST) Received: from localhost ([127.0.0.1]:36875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBuT-0005r0-Jh for importer@patchew.org; Mon, 28 Jan 2019 13:45:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40940) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN9-0002fX-OB for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN8-0008OQ-8T for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:03 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41234) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN7-0008Hl-U0 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:02 -0500 Received: by mail-wr1-x42a.google.com with SMTP id x10so19122664wrs.8 for ; Mon, 28 Jan 2019 10:10:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sgxndn8yvcv9jGeYe3WGmBhKDBlYqLQWYGqaHVEw8D8=; b=FkHEFBk81DCp4GMw5yLodv5SZeUxP2ZDxDZkrnevSk3pWROmCS5zEjhOr9DPXhxJ2W 7rlzcDwCGe0f19Z3Pq3TZrafY9h0dKC9qA9CZZM8RfNe6YfjNw+LNyj5FamK2muCu7b0 PuoCFyMSqq80X54UFBAvj4lOk8klDl/sLS7y4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sgxndn8yvcv9jGeYe3WGmBhKDBlYqLQWYGqaHVEw8D8=; b=ajXedJ8Xcyjkuc27oJrzudmA0i652QKcxF7i54iAJUM/hcK1kq+X+Cv7JD/nLAgI17 QCf8KvGV0xCgDDsoViJyPomUrA13ajk4aA9AtUK5TfRYoEWIOnxb2BS8vzm9xadtTfu7 TKs/igpiK/ae/o1uagCaFCAFqzRWvob6OJ361nxbWUAeutQdoqTfyEoS+hkjf/CNloTv dmMwjVJpuLDzo0VRiHwAiS0hpV/S/KJNUDjhMFB3YgtMzdi2Ty9Kqrl3u2gQ8njcnsIg Ecuk8Z8eijcDhYVSzsl9rwvWJyWMVX6L6fzTeR4d70nWoHbUn9o5JDORIZN3EXkH1ZEX 7G2g== X-Gm-Message-State: AJcUukdwYc1gApYaGRx/ACubFv2XU/ZIB3XsXdIq+FGyk7nBq3NW0da2 F09JV+malWKGjnDsFA3Zvsg6moKruDUVEQ== X-Google-Smtp-Source: ALg8bN6EWRHdEl49vSyDWiT3eoUdeerVSQMR3FRgT57kA8WFfi8Fqb3XDFHO/bW2s5rXVO0V+TPCiw== X-Received: by 2002:adf:f903:: with SMTP id b3mr23718000wrr.82.1548699058518; Mon, 28 Jan 2019 10:10:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:28 +0000 Message-Id: <20190128181047.20781-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 07/26] accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In cpu_signal_handler() for aarch64 hosts, currently we parse the faulting instruction to see if it is a load or a store. Since the 3.16 kernel (~2014), the kernel has provided us with the syndrome register for a fault, which includes the WnR bit. Use this instead if it is present, only falling back to instruction parsing if not. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190108180014.32386-1-peter.maydell@linaro.org --- accel/tcg/user-exec.c | 66 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 52 insertions(+), 14 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 941295ea49b..66cc818e3f3 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -479,28 +479,66 @@ int cpu_signal_handler(int host_signum, void *pinfo, =20 #elif defined(__aarch64__) =20 +#ifndef ESR_MAGIC +/* Pre-3.16 kernel headers don't have these, so provide fallback definitio= ns */ +#define ESR_MAGIC 0x45535201 +struct esr_context { + struct _aarch64_ctx head; + uint64_t esr; +}; +#endif + +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info =3D pinfo; ucontext_t *uc =3D puc; uintptr_t pc =3D uc->uc_mcontext.pc; - uint32_t insn =3D *(uint32_t *)pc; bool is_write; + struct _aarch64_ctx *hdr; + struct esr_context const *esrctx =3D NULL; =20 - /* XXX: need kernel patch to get write flag faster. */ - is_write =3D ( (insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ - || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ - || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ - || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ - || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ - || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 */ - || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128bit */ - /* Ingore bits 10, 11 & 21, controlling indexing. */ - || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-12 */ - || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128bit */ - /* Ignore bits 23 & 24, controlling indexing. */ - || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,14-16= */ + /* Find the esr_context, which has the WnR bit in it */ + for (hdr =3D first_ctx(uc); hdr->magic; hdr =3D next_ctx(hdr)) { + if (hdr->magic =3D=3D ESR_MAGIC) { + esrctx =3D (struct esr_context const *)hdr; + break; + } + } =20 + if (esrctx) { + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */ + uint64_t esr =3D esrctx->esr; + is_write =3D extract32(esr, 27, 5) =3D=3D 0x12 && extract32(esr, 6= , 1) =3D=3D 1; + } else { + /* + * Fall back to parsing instructions; will only be needed + * for really ancient (pre-3.16) kernels. + */ + uint32_t insn =3D *(uint32_t *)pc; + + is_write =3D ((insn & 0xbfff0000) =3D=3D 0x0c000000 /* C3.3.1 */ + || (insn & 0xbfe00000) =3D=3D 0x0c800000 /* C3.3.2 */ + || (insn & 0xbfdf0000) =3D=3D 0x0d000000 /* C3.3.3 */ + || (insn & 0xbfc00000) =3D=3D 0x0d800000 /* C3.3.4 */ + || (insn & 0x3f400000) =3D=3D 0x08000000 /* C3.3.6 */ + || (insn & 0x3bc00000) =3D=3D 0x39000000 /* C3.3.13 = */ + || (insn & 0x3fc00000) =3D=3D 0x3d800000 /* ... 128b= it */ + /* Ignore bits 10, 11 & 21, controlling indexing. */ + || (insn & 0x3bc00000) =3D=3D 0x38000000 /* C3.3.8-1= 2 */ + || (insn & 0x3fe00000) =3D=3D 0x3c800000 /* ... 128b= it */ + /* Ignore bits 23 & 24, controlling indexing. */ + || (insn & 0x3a400000) =3D=3D 0x28000000); /* C3.3.7,1= 4-16 */ + } return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700285840626.8526930257573; Mon, 28 Jan 2019 10:31:25 -0800 (PST) Received: from localhost ([127.0.0.1]:36660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBgk-0002JA-GJ for importer@patchew.org; Mon, 28 Jan 2019 13:31:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40915) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBN9-0002f7-96 for qemu-devel@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:10:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ne3NlB5hKc2o73d3UhVcdUrs9dAavmHG8QKv1I9DCwY=; b=FqV0z5mQCpPWmaM7rNYdygZ7uNsGFo8dqaOtzc+9t6fgCL+TmQyfCoxcBH9DwelihS IU8X5B4Z9jtsAg7Cram9CSQUxFrgBw7FuCUJkaLoZOl2axEjMCDwnhhjl4JLsdLq+duF k/w1jK/TwWx9EQQ6VYC8inxRKrJ5vManyihUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ne3NlB5hKc2o73d3UhVcdUrs9dAavmHG8QKv1I9DCwY=; b=EMMSVdIvQbFKw61oC7zsrbV4hmPkkjKTM1akwH4jtEu4MFlGDxuJBovCOuPnbeL3X4 kLJUupVBAWtbF2qskn/8PTcwhLpyWyx3dhAU2xRNScORepJGlPPgxXmGtp8RWqCP9frJ 1p/XJM1I/SSnWD+I5DoBYhT1pDc6TW+DI1g8QMnnClUrmOzBPQzVngn1Hg32veHPjszu E4EREgNVAdupkFCtXLFQlCk4YOgB7wlApe8ELC/FAHdvN0e0vVd0//q8VsJCh93Sa7SO COm3390CeJvmdRHY0e22SyWQ7tgYUvkzA44gMFFYgChpcZxX4exTNwmBAMeESpAkoOiI 6Hsg== X-Gm-Message-State: AJcUukd9k6w5HqzpV1nFmeUtxChy9dy3wVRa3zUFcfMckxP+Xy2fx+/v Zb04pnI4sQS5LQVnDtj0fVSijmcO7NVCtA== X-Google-Smtp-Source: ALg8bN6RZSn6A+pQa8bHGWl0aW3ctiXofaAjHo0Wbot/gHkp8BCgusYT7S4rMz/enNG672rE7S5tUA== X-Received: by 2002:a5d:5607:: with SMTP id l7mr22999574wrv.25.1548699059578; Mon, 28 Jan 2019 10:10:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:29 +0000 Message-Id: <20190128181047.20781-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [PULL 08/26] MAINTAINERS: update microbit ARM board files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Stefan Hajnoczi New source files were added without corresponding ./MAINTAINERS file entries. Let's get things up to date. Reviewed-by: Thomas Huth Signed-off-by: Stefan Hajnoczi Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190123183352.11025-1-stefanha@redhat.com Signed-off-by: Peter Maydell --- MAINTAINERS | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 59e1f24d680..b334b539797 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -829,9 +829,11 @@ M: Joel Stanley M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained -F: hw/arm/nrf51_soc.c -F: hw/arm/microbit.c -F: include/hw/arm/nrf51_soc.h +F: hw/*/nrf51*.c +F: hw/*/microbit*.c +F: include/hw/*/nrf51*.h +F: include/hw/*/microbit*.h +F: tests/microbit-test.c =20 CRIS Machines ------------- --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700474447630.5143683864655; Mon, 28 Jan 2019 10:34:34 -0800 (PST) Received: from localhost ([127.0.0.1]:36688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBjt-0004iA-9m for importer@patchew.org; Mon, 28 Jan 2019 13:34:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNA-0002g8-9O for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN8-0008PY-Py for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:04 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38717) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN8-0008NJ-I4 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:02 -0500 Received: by mail-wm1-x343.google.com with SMTP id m22so15036222wml.3 for ; Mon, 28 Jan 2019 10:11:02 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.10.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ori3cO87FQgSnTdpKDHLNY2jwd5cT8Lr+GZNSeVH0Ck=; b=bDIzp6OGG0DR79uU7qH9JOn9Y6dhOZ32wyZyfYgMqvehiS9B1OwDRRTa/3OHDx0t6h Gva76ZPqCIx59q5FyOszF6H558QgVgXr24LGaAFy5STpoycQUUexrMACwQL7cQDPxkYx svSx4ixVpgCAwzC7E//Yk8OJtBcQD2ttu+Y8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ori3cO87FQgSnTdpKDHLNY2jwd5cT8Lr+GZNSeVH0Ck=; b=tUdXWx15Kz3BnGbPuf1OnViAPUCbt2lKJvBQBkQ4SVjrUY96nljQDh3z8Yxsv0OYRX onF8g4MkaRWhVXKBqOV4ioejYpLbvrzSMB7c2MO5W4BId8Xk8V17iq+kM1SMIadidjFj RbtmZTAD8cqlmzd4v54BEpmRfskd2gffF7q+KJ4ACR+mmEsQ0V4Ad/ALhCEsY2Z78WxH gfVekALA7GorBNyAj6G/XEHtWgW2obCg7mOFz5NHrBWQzpA28PB7d6b5OY+zgnqvDhT1 r5dGveLAJNSF1dKayPqnlR857ey58Y+hmBreuzXgkomQGfHFLuNx0/1cl3wDyrAqiEzu UKug== X-Gm-Message-State: AJcUukcEQZ2f7C/2vDv2EOHQG29CNMijnx1/P/z8TNtAKJinaw+0dc+7 Mzho2Jf99uoE98Gvc4gwRM/wrBew4+2Vew== X-Google-Smtp-Source: ALg8bN4QNTYXlP0CwVaJLr1qhjfXr+AuPwGEkwFGGQ6yvW3A0fDo9GrazcKs9v9fKyC8gEv7O+n4AA== X-Received: by 2002:a1c:4c10:: with SMTP id z16mr18812215wmf.117.1548699061051; Mon, 28 Jan 2019 10:11:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:30 +0000 Message-Id: <20190128181047.20781-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 09/26] target/arm: Don't clear supported PMU events when initializing PMCEID1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay OS A bug was introduced during a respin of: commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20190123195814.29253-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 +++++------ target/arm/cpu.c | 3 +-- target/arm/helper.c | 27 ++++++++++++++++----------- 3 files changed, 22 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff81db420d5..b8161cb6d73 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1012,14 +1012,13 @@ void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 /* - * get_pmceid - * @env: CPUARMState - * @which: which PMCEID register to return (0 or 1) + * pmu_init + * @cpu: ARMCPU * - * Return the PMCEID[01]_EL0 register values corresponding to the counters - * which are supported given the current configuration + * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal s= tate + * for the current configuration */ -uint64_t get_pmceid(CPUARMState *env, unsigned which); +void pmu_init(ARMCPU *cpu); =20 /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e1f3dd637a..d6da3f4fed3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1039,8 +1039,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - cpu->pmceid0 =3D get_pmceid(&cpu->env, 0); - cpu->pmceid1 =3D get_pmceid(&cpu->env, 1); + pmu_init(cpu); =20 if (!kvm_enabled()) { arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); diff --git a/target/arm/helper.c b/target/arm/helper.c index 676059cb386..66faebea8ec 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1090,22 +1090,24 @@ static const pm_event pm_events[] =3D { static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 /* - * Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicat= ed by - * 'which'). We also use it to build a map of ARM event numbers to indices= in - * our pm_events array. + * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map + * of ARM event numbers to indices in our pm_events array. * * Note: Events in the 0x40XX range are not currently supported. */ -uint64_t get_pmceid(CPUARMState *env, unsigned which) +void pmu_init(ARMCPU *cpu) { - uint64_t pmceid =3D 0; unsigned int i; =20 - assert(which <=3D 1); - + /* + * Empty supported_event_map and cpu->pmceid[01] before adding support= ed + * events to them + */ for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { supported_event_map[i] =3D UNSUPPORTED_EVENT; } + cpu->pmceid0 =3D 0; + cpu->pmceid1 =3D 0; =20 for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { const pm_event *cnt =3D &pm_events[i]; @@ -1113,13 +1115,16 @@ uint64_t get_pmceid(CPUARMState *env, unsigned whic= h) /* We do not currently support events in the 0x40xx range */ assert(cnt->number <=3D 0x3f); =20 - if ((cnt->number & 0x20) =3D=3D (which << 6) && - cnt->supported(env)) { - pmceid |=3D (1 << (cnt->number & 0x1f)); + if (cnt->supported(&cpu->env)) { supported_event_map[cnt->number] =3D i; + uint64_t event_mask =3D 1 << (cnt->number & 0x1f); + if (cnt->number & 0x20) { + cpu->pmceid1 |=3D event_mask; + } else { + cpu->pmceid0 |=3D event_mask; + } } } - return pmceid; } =20 /* --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700658147913.1063441202662; Mon, 28 Jan 2019 10:37:38 -0800 (PST) Received: from localhost ([127.0.0.1]:36751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBmm-0007DL-4L for importer@patchew.org; Mon, 28 Jan 2019 13:37:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40982) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNA-0002gd-Oo for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBN9-0008Rf-RI for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:04 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:44063) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBN9-0008Pf-JS for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:03 -0500 Received: by mail-wr1-x436.google.com with SMTP id z5so19119239wrt.11 for ; Mon, 28 Jan 2019 10:11:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=07yrPBcrxdQgo8XLbgpxSvssxeoja/CdPeRpQD42bkw=; b=dglg2Cd9MKsrBaLqgl8plzNMQddPMEJhKwOrVJD5iHUia8bfBszLaVH8o1zrHdQHhF sPSi6BS1HO+RuDmXHlzJspfRoFrUqOTgvx9hWgJA7FdithkKyNxtMcctNH1a2S/yIh1F +qIhT47sMMPgPFoLsTVTR4OBNMWM4dvJsTFmY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=07yrPBcrxdQgo8XLbgpxSvssxeoja/CdPeRpQD42bkw=; b=B07/n74sBcbsZoNjUJWWX9SIRiVFZKiyuYzwyPrX3+pO5DtXUk+SCi6PiTwXTxtBDL QNVwt9xV8QIDD8cWsdvUVRSZpLoOtRNyu9Q1vkhMgqwSTT60GsWCDjEk26r9k/06hAHp /fF+RXNYWF9SbU6FI5q8XRF8uyhN6tSGPRtDFxHjzuLuN89BTTdS77/Hnbz23fzwbFrS sygfQrjsxbISx1homasja+tFIqV5rmcyXf+NPaA8Fvy05+gi59sjcXIKPGoME8xu7fTX vsBDvouhE9ZOBt87TPEg1ROn9TWywzx80F/hBPnB5NkVh4Vsf6lsLCZsSgYpqLZxSPZ5 qVOg== X-Gm-Message-State: AJcUukcDFuMwTT/XoXcEkRZflIqCA1urGFnqYcHRVY6d6UdeBCBgR2Wm 6hvYBLJnyd5lGLyCYFaslJ7MZ5Ek4e5L9g== X-Google-Smtp-Source: ALg8bN7wZZu2mTSjHMMoTbPIEn9w6SkxowDKKH4ziyQ/tWFZbOWD45NowwoqnYRxZuwsg1Fh9ctbWg== X-Received: by 2002:adf:891a:: with SMTP id s26mr22571309wrs.44.1548699062245; Mon, 28 Jan 2019 10:11:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:31 +0000 Message-Id: <20190128181047.20781-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 10/26] memory: add memory_region_flush_rom_device() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stefan Hajnoczi ROM devices go via MemoryRegionOps->write() callbacks for write operations and do not dirty/invalidate that memory. Device emulation must be able to mark memory ranges that have been modified internally (e.g. using memory_region_get_ram_ptr()). Introduce the memory_region_flush_rom_device() API for this purpose. Signed-off-by: Stefan Hajnoczi Message-id: 20190123212234.32068-2-stefanha@redhat.com Reviewed-by: Peter Maydell [PMM: fix block comment style] Signed-off-by: Peter Maydell --- include/exec/memory.h | 18 ++++++++++++++++++ exec.c | 13 +++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index cd2f209b64e..abe9cc79c0d 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1344,6 +1344,24 @@ bool memory_region_snapshot_get_dirty(MemoryRegion *= mr, void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr, hwaddr size, unsigned client); =20 +/** + * memory_region_flush_rom_device: Mark a range of pages dirty and invalid= ate + * TBs (for self-modifying code). + * + * The MemoryRegionOps->write() callback of a ROM device must use this fun= ction + * to mark byte ranges that have been modified internally, such as by dire= ctly + * accessing the memory returned by memory_region_get_ram_ptr(). + * + * This function marks the range dirty and invalidates TBs so that TCG can + * detect self-modifying code. + * + * @mr: the region being flushed. + * @addr: the start, relative to the start of the region, of the range bei= ng + * flushed. + * @size: the size, in bytes, of the range being flushed. + */ +void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr = size); + /** * memory_region_set_readonly: Turn a memory region read-only (or read-wri= te) * diff --git a/exec.c b/exec.c index 9557a4e523c..da3e635f91b 100644 --- a/exec.c +++ b/exec.c @@ -3162,6 +3162,19 @@ static void invalidate_and_set_dirty(MemoryRegion *m= r, hwaddr addr, cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); } =20 +void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr = size) +{ + /* + * In principle this function would work on other memory region types = too, + * but the ROM device use case is the only one where this operation is + * necessary. Other memory regions should use the + * address_space_read/write() APIs. + */ + assert(memory_region_is_romd(mr)); + + invalidate_and_set_dirty(mr, addr, size); +} + static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) { unsigned access_size_max =3D mr->ops->valid.max_access_size; --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700583734582.8925022334504; Mon, 28 Jan 2019 10:36:23 -0800 (PST) Received: from localhost ([127.0.0.1]:36745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBlc-0006IW-GX for importer@patchew.org; Mon, 28 Jan 2019 13:36:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41026) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNF-0002nS-5m for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNB-0008Uf-Lo for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:09 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:34047) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNB-0008T1-Bi for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:05 -0500 Received: by mail-wm1-x32d.google.com with SMTP id y185so11062630wmd.1 for ; Mon, 28 Jan 2019 10:11:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SWfDOeb785mNMZYScilr3ttyuhkCRoEJgLu+ZhAMVNk=; b=Envvh7xCL/eEpDFCD6Yt0v4dibYq6PJz6+c8TUvLn725JKpobJ3rOlq0if9vYAkzaE dN2vj9s7jUq7yTZyJ+0UhQvITOTKGoPQc6Erp8PWiOWcV9Uo00XD/diCYN4vfNRPGOIf FlV7IzxmescZLvEvQeYGqqsk5KmQxmXqu9dkg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SWfDOeb785mNMZYScilr3ttyuhkCRoEJgLu+ZhAMVNk=; b=LCJPR8ibXpfSrhTzqeLpNrGGMeHp5Q7oS0lcPS9ZX7n4EW2GdbNvTKI/q9aWSNoOQm Vbwb6p9s6GzQc6BxfVBQnDTY6KyBOdscj/XhbU6VSs7EBaGbr3tiTiPvWM5b/0c1lbwJ 3DgapHRaXK7viZYOEbtNy+u/evCjwoN2dQ65TQLCtoni4ZoZpAkfeQDnCICZTcO6sa7h EyGMQXkFjoSKGRcV2sjnb1JVdzraxZ35T5n/AqWBbMhkttBO4kAZrtBPRqu7CH+9TPeR zWSyP/wBRYeldJ3FTdjkZymhvvKVV7c6mC7wzamIbU9cZgfKzIC+chRsyAsNuRL6RIsq 4EtA== X-Gm-Message-State: AJcUukfs7xSRMz2AG8GCf+O1QPMLQqs1M55mMoGmJufRLXk1Fe/OJ2me 2VIg5EK6VjSD23UsgArHDF2lcdQVpxPkNA== X-Google-Smtp-Source: ALg8bN4Rv8p+eNfhMy+GcyICQzu95kSWrXe5yF0MhlcEKcQG+YVLf7FfES2Fq6MQWBC3QbjE/Fu6RQ== X-Received: by 2002:a1c:a3c3:: with SMTP id m186mr17921345wme.16.1548699063833; Mon, 28 Jan 2019 10:11:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:32 +0000 Message-Id: <20190128181047.20781-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d Subject: [Qemu-devel] [PULL 11/26] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz The nRF51 contains three regions of non-volatile memory (NVM): - CODE (R/W): contains code - FICR (R): Factory information like code size, chip id etc. - UICR (R/W): Changeable configuration data. Lock bits, Code protection configuration, Bootloader address, Nordic SoftRadio configuration, Firmware configuration. Read and write access to the memories is managed by the Non-volatile memory controller. Memory schema: [ CPU ] -+- [ NVM, either FICR, UICR or CODE ] | | \- [ NVMC ] Signed-off-by: Steffen G=C3=B6rtz Signed-off-by: Stefan Hajnoczi Message-id: 20190123212234.32068-4-stefanha@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/nvram/Makefile.objs | 1 + include/hw/nvram/nrf51_nvm.h | 64 ++++++ hw/nvram/nrf51_nvm.c | 381 +++++++++++++++++++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 include/hw/nvram/nrf51_nvm.h create mode 100644 hw/nvram/nrf51_nvm.c diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index b318e53a434..26f7b4ca357 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -5,3 +5,4 @@ common-obj-y +=3D fw_cfg.o common-obj-y +=3D chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) +=3D mac_nvram.o obj-$(CONFIG_PSERIES) +=3D spapr_nvram.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_nvm.o diff --git a/include/hw/nvram/nrf51_nvm.h b/include/hw/nvram/nrf51_nvm.h new file mode 100644 index 00000000000..0a8b41b3589 --- /dev/null +++ b/include/hw/nvram/nrf51_nvm.h @@ -0,0 +1,64 @@ +/* + * Nordic Semiconductor nRF51 non-volatile memory + * + * It provides an interface to erase regions in flash memory. + * Furthermore it provides the user and factory information registers. + * + * QEMU interface: + * + sysbus MMIO regions 0: NVMC peripheral registers + * + sysbus MMIO regions 1: FICR peripheral registers + * + sysbus MMIO regions 2: UICR peripheral registers + * + flash-size property: flash size in bytes. + * + * Accuracy of the peripheral model: + * + Code regions (MPU configuration) are disregarded. + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + * + */ +#ifndef NRF51_NVM_H +#define NRF51_NVM_H + +#include "hw/sysbus.h" +#define TYPE_NRF51_NVM "nrf51_soc.nvm" +#define NRF51_NVM(obj) OBJECT_CHECK(NRF51NVMState, (obj), TYPE_NRF51_NVM) + +#define NRF51_UICR_FIXTURE_SIZE 64 + +#define NRF51_NVMC_SIZE 0x1000 + +#define NRF51_NVMC_READY 0x400 +#define NRF51_NVMC_READY_READY 0x01 +#define NRF51_NVMC_CONFIG 0x504 +#define NRF51_NVMC_CONFIG_MASK 0x03 +#define NRF51_NVMC_CONFIG_WEN 0x01 +#define NRF51_NVMC_CONFIG_EEN 0x02 +#define NRF51_NVMC_ERASEPCR1 0x508 +#define NRF51_NVMC_ERASEPCR0 0x510 +#define NRF51_NVMC_ERASEALL 0x50C +#define NRF51_NVMC_ERASEUICR 0x514 +#define NRF51_NVMC_ERASE 0x01 + +#define NRF51_UICR_SIZE 0x100 + +typedef struct NRF51NVMState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + MemoryRegion ficr; + MemoryRegion uicr; + MemoryRegion flash; + + uint32_t uicr_content[NRF51_UICR_FIXTURE_SIZE]; + uint32_t flash_size; + uint32_t *storage; + + uint32_t config; + +} NRF51NVMState; + + +#endif diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c new file mode 100644 index 00000000000..e51228d6698 --- /dev/null +++ b/hw/nvram/nrf51_nvm.c @@ -0,0 +1,381 @@ +/* + * Nordic Semiconductor nRF51 non-volatile memory + * + * It provides an interface to erase regions in flash memory. + * Furthermore it provides the user and factory information registers. + * + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * + * See nRF51 reference manual and product sheet sections: + * + Non-Volatile Memory Controller (NVMC) + * + Factory Information Configuration Registers (FICR) + * + User Information Configuration Registers (UICR) + * + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "exec/address-spaces.h" +#include "hw/arm/nrf51.h" +#include "hw/nvram/nrf51_nvm.h" + +/* + * FICR Registers Assignments + * CODEPAGESIZE 0x010 + * CODESIZE 0x014 + * CLENR0 0x028 + * PPFC 0x02C + * NUMRAMBLOCK 0x034 + * SIZERAMBLOCKS 0x038 + * SIZERAMBLOCK[0] 0x038 + * SIZERAMBLOCK[1] 0x03C + * SIZERAMBLOCK[2] 0x040 + * SIZERAMBLOCK[3] 0x044 + * CONFIGID 0x05C + * DEVICEID[0] 0x060 + * DEVICEID[1] 0x064 + * ER[0] 0x080 + * ER[1] 0x084 + * ER[2] 0x088 + * ER[3] 0x08C + * IR[0] 0x090 + * IR[1] 0x094 + * IR[2] 0x098 + * IR[3] 0x09C + * DEVICEADDRTYPE 0x0A0 + * DEVICEADDR[0] 0x0A4 + * DEVICEADDR[1] 0x0A8 + * OVERRIDEEN 0x0AC + * NRF_1MBIT[0] 0x0B0 + * NRF_1MBIT[1] 0x0B4 + * NRF_1MBIT[2] 0x0B8 + * NRF_1MBIT[3] 0x0BC + * NRF_1MBIT[4] 0x0C0 + * BLE_1MBIT[0] 0x0EC + * BLE_1MBIT[1] 0x0F0 + * BLE_1MBIT[2] 0x0F4 + * BLE_1MBIT[3] 0x0F8 + * BLE_1MBIT[4] 0x0FC + */ +static const uint32_t ficr_content[64] =3D { + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000400, + 0x00000100, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000002, 0x00002000, + 0x00002000, 0x00002000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000003, + 0x12345678, 0x9ABCDEF1, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF +}; + +static uint64_t ficr_read(void *opaque, hwaddr offset, unsigned int size) +{ + assert(offset < sizeof(ficr_content)); + return ficr_content[offset / 4]; +} + +static void ficr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + /* Intentionally do nothing */ +} + +static const MemoryRegionOps ficr_ops =3D { + .read =3D ficr_read, + .write =3D ficr_write, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + +/* + * UICR Registers Assignments + * CLENR0 0x000 + * RBPCONF 0x004 + * XTALFREQ 0x008 + * FWID 0x010 + * BOOTLOADERADDR 0x014 + * NRFFW[0] 0x014 + * NRFFW[1] 0x018 + * NRFFW[2] 0x01C + * NRFFW[3] 0x020 + * NRFFW[4] 0x024 + * NRFFW[5] 0x028 + * NRFFW[6] 0x02C + * NRFFW[7] 0x030 + * NRFFW[8] 0x034 + * NRFFW[9] 0x038 + * NRFFW[10] 0x03C + * NRFFW[11] 0x040 + * NRFFW[12] 0x044 + * NRFFW[13] 0x048 + * NRFFW[14] 0x04C + * NRFHW[0] 0x050 + * NRFHW[1] 0x054 + * NRFHW[2] 0x058 + * NRFHW[3] 0x05C + * NRFHW[4] 0x060 + * NRFHW[5] 0x064 + * NRFHW[6] 0x068 + * NRFHW[7] 0x06C + * NRFHW[8] 0x070 + * NRFHW[9] 0x074 + * NRFHW[10] 0x078 + * NRFHW[11] 0x07C + * CUSTOMER[0] 0x080 + * CUSTOMER[1] 0x084 + * CUSTOMER[2] 0x088 + * CUSTOMER[3] 0x08C + * CUSTOMER[4] 0x090 + * CUSTOMER[5] 0x094 + * CUSTOMER[6] 0x098 + * CUSTOMER[7] 0x09C + * CUSTOMER[8] 0x0A0 + * CUSTOMER[9] 0x0A4 + * CUSTOMER[10] 0x0A8 + * CUSTOMER[11] 0x0AC + * CUSTOMER[12] 0x0B0 + * CUSTOMER[13] 0x0B4 + * CUSTOMER[14] 0x0B8 + * CUSTOMER[15] 0x0BC + * CUSTOMER[16] 0x0C0 + * CUSTOMER[17] 0x0C4 + * CUSTOMER[18] 0x0C8 + * CUSTOMER[19] 0x0CC + * CUSTOMER[20] 0x0D0 + * CUSTOMER[21] 0x0D4 + * CUSTOMER[22] 0x0D8 + * CUSTOMER[23] 0x0DC + * CUSTOMER[24] 0x0E0 + * CUSTOMER[25] 0x0E4 + * CUSTOMER[26] 0x0E8 + * CUSTOMER[27] 0x0EC + * CUSTOMER[28] 0x0F0 + * CUSTOMER[29] 0x0F4 + * CUSTOMER[30] 0x0F8 + * CUSTOMER[31] 0x0FC + */ + +static uint64_t uicr_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + assert(offset < sizeof(s->uicr_content)); + return s->uicr_content[offset / 4]; +} + +static void uicr_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + assert(offset < sizeof(s->uicr_content)); + s->uicr_content[offset / 4] =3D value; +} + +static const MemoryRegionOps uicr_ops =3D { + .read =3D uicr_read, + .write =3D uicr_write, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN +}; + + +static uint64_t io_read(void *opaque, hwaddr offset, unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + uint64_t r =3D 0; + + switch (offset) { + case NRF51_NVMC_READY: + r =3D NRF51_NVMC_READY_READY; + break; + case NRF51_NVMC_CONFIG: + r =3D s->config; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad read offset 0x%" HWADDR_PRIx "\n", __func__, offs= et); + break; + } + + return r; +} + +static void io_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + switch (offset) { + case NRF51_NVMC_CONFIG: + s->config =3D value & NRF51_NVMC_CONFIG_MASK; + break; + case NRF51_NVMC_ERASEPCR0: + case NRF51_NVMC_ERASEPCR1: + if (s->config & NRF51_NVMC_CONFIG_EEN) { + /* Mask in-page sub address */ + value &=3D ~(NRF51_PAGE_SIZE - 1); + if (value < (s->flash_size - NRF51_PAGE_SIZE)) { + memset(s->storage + value / 4, 0xFF, NRF51_PAGE_SIZE); + memory_region_flush_rom_device(&s->flash, value, + NRF51_PAGE_SIZE); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Flash erase at 0x%" HWADDR_PRIx" while flash not erasable= .\n", + __func__, offset); + } + break; + case NRF51_NVMC_ERASEALL: + if (value =3D=3D NRF51_NVMC_ERASE) { + if (s->config & NRF51_NVMC_CONFIG_EEN) { + memset(s->storage, 0xFF, s->flash_size); + memory_region_flush_rom_device(&s->flash, 0, s->flash_size= ); + memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash not erasable.\n", + __func__); + } + } + break; + case NRF51_NVMC_ERASEUICR: + if (value =3D=3D NRF51_NVMC_ERASE) { + memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad write offset 0x%" HWADDR_PRIx "\n", __func__, off= set); + } +} + +static const MemoryRegionOps io_ops =3D { + .read =3D io_read, + .write =3D io_write, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + + +static void flash_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + NRF51NVMState *s =3D NRF51_NVM(opaque); + + if (s->config & NRF51_NVMC_CONFIG_WEN) { + assert(offset < s->flash_size); + /* NOR Flash only allows bits to be flipped from 1's to 0's on wri= te */ + s->storage[offset / 4] &=3D value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Flash write 0x%" HWADDR_PRIx" while flash not writabl= e.\n", + __func__, offset); + } +} + + + +static const MemoryRegionOps flash_ops =3D { + .write =3D flash_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void nrf51_nvm_init(Object *obj) +{ + NRF51NVMState *s =3D NRF51_NVM(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mmio, obj, &io_ops, s, "nrf51_soc.nvmc", + NRF51_NVMC_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + + memory_region_init_io(&s->ficr, obj, &ficr_ops, s, "nrf51_soc.ficr", + sizeof(ficr_content)); + sysbus_init_mmio(sbd, &s->ficr); + + memory_region_init_io(&s->uicr, obj, &uicr_ops, s, "nrf51_soc.uicr", + sizeof(s->uicr_content)); + sysbus_init_mmio(sbd, &s->uicr); +} + +static void nrf51_nvm_realize(DeviceState *dev, Error **errp) +{ + NRF51NVMState *s =3D NRF51_NVM(dev); + Error *err =3D NULL; + + memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s, + "nrf51_soc.flash", s->flash_size, &err); + if (err) { + error_propagate(errp, err); + return; + } + + s->storage =3D memory_region_get_ram_ptr(&s->flash); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->flash); +} + +static void nrf51_nvm_reset(DeviceState *dev) +{ + NRF51NVMState *s =3D NRF51_NVM(dev); + + s->config =3D 0x00; + memset(s->uicr_content, 0xFF, sizeof(s->uicr_content)); +} + +static Property nrf51_nvm_properties[] =3D { + DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_nvm =3D { + .name =3D "nrf51_soc.nvm", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(uicr_content, NRF51NVMState, + NRF51_UICR_FIXTURE_SIZE), + VMSTATE_UINT32(config, NRF51NVMState), + VMSTATE_END_OF_LIST() + } +}; + +static void nrf51_nvm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->props =3D nrf51_nvm_properties; + dc->vmsd =3D &vmstate_nvm; + dc->realize =3D nrf51_nvm_realize; + dc->reset =3D nrf51_nvm_reset; +} + +static const TypeInfo nrf51_nvm_info =3D { + .name =3D TYPE_NRF51_NVM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51NVMState), + .instance_init =3D nrf51_nvm_init, + .class_init =3D nrf51_nvm_class_init +}; + +static void nrf51_nvm_register_types(void) +{ + type_register_static(&nrf51_nvm_info); +} + +type_init(nrf51_nvm_register_types) --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700393491651.2991805743826; Mon, 28 Jan 2019 10:33:13 -0800 (PST) Received: from localhost ([127.0.0.1]:36684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBia-0003hs-9t for importer@patchew.org; Mon, 28 Jan 2019 13:33:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41025) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNF-0002nR-5m for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::32b Subject: [Qemu-devel] [PULL 12/26] arm: Instantiate NRF51 special NVM's and NVMC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Peter Maydell Reviewed-by: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi Message-id: 20190123212234.32068-5-stefanha@redhat.com Signed-off-by: Peter Maydell --- include/hw/arm/nrf51_soc.h | 2 ++ hw/arm/nrf51_soc.c | 41 +++++++++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index fbdefc07e4d..fd7fcc71a56 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -15,6 +15,7 @@ #include "hw/char/nrf51_uart.h" #include "hw/misc/nrf51_rng.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" @@ -32,6 +33,7 @@ typedef struct NRF51State { =20 NRF51UARTState uart; NRF51RNGState rng; + NRF51NVMState nvm; NRF51GPIOState gpio; NRF51TimerState timer[NRF51_NUM_TIMERS]; =20 diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 1630c275940..b839daea8b9 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -29,8 +29,10 @@ * are supported in the future, add a sub-class of NRF51SoC for * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) -#define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) +#define NRF51822_FLASH_PAGES 256 +#define NRF51822_SRAM_PAGES 16 +#define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) +#define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) =20 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) =20 @@ -81,14 +83,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 - memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_s= ize, - &err); - if (err) { - error_propagate(errp, err); - return; - } - memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash= ); - memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); if (err) { error_propagate(errp, err); @@ -121,6 +115,29 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Er= ror **errp) qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(NRF51_RNG_BASE))); =20 + /* UICR, FICR, NVMC, FLASH */ + object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size", + &err); + if (err) { + error_propagate(errp, err); + return; + } + + object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); + memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr= , 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); + memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr= , 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); + memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr= , 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); + memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, m= r, 0); + /* GPIO */ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); if (err) { @@ -158,8 +175,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) =20 create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, NRF51_IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, - NRF51_FICR_SIZE); create_unimplemented_device("nrf51_soc.private", NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); } @@ -186,6 +201,8 @@ static void nrf51_soc_init(Object *obj) sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), TYPE_NRF51_RNG); =20 + sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_= NVM); + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701097298127.48578434235219; Mon, 28 Jan 2019 10:44:57 -0800 (PST) Received: from localhost ([127.0.0.1]:36867 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBtr-0005QA-BT for importer@patchew.org; Mon, 28 Jan 2019 13:44:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNU-00031J-Dh for qemu-devel@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.05 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aQjll81H3OlPviwbtYP9VWPnH/Zh0TuRsXiE7aLYYwQ=; b=SIJHfOXbS7o8P0g2kwmzOUoNi2sBYaxZfxM00wkpz+Iq+NVAtma284GPi4UY5AyPlr AmFkJcDU5U6nMQSVl6JXLhvfBwIzk5ge8WE537hWUkILILe8V0S5N3igHMqjLp4dLV4c OctidEJJe/BsyvkeannqJumCIifTdygSx+glo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aQjll81H3OlPviwbtYP9VWPnH/Zh0TuRsXiE7aLYYwQ=; b=IqxXuUDXTu5Vtpcj94UmjHDAvnKU8+G2TMybgq3iUceI5Xj7CUorFWIPsLyRo2eMaI QoaKzkrGQbBC6zO1xCzQC0fcm7ChM//KGfbYDFs6r4b5e7YqVGDHjyMULXad9wPoweBi TXtWNqWTnQ8hlzYMB1++LrojQK5A/MHl4GeG00cdZs8Vt/vE8WJovyFImyi4DqupvFqB EpLp7VBP7FyaFGwpudkRipDYEzCTjMb8TgPNhbSt1XCB8bzSdQuDvyuLv1dAlcTzRDT5 DgQMa+6LlgKm7pWdSd8JzmSuKqaX0jTpAMA5EqTfm2lW3ENkw/RFgPPbF2MiiOsocOnk 0OQw== X-Gm-Message-State: AJcUukfZuZzak2E/4ZjUIc/rzchhO2reyWaz+0EaqnMlsUH5SFgncGGM s5S6sc6r9CRQ/PXrMN+jkAtPnhe65tvrBg== X-Google-Smtp-Source: ALg8bN68rKCB2ss0635V6tUYynvFR2Tvxl3joR2LDkWRxtXEJpZAug3Wn0MtT1ZSKoknRAxXwEfxMw== X-Received: by 2002:adf:90e5:: with SMTP id i92mr21805217wri.210.1548699066599; Mon, 28 Jan 2019 10:11:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:34 +0000 Message-Id: <20190128181047.20781-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b Subject: [Qemu-devel] [PULL 13/26] tests/libqtest: Introduce qtest_init_with_serial() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Julia Suvorova Run qtest with a socket that connects QEMU chardev and test code. Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi Reviewed-by: Thomas Huth Reviewed-by: Alex Benn=C3=A9e Message-id: 20190123120759.7162-2-jusual@mail.ru Signed-off-by: Peter Maydell --- tests/libqtest.h | 11 +++++++++++ tests/libqtest.c | 25 +++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/tests/libqtest.h b/tests/libqtest.h index 7ea94139b0c..5937f919123 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -62,6 +62,17 @@ QTestState *qtest_init(const char *extra_args); */ QTestState *qtest_init_without_qmp_handshake(const char *extra_args); =20 +/** + * qtest_init_with_serial: + * @extra_args: other arguments to pass to QEMU. CAUTION: these + * arguments are subject to word splitting and shell evaluation. + * @sock_fd: pointer to store the socket file descriptor for + * connection with serial. + * + * Returns: #QTestState instance. + */ +QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd); + /** * qtest_quit: * @s: #QTestState instance to operate on. diff --git a/tests/libqtest.c b/tests/libqtest.c index 55750dd68de..6fb30855faf 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -315,6 +315,31 @@ QTestState *qtest_initf(const char *fmt, ...) return s; } =20 +QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd) +{ + int sock_fd_init; + char *sock_path, sock_dir[] =3D "/tmp/qtest-serial-XXXXXX"; + QTestState *qts; + + g_assert_true(mkdtemp(sock_dir) !=3D NULL); + sock_path =3D g_strdup_printf("%s/sock", sock_dir); + + sock_fd_init =3D init_socket(sock_path); + + qts =3D qtest_initf("-chardev socket,id=3Ds0,path=3D%s -serial chardev= :s0 %s", + sock_path, extra_args); + + *sock_fd =3D socket_accept(sock_fd_init); + + unlink(sock_path); + g_free(sock_path); + rmdir(sock_dir); + + g_assert_true(*sock_fd >=3D 0); + + return qts; +} + void qtest_quit(QTestState *s) { g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s= )); --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700833920231.20072150247688; Mon, 28 Jan 2019 10:40:33 -0800 (PST) Received: from localhost ([127.0.0.1]:36778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBpb-0001Bu-Lt for importer@patchew.org; Mon, 28 Jan 2019 13:40:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNb-00037o-PF for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNU-0000SZ-BC for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:28 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:46330) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNQ-0000A3-6u for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:22 -0500 Received: by mail-wr1-x442.google.com with SMTP id l9so19088281wrt.13 for ; Mon, 28 Jan 2019 10:11:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DonBq4Yn8tJ5IMUhhyslVwxS/ZuXbCwOXQTV7SNCdIk=; b=NxNmIDTlqNMl8BGkWtDWHT3GKE1D/DZSYwv8/PoszEuC4lkGRhqSng+NEVngP0UJQs tzEM07XKwO3IXlFJcven9RezDCPat1bW9oHoasQwlG//OlX2HxwFeVUkbV5BHIgjmOo0 B81eaISB0BPrTiQpFqMIYEK4nf9NRkd1MdWg0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DonBq4Yn8tJ5IMUhhyslVwxS/ZuXbCwOXQTV7SNCdIk=; b=gwbkYjAV3rCnWlX/3llr5Np/8F+NpxBztPQIzBblidyos6hCT8lByifSPurOfxoc9i 2L/j5oyMx7q7t+gSkx03AJtXr763oSxVGgZxbuSfKeJkPtmzAJwrUZMr2OX+S2MYaDdW QVkxs1TsAvy3MkrbolXyQUdFy3R2BVNkRWfzEP8T1DEsgBJ5cDrpavTYdpdGEA/MQH/+ qq9x72uGWIRJZZNYZA7G5cuelXtnSVfRXYmT8Grv9zdQW15GGTREf9BnIi+gbUfLu2JT HyU6B059HH6/0fp77IML37EaS9c9K0hgM3DMuX1k+OUn+TXp2VgoBHGscRe8vcKJ/RlE 81cQ== X-Gm-Message-State: AHQUAuaJmvRAt6zx0eO6f19RmBlMgv0sSqFc+Wc1KPTupH1zBsWmHvXu xR9SejmXWpqBcKD9Paea3QecZ22txl8Mnw== X-Google-Smtp-Source: AHgI3IZ6FvBm+aZkfSEF2Rc4PQR8akntI36H040ge68mIjDxcn3u2jxTADwBMLzXT6cqbG38dNQnXg== X-Received: by 2002:adf:ed92:: with SMTP id c18mr15087471wro.194.1548699067911; Mon, 28 Jan 2019 10:11:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:35 +0000 Message-Id: <20190128181047.20781-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 14/26] tests/microbit-test: Make test independent of global_qtest X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Julia Suvorova Using of global_qtest is not required here. Let's replace functions like readl() with the corresponding qtest_* counterparts. Signed-off-by: Julia Suvorova Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Thomas Huth Reviewed-by: Stefan Hajnoczi Message-id: 20190123120759.7162-3-jusual@mail.ru Signed-off-by: Peter Maydell --- tests/microbit-test.c | 247 ++++++++++++++++++++++-------------------- 1 file changed, 129 insertions(+), 118 deletions(-) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index dcdc0cd41a5..afeb6b082a6 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -24,22 +24,22 @@ #include "hw/i2c/microbit_i2c.h" =20 /* Read a byte from I2C device at @addr from register @reg */ -static uint32_t i2c_read_byte(uint32_t addr, uint32_t reg) +static uint32_t i2c_read_byte(QTestState *qts, uint32_t addr, uint32_t reg) { uint32_t val; =20 - writel(NRF51_TWI_BASE + NRF51_TWI_REG_ADDRESS, addr); - writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STARTTX, 1); - writel(NRF51_TWI_BASE + NRF51_TWI_REG_TXD, reg); - val =3D readl(NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ADDRESS, addr); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STARTTX, 1); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_TXD, reg); + val =3D qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_TXDSENT); g_assert_cmpuint(val, =3D=3D, 1); - writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); =20 - writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STARTRX, 1); - val =3D readl(NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STARTRX, 1); + val =3D qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_EVENT_RXDREADY); g_assert_cmpuint(val, =3D=3D, 1); - val =3D readl(NRF51_TWI_BASE + NRF51_TWI_REG_RXD); - writel(NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); + val =3D qtest_readl(qts, NRF51_TWI_BASE + NRF51_TWI_REG_RXD); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_TASK_STOP, 1); =20 return val; } @@ -47,22 +47,25 @@ static uint32_t i2c_read_byte(uint32_t addr, uint32_t r= eg) static void test_microbit_i2c(void) { uint32_t val; + QTestState *qts =3D qtest_init("-M microbit"); =20 /* We don't program pins/irqs but at least enable the device */ - writel(NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 5); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 5); =20 /* MMA8653 magnetometer detection */ - val =3D i2c_read_byte(0x3A, 0x0D); + val =3D i2c_read_byte(qts, 0x3A, 0x0D); g_assert_cmpuint(val, =3D=3D, 0x5A); =20 - val =3D i2c_read_byte(0x3A, 0x0D); + val =3D i2c_read_byte(qts, 0x3A, 0x0D); g_assert_cmpuint(val, =3D=3D, 0x5A); =20 /* LSM303 accelerometer detection */ - val =3D i2c_read_byte(0x3C, 0x4F); + val =3D i2c_read_byte(qts, 0x3C, 0x4F); g_assert_cmpuint(val, =3D=3D, 0x40); =20 - writel(NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 0); + qtest_writel(qts, NRF51_TWI_BASE + NRF51_TWI_REG_ENABLE, 0); + + qtest_quit(qts); } =20 static void test_nrf51_gpio(void) @@ -80,220 +83,228 @@ static void test_nrf51_gpio(void) {NRF51_GPIO_REG_DIRCLR, 0x00000000} }; =20 + QTestState *qts =3D qtest_init("-M microbit"); + /* Check reset state */ for (i =3D 0; i < ARRAY_SIZE(reset_state); i++) { expected =3D reset_state[i].expected; - actual =3D readl(NRF51_GPIO_BASE + reset_state[i].addr); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + reset_state[i].addr); g_assert_cmpuint(actual, =3D=3D, expected); } =20 for (i =3D 0; i < NRF51_GPIO_PINS; i++) { expected =3D 0x00000002; - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START + i * = 4); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + + NRF51_GPIO_REG_CNF_START + i * 4); g_assert_cmpuint(actual, =3D=3D, expected); } =20 /* Check dir bit consistency between dir and cnf */ /* Check set via DIRSET */ expected =3D 0x80000001; - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRSET, expected); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); g_assert_cmpuint(actual, =3D=3D, expected); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) + & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x01); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) = & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x01); =20 /* Check clear via DIRCLR */ - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIRCLR, 0x80000001); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); g_assert_cmpuint(actual, =3D=3D, 0x00000000); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) + & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x00); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) = & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x00); =20 /* Check set via DIR */ expected =3D 0x80000001; - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, expected); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR); g_assert_cmpuint(actual, =3D=3D, expected); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START) + & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x01); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) & 0x01; + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_END) = & 0x01; g_assert_cmpuint(actual, =3D=3D, 0x01); =20 /* Reset DIR */ - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_DIR, 0x00000000); =20 /* Check Input propagates */ - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x00); + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x00); - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 1); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x01); - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= -1); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, -1); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x01); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); =20 /* Check pull-up working */ - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x00); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b1110); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x01); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); =20 /* Check pull-down working */ - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 1); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 1); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0000); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x01); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0110); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x00); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= -1); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0x02); + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, -1); =20 /* Check Output propagates */ - irq_intercept_out("/machine/nrf51"); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); - g_assert_true(get_irq(0)); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); - g_assert_false(get_irq(0)); + qtest_irq_intercept_out(qts, "/machine/nrf51"); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b0011); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + g_assert_true(qtest_get_irq(qts, 0)); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + g_assert_false(qtest_get_irq(qts, 0)); =20 /* Check self-stimulation */ - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x01); =20 - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); - actual =3D readl(NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x01; + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTCLR, 0x01); + actual =3D qtest_readl(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_IN) & 0x0= 1; g_assert_cmpuint(actual, =3D=3D, 0x00); =20 /* * Check short-circuit - generates an guest_error which must be checked * manually as long as qtest can not scan qemu_log messages */ - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); - writel(NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); - qtest_set_irq_in(global_qtest, "/machine/nrf51", "unnamed-gpio-in", 0,= 0); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_CNF_START, 0b01); + qtest_writel(qts, NRF51_GPIO_BASE + NRF51_GPIO_REG_OUTSET, 0x01); + qtest_set_irq_in(qts, "/machine/nrf51", "unnamed-gpio-in", 0, 0); + + qtest_quit(qts); } =20 -static void timer_task(hwaddr task) +static void timer_task(QTestState *qts, hwaddr task) { - writel(NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); + qtest_writel(qts, NRF51_TIMER_BASE + task, NRF51_TRIGGER_TASK); } =20 -static void timer_clear_event(hwaddr event) +static void timer_clear_event(QTestState *qts, hwaddr event) { - writel(NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); + qtest_writel(qts, NRF51_TIMER_BASE + event, NRF51_EVENT_CLEAR); } =20 -static void timer_set_bitmode(uint8_t mode) +static void timer_set_bitmode(QTestState *qts, uint8_t mode) { - writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); + qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_BITMODE, mode); } =20 -static void timer_set_prescaler(uint8_t prescaler) +static void timer_set_prescaler(QTestState *qts, uint8_t prescaler) { - writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, prescaler); + qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_PRESCALER, presca= ler); } =20 -static void timer_set_cc(size_t idx, uint32_t value) +static void timer_set_cc(QTestState *qts, size_t idx, uint32_t value) { - writel(NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, value); + qtest_writel(qts, NRF51_TIMER_BASE + NRF51_TIMER_REG_CC0 + idx * 4, va= lue); } =20 -static void timer_assert_events(uint32_t ev0, uint32_t ev1, uint32_t ev2, - uint32_t ev3) +static void timer_assert_events(QTestState *qts, uint32_t ev0, uint32_t ev= 1, + uint32_t ev2, uint32_t ev3) { - g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_0) =3D=3D = ev0); - g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_1) =3D=3D = ev1); - g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_2) =3D=3D = ev2); - g_assert(readl(NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE_3) =3D=3D = ev3); + g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE= _0) + =3D=3D ev0); + g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE= _1) + =3D=3D ev1); + g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE= _2) + =3D=3D ev2); + g_assert(qtest_readl(qts, NRF51_TIMER_BASE + NRF51_TIMER_EVENT_COMPARE= _3) + =3D=3D ev3); } =20 static void test_nrf51_timer(void) { uint32_t steps_to_overflow =3D 408; + QTestState *qts =3D qtest_init("-M microbit"); =20 /* Compare Match */ - timer_task(NRF51_TIMER_TASK_STOP); - timer_task(NRF51_TIMER_TASK_CLEAR); + timer_task(qts, NRF51_TIMER_TASK_STOP); + timer_task(qts, NRF51_TIMER_TASK_CLEAR); =20 - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_3); =20 - timer_set_bitmode(NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ - timer_set_prescaler(0); + timer_set_bitmode(qts, NRF51_TIMER_WIDTH_16); /* 16 MHz Timer */ + timer_set_prescaler(qts, 0); /* Swept over in first step */ - timer_set_cc(0, 2); + timer_set_cc(qts, 0, 2); /* Barely miss on first step */ - timer_set_cc(1, 162); + timer_set_cc(qts, 1, 162); /* Spot on on third step */ - timer_set_cc(2, 480); + timer_set_cc(qts, 2, 480); =20 - timer_assert_events(0, 0, 0, 0); + timer_assert_events(qts, 0, 0, 0, 0); =20 - timer_task(NRF51_TIMER_TASK_START); - clock_step(10000); - timer_assert_events(1, 0, 0, 0); + timer_task(qts, NRF51_TIMER_TASK_START); + qtest_clock_step(qts, 10000); + timer_assert_events(qts, 1, 0, 0, 0); =20 /* Swept over on first overflow */ - timer_set_cc(3, 114); + timer_set_cc(qts, 3, 114); =20 - clock_step(10000); - timer_assert_events(1, 1, 0, 0); + qtest_clock_step(qts, 10000); + timer_assert_events(qts, 1, 1, 0, 0); =20 - clock_step(10000); - timer_assert_events(1, 1, 1, 0); + qtest_clock_step(qts, 10000); + timer_assert_events(qts, 1, 1, 1, 0); =20 /* Wrap time until internal counter overflows */ while (steps_to_overflow--) { - timer_assert_events(1, 1, 1, 0); - clock_step(10000); + timer_assert_events(qts, 1, 1, 1, 0); + qtest_clock_step(qts, 10000); } =20 - timer_assert_events(1, 1, 1, 1); + timer_assert_events(qts, 1, 1, 1, 1); =20 - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_0); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_1); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_2); - timer_clear_event(NRF51_TIMER_EVENT_COMPARE_3); - timer_assert_events(0, 0, 0, 0); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_0); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_1); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_2); + timer_clear_event(qts, NRF51_TIMER_EVENT_COMPARE_3); + timer_assert_events(qts, 0, 0, 0, 0); =20 - timer_task(NRF51_TIMER_TASK_STOP); + timer_task(qts, NRF51_TIMER_TASK_STOP); =20 /* Test Proposal: Stop/Shutdown */ /* Test Proposal: Shortcut Compare -> Clear */ /* Test Proposal: Shortcut Compare -> Stop */ /* Test Proposal: Counter Mode */ + + qtest_quit(qts); } =20 int main(int argc, char **argv) { - int ret; - g_test_init(&argc, &argv, NULL); =20 - global_qtest =3D qtest_initf("-machine microbit"); - qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); =20 - ret =3D g_test_run(); - - qtest_quit(global_qtest); - return ret; + return g_test_run(); } --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701277621540.9942664232318; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uX5nAYGehv68vGAECP4Mrhj/iKf1M0dS2W4krBZSGkI=; b=iX97tbEWVOko3Is+W7vZ6DwSQdzYLtTUFMeCRuRPDlM5dENRDGHav9GryU1aAWPF9G QQ+ArmDMx3QyOAkQJrdXjshlUXj8pYTd8AGshTHSoaQXbbt/eSyaA6OsL7khsBTcU0/9 rMYfZk0qmi9rwHGNoSc5dI7rk0hbdbjDyE0y0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uX5nAYGehv68vGAECP4Mrhj/iKf1M0dS2W4krBZSGkI=; b=kXXEVrkWddRSVVfmZiIE6obHnL31zUb9Kv1wo2L6F7Ib8RBUglaOuCbnKDNbcgDZjv B6mWVSPf0wZJjHAUrgjB+hlxm+ku5ZwaHx1mvLddNI821FS0eIJhEJpPJV9fbJOZSspE 42bDvbcUEgmZma1EL/BmHGxRVmpBs1EpOiz3rCinz0jZsYGj2l6ZME+KsxjbeZYD2HVV 6sPQbfbNjHYfkPwSfbTKKcqYh3zkY3J7UElqmQMKh1BLxr2Lfh5Cw5XUfXtEE8zgxo6s 7tzr+J7KooqAA7Q5K34R1fzdWra9FfAFww3ZiRU5pENqmQTdCTqvr/gx0rN6q6wk5ARb kZpg== X-Gm-Message-State: AJcUukesKM192ceoJEPQT6GHgOJ1Y6yjyqnoxDTjkblyVGX5n0kF9uUe 9nCwxTv0ZWsitqtEHS6SIAiHCnbrQ19Khw== X-Google-Smtp-Source: ALg8bN4EHQt+vjyP4KSsIvG8EY9sCPSqRp5sCL+N4E0GPBzYKt0FuC1YxYw40fFRW2Tnkjmh3f9wQg== X-Received: by 2002:adf:9c01:: with SMTP id f1mr23630381wrc.286.1548699069072; Mon, 28 Jan 2019 10:11:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:36 +0000 Message-Id: <20190128181047.20781-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 15/26] tests/microbit-test: Check nRF51 UART functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Julia Suvorova Some functional tests for: Basic reception/transmittion Suspending INTEN* registers Signed-off-by: Julia Suvorova Reviewed-by: Stefan Hajnoczi Acked-by: Thomas Huth Message-id: 20190123120759.7162-4-jusual@mail.ru Signed-off-by: Peter Maydell --- tests/microbit-test.c | 89 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index afeb6b082a6..3bad947b6cd 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -19,10 +19,98 @@ #include "libqtest.h" =20 #include "hw/arm/nrf51.h" +#include "hw/char/nrf51_uart.h" #include "hw/gpio/nrf51_gpio.h" #include "hw/timer/nrf51_timer.h" #include "hw/i2c/microbit_i2c.h" =20 +static bool uart_wait_for_event(QTestState *qts, uint32_t event_addr) +{ + time_t now, start =3D time(NULL); + + while (true) { + if (qtest_readl(qts, event_addr) =3D=3D 1) { + qtest_writel(qts, event_addr, 0x00); + return true; + } + + /* Wait at most 10 minutes */ + now =3D time(NULL); + if (now - start > 600) { + break; + } + g_usleep(10000); + } + + return false; +} + +static void uart_rw_to_rxd(QTestState *qts, int sock_fd, const char *in, + char *out) +{ + int i, in_len =3D strlen(in); + + g_assert_true(write(sock_fd, in, in_len) =3D=3D in_len); + for (i =3D 0; i < in_len; i++) { + g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + + A_UART_RXDRDY)); + out[i] =3D qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD); + } + out[i] =3D '\0'; +} + +static void uart_w_to_txd(QTestState *qts, const char *in) +{ + int i, in_len =3D strlen(in); + + for (i =3D 0; i < in_len; i++) { + qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, in[i]); + g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + + A_UART_TXDRDY)); + } +} + +static void test_nrf51_uart(void) +{ + int sock_fd; + char s[10]; + QTestState *qts =3D qtest_init_with_serial("-M microbit", &sock_fd); + + g_assert_true(write(sock_fd, "c", 1) =3D=3D 1); + g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), =3D=3D= , 0x00); + + qtest_writel(qts, NRF51_UART_BASE + A_UART_ENABLE, 0x04); + qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTRX, 0x01); + + g_assert_true(uart_wait_for_event(qts, NRF51_UART_BASE + A_UART_RXDRDY= )); + qtest_writel(qts, NRF51_UART_BASE + A_UART_RXDRDY, 0x00); + g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_RXD), =3D=3D= , 'c'); + + qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENSET, 0x04); + g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), =3D= =3D, 0x04); + qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENCLR, 0x04); + g_assert_cmphex(qtest_readl(qts, NRF51_UART_BASE + A_UART_INTEN), =3D= =3D, 0x00); + + uart_rw_to_rxd(qts, sock_fd, "hello", s); + g_assert_true(memcmp(s, "hello", 5) =3D=3D 0); + + qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTTX, 0x01); + uart_w_to_txd(qts, "d"); + g_assert_true(read(sock_fd, s, 10) =3D=3D 1); + g_assert_cmphex(s[0], =3D=3D, 'd'); + + qtest_writel(qts, NRF51_UART_BASE + A_UART_SUSPEND, 0x01); + qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, 'h'); + qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTTX, 0x01); + uart_w_to_txd(qts, "world"); + g_assert_true(read(sock_fd, s, 10) =3D=3D 5); + g_assert_true(memcmp(s, "world", 5) =3D=3D 0); + + close(sock_fd); + + qtest_quit(qts); +} + /* Read a byte from I2C device at @addr from register @reg */ static uint32_t i2c_read_byte(QTestState *qts, uint32_t addr, uint32_t reg) { @@ -302,6 +390,7 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 + qtest_add_func("/microbit/nrf51/uart", test_nrf51_uart); qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hWVJfr9it5CUSBlRCnYp1LsmFwKpFh4z3yZ8aj5auJQ=; b=DeDavezT+C6gXDHDtTEtGqHAqJsoWDgulY3lQAFO12I1sHGGmtLCXgzJsZg2DGhMsk BJqCDNqhC5GJhUaxE5twGG/b2VoIDhaISNQz8Gf+n8SLeWSTcIOdUEJvpwMRJJPoRbRx 9OfWYVqV8tdz/HpZB/alJIXPzTTEYuaCvpCK8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hWVJfr9it5CUSBlRCnYp1LsmFwKpFh4z3yZ8aj5auJQ=; b=N/suZxdZwKyzaQ9JxzS4RjcZ26mIlLPtI4PmoNfWzSENYdPd2Eqzv7xe7tg2wZjhCJ Tm3WM0/2KiIa70j4JfrUsGxS9qYwdUXl13sL0CftvCv/X5m2lhvI1ru3hOE8qIOFBw/h b642tVFr3MN7BDKD3vz16lm28MJNgvWfPcwKNow8KkrD5OAQq84b2rPuDrqdDAWTQBSI M/vl62aqBX4og0tNKh7QpKB+/prJAB4LeSly8ZNq5BTYGaRcEIQivXbrdcpXhG1+6HAR HEVb9hv810oqY0FE63Khrk3wGKYBBviBFQkr+irb/SGXuZDPZvmYe0zYubFw8t+D8SqD dKSg== X-Gm-Message-State: AJcUukc7T8gDOIUDMqEr7OvkT8E1ucg4ApQ7huzldPPg3saPbAFVC2Va iFOKLLmqEuUzoPEWtadr+O6eclPt6zFXjw== X-Google-Smtp-Source: ALg8bN6yVMqMEVtMnj7w/H8MuWPEhNggiFXADIJUzYoMWGGpQPX2Fzry20Xd7NXBywgbUW9Sk2GPvA== X-Received: by 2002:a5d:4d87:: with SMTP id b7mr21573375wru.316.1548699070334; Mon, 28 Jan 2019 10:11:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:37 +0000 Message-Id: <20190128181047.20781-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 Subject: [Qemu-devel] [PULL 16/26] checkpatch: Don't emit spurious warnings about block comments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In checkpatch we attempt to check for and warn about block comments which start with /* or /** followed by a non-blank. Unfortunately a bug in the regex meant that we would incorrectly warn about comments starting with "/**" with no following text: git show 9813dc6ac3954d58ba16b3920556f106f97e1c67|./scripts/checkpatch.pl= - WARNING: Block comments use a leading /* on a separate line #34: FILE: tests/libqtest.h:233: +/** The sequence "/\*\*?" was intended to match either "/*" or "/**", but Perl's semantics for '?' allow it to backtrack and try the "matches 0 chars" option if the "matches 1 char" choice leads to a failure of the rest of the regex to match. Switch to "/\*\*?+" which uses what perlre(1) calls the "possessive" quantifier form: this means that if it matches the "/**" string it will not later backtrack to matching just the "/*" prefix. The other end of the regex is also wrong: it is attempting to check for "/* or /** followed by something that isn't just whitespace", but [ \t]*.+[ \t]* will match on pure whitespace. This is less significant but means that a line with just a comment-starter followed by trailing whitespace will generate an incorrect warning about block comment style as well as the correct error about trailing whitespace which a different checkpatch test emits. Fixes: 8c06fbdf36bf4d ("scripts/checkpatch.pl: Enforce multiline comment sy= ntax") Reported-by: Thomas Huth Reported-by: Eric Blake Signed-off-by: Peter Maydell Reviewed-by: Eric Blake Message-id: 20190118165050.22270-1-peter.maydell@linaro.org --- scripts/checkpatch.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index d10dddf1be4..88682cb0a9f 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -1624,7 +1624,7 @@ sub process { =20 # Block comments use /* on a line of its own if ($rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ - $rawline =3D~ m@^\+.*/\*\*?[ \t]*.+[ \t]*$@) { # /* or /** non-blank + $rawline =3D~ m@^\+.*/\*\*?+[ \t]*[^ \t]@) { # /* or /** non-blank WARN("Block comments use a leading /* on a separate line\n" . $herecurr= ); } =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701315915654.0856569942947; Mon, 28 Jan 2019 10:48:35 -0800 (PST) Received: from localhost ([127.0.0.1]:36941 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBxN-0008F0-Ux for importer@patchew.org; Mon, 28 Jan 2019 13:48:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNU-00031O-EA for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNQ-0000Pq-5v for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:24 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39006) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNJ-0000Ez-94 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:15 -0500 Received: by mail-wr1-x444.google.com with SMTP id t27so19148906wra.6 for ; Mon, 28 Jan 2019 10:11:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1LYeV/7A19n/oOAfWvaA7HfPSjT1wTZDwCl9XfLG4wQ=; b=k2O7Fk5CFRyJctPdGU4Hn9Msvr+VMICn6mNeHP9m5MiXEPj+f0Ic2EpPp6wUTN5iB3 Wuhgo0WTUjeTty8QAbvSv7RmCbCScW33+wmN7YydeCv/LswPiBqSbACL/WBO7etYrz7z h2+rrl0QV9PsoE/hUW/BT9tskzxQEHn/SH8NU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1LYeV/7A19n/oOAfWvaA7HfPSjT1wTZDwCl9XfLG4wQ=; b=A9sGPA+WP3zHqveOptGBUdE6ANrMKqulGgNJ4c7TXFvghxIZcW9NLsVMvhRYiQBVRU Mpgr2BX6ftyGihOewNAMzlc5peKHmaEIznoX5GkDMmvwCcdiSCfd/erK5YVrnvwzYVI+ VAHHk5Ss1Nu6lhMeMr6U90pD19kTGCaRMG33RZ9LupFOorzemZus+oFZGyW0w0MLhfez kUJxaxtFD0Byijnj3DjPRaFbUuDyYclHcCeHHV25IYHCgLVXT6WzK52xQsUwkyK0x7y+ OIiHjfOa6Ms4HBsc8KHIrPuDNyDewdz3b242PztYSQn6NU/ul6K9dxp/odu+5FLDS23U p/eA== X-Gm-Message-State: AJcUuke9gVQD7IbLBCcAcn/d6LkE2fw/jd4oSSV8uteaIl/jOSZCL5UW K0akZFxFTH/SMCXp0AUHSF1osZRhm3Sz1A== X-Google-Smtp-Source: ALg8bN4tsMv1hjmdo2MgxVpNzvHnl0r3Pxi/vT4lXTtidPUBXLXQKJkma+zAp6jxu+LmeO+YPF4cvQ== X-Received: by 2002:adf:9dd2:: with SMTP id q18mr22610177wre.12.1548699071445; Mon, 28 Jan 2019 10:11:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:38 +0000 Message-Id: <20190128181047.20781-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 17/26] xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) If we aren't going to create any RPUs, then don't create the rpu-cluster unit. This allows us to add an assertion to the cluster object that it contains at least one CPU, which helps to avoid bugs in creating clusters and putting CPUs in them. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20190121184314.14311-1-peter.maydell@linaro.org --- hw/arm/xlnx-zynqmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c67ac2e64ac..70cbe6bd475 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -178,6 +178,11 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s,= const char *boot_cpu, int i; int num_rpus =3D MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_= NUM_RPU_CPUS); =20 + if (num_rpus <=3D 0) { + /* Don't create rpu-cluster object if there's nothing to put in it= */ + return; + } + object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, sizeof(s->rpu_cluster), TYPE_CPU_CLUSTER, &error_abort, NULL); --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701414089691.8431283890664; Mon, 28 Jan 2019 10:50:14 -0800 (PST) Received: from localhost ([127.0.0.1]:36954 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goByv-0000kc-Lw for importer@patchew.org; Mon, 28 Jan 2019 13:50:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNd-00038r-3a for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Xw-AI for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:33 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:41244) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000HP-2t for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wr1-x432.google.com with SMTP id x10so19123490wrs.8 for ; Mon, 28 Jan 2019 10:11:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.11 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=F4JmOlOwq7xp60ySXOl4Ahq+78GWoCsJheA9B1t63k0=; b=BNAHjiwK72uJ6E+wGuSTigNLakJceX/VFg87sz10wYp1dSlGIZx3ajpYyAKCTQTM5e XYOUa2QKVSZIqLAiimjZ9uvSF03KIzJxXogY8h1OjE66Y87XJmX0F4CZsWyN/bob/APG lkzjq4ebYyAPkBYXJrpKz0a2RKWHntGV5gpVU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4JmOlOwq7xp60ySXOl4Ahq+78GWoCsJheA9B1t63k0=; b=mlhQLaoCustu7hvdY9Ntv2YKdKIBtEkmk22XiNRzWEpDx5gunEvXYbJkMYFX4CNTqf E1jMj+PK2nfPASWy7eNhmh7qjJl7o3Xe1QoZ0OXHRNh5vr8Fcwrb6qA8t1RxGHsZ0Xv+ 4TILwtPiBoKIoW/CDQU8RGZiYwFNe/hF0U0i3753MvLiRYl0IwNTsETtZcFK5NkPL12P LaxISU5tf2uq6SGQG2W0d/3VN+IRkfRhY3jSQbQSiBNcLEVkVWlWQigVRanJjDPT0YBs 1MwTKLNxMxSsPvq9ojHgEE0fRfd/kI18hVIL7cmFWGETIC5Tfo2q0HczmSs/gRtjN/sR PKsw== X-Gm-Message-State: AJcUukdzsp/EQoJvVNKhd2BPnhV1IEvZvsPeN3s9IZKaHM6EVukOwk7i xqvADfsA1d6CO3Wc5lc9EUZO8F1W/S7r6w== X-Google-Smtp-Source: ALg8bN7kuOGoZrnt3LsPl7T41kYrviWkkrIdkrg9wfOGm2Dqj7Zp4eerSCKvol78IX3bHnfREJxb9Q== X-Received: by 2002:adf:f691:: with SMTP id v17mr21950862wrp.114.1548699072739; Mon, 28 Jan 2019 10:11:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:39 +0000 Message-Id: <20190128181047.20781-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 18/26] aspeed/smc: fix default read value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater 0xFFFFFFFF should be returned for non implemented registers. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190124140519.13838-2-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 1270842dcf0..7af808c33c5 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -670,7 +670,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); - return 0; + return -1; } } =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700765958604.0636725314514; Mon, 28 Jan 2019 10:39:25 -0800 (PST) Received: from localhost ([127.0.0.1]:36770 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBoa-0000Cy-Uu for importer@patchew.org; Mon, 28 Jan 2019 13:39:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNd-00039T-Pb for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000YX-LW for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:33 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35836) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000Ih-Cr for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wr1-x431.google.com with SMTP id 96so19193366wrb.2 for ; Mon, 28 Jan 2019 10:11:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GCnlMeweuIJvpl2JL6nATLlnfPOZB2vDzvUEhxD4dTw=; b=F2j9aIP3/l65PlSZl7Fav1WnStv/v+Zp/pQHvC7YxqNvbcpZChz2DIBUrIN2AIOjeZ o65oZ3KCMYhu9TxqQnJ2LF0sbmX1mvlUXxyMq4fD/1CoJuXzSMM7JkCEfAjGrVUsoyQu pMODrAqGqCZEmZ5IVFQO47zyFpuMBvk9htS1I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GCnlMeweuIJvpl2JL6nATLlnfPOZB2vDzvUEhxD4dTw=; b=ZavxFHBBVSjpHeQTcerCdBmXUBvfBuE1iBmnjwMDr3dt7ZJTYQDFzqo2j+8wA8uNPx hoeBwj/FCuy7S9SrMOgjJYSeTogHTlT3M6V4qwSx3WD14SSmHKR3cfFk6UT51e5WEyki ux/bVg4qlkvTc0N7BIUzUOdBWC4WtMHq3PxvpSYTcJbtF/rhIMevbduG3eMzIQzAyvFX V/cuf+XonFAByjF3wQBBtTzselkAubDM7WZmWTgpbjlAergBoyvFq/3qMmBdptjRt9FQ EuunAd1hcd0nOljQP7VUsNzSby7PSHxR3wGSIka4YRlWn0x9xLzGn0dqAfUUeEttZREA m8OA== X-Gm-Message-State: AJcUukeF6PgT+We3Kd5Ya3piYPN8JPIzbKa3Ii8TaDTayEEIrh1s2fuL CSl39L4/ITYSY8LL79mmi0YxUy/cEnSG5g== X-Google-Smtp-Source: ALg8bN7EQEUPlXsa36S55w6e+xRAk1GMqME48sf45AcDhlpqou681Y2nGR/fxifOZB2e3yKd1xu4SQ== X-Received: by 2002:a5d:548d:: with SMTP id h13mr21663809wrv.80.1548699073769; Mon, 28 Jan 2019 10:11:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:40 +0000 Message-Id: <20190128181047.20781-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 Subject: [Qemu-devel] [PULL 19/26] aspeed/smc: define registers for all possible CS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The model should expose one control register per possible CS. When testing the validity of the register number in the read operation, replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum number of flash devices a controller can handle. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Message-id: 20190124140519.13838-3-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 7af808c33c5..6045ca11b96 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -665,7 +665,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) addr =3D=3D s->r_ce_ctrl || addr =3D=3D R_INTR_CTRL || (addr >=3D R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves= ) || - (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) { + (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves))= { return s->regs[addr]; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701484242448.3784693063419; Mon, 28 Jan 2019 10:51:24 -0800 (PST) Received: from localhost ([127.0.0.1]:36993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goC0B-0001a7-AY for importer@patchew.org; Mon, 28 Jan 2019 13:51:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNd-00038t-5P for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Xl-70 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:33 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:56072) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNb-0000L7-Vv for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wm1-x333.google.com with SMTP id y139so14913878wmc.5 for ; Mon, 28 Jan 2019 10:11:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.13 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7LfPJAlqVpZ1EVfMdQKU6XxBBLcXbTeo3SylN/1FKzk=; b=WmEIoJuClb13Z3zMTdgO0HywOGookjHXZW+Yy0j0RbytgykJqDF4SlKhZGgd1qsqh6 zIrldd/oKICAqIr+AwmiUivvSq9ylMyPLFRFaJvcCaOUFvLCDuyGlA46XZH+Lt21Drjv wp4tbKau7ZyGkmJTPLonBx7Itg7hPQssol6Ys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7LfPJAlqVpZ1EVfMdQKU6XxBBLcXbTeo3SylN/1FKzk=; b=ImXVM8IpLJhE4KpHxcvIWEeMeQWhthgt5+tYBb84d4ZbJEdfVZqOk1nl5zeitVNKZe rkCM46b4UNZpo4DuT8BfsGHwyE+ie+Fa/XIle6yopOcHpSjnu8PF0ORADCWZQ0agqttW FVbQoepsDAiIT5T1dLqRTvZTH+Tp4420N3uZ++x86/kHi/Gvqs/E1e/3chonRW6XwDPO qBUSO5wvQpn5fvzOraL1j+PZptNLRmIkAhzGr/VLQb6+ei130GZxsA99udOtoLHozUTx muWL4/28zRZcJNLc4qKrulSCMBXaC2MelIAAKjvHZTPbbYoOgTKWxEarG+Bt5bYtYoBe 7UQA== X-Gm-Message-State: AJcUukegUq0mekiS5HBvGgsQxth/mkGReijiZaUiOmOhYl9HJFpHPfvn 4kTArGCxulCTaeyw91P2TNGMDwWKxC5o7A== X-Google-Smtp-Source: ALg8bN7fYqLEyQxyOOuxRX7KfEgLeGPCytH2y21aSQuKCGpzudqx0v8k71RaZGJSvsefxwRrfIF1+w== X-Received: by 2002:a1c:b456:: with SMTP id d83mr18801108wmf.115.1548699074810; Mon, 28 Jan 2019 10:11:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:41 +0000 Message-Id: <20190128181047.20781-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 Subject: [Qemu-devel] [PULL 20/26] aspeed/smc: Add dummy data register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The SMC controllers have a register containing the byte that will be used as dummy output. It can be modified by software. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Joel Stanley Message-id: 20190124140519.13838-4-clg@kaod.org Signed-off-by: Peter Maydell --- hw/ssi/aspeed_smc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 6045ca11b96..9f3b6f4b450 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -98,8 +98,8 @@ /* Misc Control Register #1 */ #define R_MISC_CTRL1 (0x50 / 4) =20 -/* Misc Control Register #2 */ -#define R_MISC_CTRL2 (0x54 / 4) +/* SPI dummy cycle data */ +#define R_DUMMY_DATA (0x54 / 4) =20 /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) @@ -529,7 +529,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, = uint32_t addr) */ if (aspeed_smc_flash_mode(fl) =3D=3D CTRL_FREADMODE) { for (i =3D 0; i < aspeed_smc_flash_dummies(fl); i++) { - ssi_transfer(fl->controller->spi, 0xFF); + ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff= ); } } } @@ -664,6 +664,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad= dr, unsigned int size) addr =3D=3D s->r_timings || addr =3D=3D s->r_ce_ctrl || addr =3D=3D R_INTR_CTRL || + addr =3D=3D R_DUMMY_DATA || (addr >=3D R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves= ) || (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves))= { return s->regs[addr]; @@ -697,6 +698,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr,= uint64_t data, if (value !=3D s->regs[R_SEG_ADDR0 + cs]) { aspeed_smc_flash_set_segment(s, cs, value); } + } else if (addr =3D=3D R_DUMMY_DATA) { + s->regs[addr] =3D value & 0xff; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n", __func__, addr); --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548701651766498.9249580778012; Mon, 28 Jan 2019 10:54:11 -0800 (PST) Received: from localhost ([127.0.0.1]:37007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goC2n-0003K3-O4 for importer@patchew.org; Mon, 28 Jan 2019 13:54:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNe-0003AV-O7 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Yd-Mo for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52375) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000NX-De for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wm1-x333.google.com with SMTP id m1so15043046wml.2 for ; Mon, 28 Jan 2019 10:11:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=P5GV8ZOhOv+ITXhiylNYBsFbrkOPLRqvGIgOhWeqpxs=; b=J6xd7OcHtP3f+/t/0kpNVbhTrWHn/hwe5+y1TSe7eohVM3K0SpowHOafauG/Hg7RnO Qi+uEMluHvey0r4ilkQsjzANzYtHw770eylZkNwCSCKczMEdtvJhNvodC2R2D7lQn35i tnr41qlZl0BPme1LHZFrCSz62lT0Dz9WWBmJ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P5GV8ZOhOv+ITXhiylNYBsFbrkOPLRqvGIgOhWeqpxs=; b=KWhuasdtgbuUaOZL5UFwWCXSBgUlhZzaFt2Dl0/cg4tm86Lnx0H21peyBfmXuk26b8 bsd1v1Fqf4Simm/sb/jEShurI8i4nNRdqmEKkjzjohjNaDSY9jjmarapnINqzVrjL7u1 Wj4O9Uu6NvaL/Hg90KfnYIND4i2M4xShSYdlu/25N14YFK29bm4yUNBv1bzcO6yKM3Pb qrKPCLQuwAirkTjGRrlOtPYWpRhiwh4sqlSxOzgV6xpBX+6eeB9yPSoRJWwxxxQeWJEX a2K1tRWUr11IWpgZyDQDKn8jILrhy03byk4ZnK4fsl87woKar0SZAxk15VPF4BP+Vy57 UYrg== X-Gm-Message-State: AJcUukcjJXZSlvGjkU1f2ZSI3kOCgzvOWq5G3zCIfghFNEYJMrfhGs+Z mYoo3Tz2Oe7IeKyfA+1Wa3MKd6fqPooj+w== X-Google-Smtp-Source: ALg8bN7UAcA1Ls/ZJDUqC+Xytz6x6QA0TXtrVGjeEFk7t+KfSGNaqeEdAC2IMpQLBdPZL54NIoLkRA== X-Received: by 2002:a1c:7306:: with SMTP id d6mr17474454wmb.98.1548699075994; Mon, 28 Jan 2019 10:11:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:42 +0000 Message-Id: <20190128181047.20781-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 Subject: [Qemu-devel] [PULL 21/26] aspeed/smc: snoop SPI transfers to fake dummy cycles X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: C=C3=A9dric Le Goater The m25p80 models dummy cycles using byte transfers. This works well when the transfers are initiated by the QEMU model of a SPI controller but when these are initiated by the OS, it breaks emulation. Snoop the SPI transfer to catch commands requiring dummy cycles and replace them with byte transfers compatible with the m25p80 model. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Alistair Francis Reviewed-by: Francisco Iglesias Message-id: 20190124140519.13838-5-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/ssi/aspeed_smc.h | 3 + hw/ssi/aspeed_smc.c | 115 +++++++++++++++++++++++++++++++++++- 2 files changed, 115 insertions(+), 3 deletions(-) diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 1f557313fa9..3b1e7fce6c8 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -98,6 +98,9 @@ typedef struct AspeedSMCState { uint8_t conf_enable_w0; =20 AspeedSMCFlash *flashes; + + uint8_t snoop_index; + uint8_t snoop_dummies; } AspeedSMCState; =20 #endif /* ASPEED_SMC_H */ diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 9f3b6f4b450..f1e66870d71 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -145,6 +145,9 @@ /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ =20 +#define SNOOP_OFF 0xFF +#define SNOOP_START 0x0 + /* * Default segments mapping addresses and size for each slave per * controller. These can be changed when board is initialized with the @@ -566,6 +569,101 @@ static uint64_t aspeed_smc_flash_read(void *opaque, h= waddr addr, unsigned size) return ret; } =20 +/* + * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a + * common include header. + */ +typedef enum { + READ =3D 0x3, READ_4 =3D 0x13, + FAST_READ =3D 0xb, FAST_READ_4 =3D 0x0c, + DOR =3D 0x3b, DOR_4 =3D 0x3c, + QOR =3D 0x6b, QOR_4 =3D 0x6c, + DIOR =3D 0xbb, DIOR_4 =3D 0xbc, + QIOR =3D 0xeb, QIOR_4 =3D 0xec, + + PP =3D 0x2, PP_4 =3D 0x12, + DPP =3D 0xa2, + QPP =3D 0x32, QPP_4 =3D 0x34, +} FlashCMD; + +static int aspeed_smc_num_dummies(uint8_t command) +{ + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 4; + default: + return -1; + } +} + +static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, + unsigned size) +{ + AspeedSMCState *s =3D fl->controller; + uint8_t addr_width =3D aspeed_smc_flash_is_4byte(fl) ? 4 : 3; + + if (s->snoop_index =3D=3D SNOOP_OFF) { + return false; /* Do nothing */ + + } else if (s->snoop_index =3D=3D SNOOP_START) { + uint8_t cmd =3D data & 0xff; + int ndummies =3D aspeed_smc_num_dummies(cmd); + + /* + * No dummy cycles are expected with the current command. Turn + * off snooping and let the transfer proceed normally. + */ + if (ndummies <=3D 0) { + s->snoop_index =3D SNOOP_OFF; + return false; + } + + s->snoop_dummies =3D ndummies * 8; + + } else if (s->snoop_index >=3D addr_width + 1) { + + /* The SPI transfer has reached the dummy cycles sequence */ + for (; s->snoop_dummies; s->snoop_dummies--) { + ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); + } + + /* If no more dummy cycles are expected, turn off snooping */ + if (!s->snoop_dummies) { + s->snoop_index =3D SNOOP_OFF; + } else { + s->snoop_index +=3D size; + } + + /* + * Dummy cycles have been faked already. Ignore the current + * SPI transfer + */ + return true; + } + + s->snoop_index +=3D size; + return false; +} + static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t dat= a, unsigned size) { @@ -581,6 +679,10 @@ static void aspeed_smc_flash_write(void *opaque, hwadd= r addr, uint64_t data, =20 switch (aspeed_smc_flash_mode(fl)) { case CTRL_USERMODE: + if (aspeed_smc_do_snoop(fl, data, size)) { + break; + } + for (i =3D 0; i < size; i++) { ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); } @@ -613,7 +715,9 @@ static const MemoryRegionOps aspeed_smc_flash_ops =3D { =20 static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl) { - const AspeedSMCState *s =3D fl->controller; + AspeedSMCState *s =3D fl->controller; + + s->snoop_index =3D aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOO= P_START; =20 qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); } @@ -652,6 +756,9 @@ static void aspeed_smc_reset(DeviceState *d) if (s->ctrl->segments =3D=3D aspeed_segments_fmc) { s->regs[s->r_conf] |=3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0); } + + s->snoop_index =3D SNOOP_OFF; + s->snoop_dummies =3D 0; } =20 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int si= ze) @@ -793,10 +900,12 @@ static void aspeed_smc_realize(DeviceState *dev, Erro= r **errp) =20 static const VMStateDescription vmstate_aspeed_smc =3D { .name =3D "aspeed.smc", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), + VMSTATE_UINT8(snoop_index, AspeedSMCState), + VMSTATE_UINT8(snoop_dummies, AspeedSMCState), VMSTATE_END_OF_LIST() } }; --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 15487018239859.60779360368906; Mon, 28 Jan 2019 10:57:03 -0800 (PST) Received: from localhost ([127.0.0.1]:37063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goC5Z-0005Sr-Qq for importer@patchew.org; Mon, 28 Jan 2019 13:56:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41259) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNf-0003BY-K6 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Ys-Pt for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:35 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:44053) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000P1-Fn for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wr1-x429.google.com with SMTP id z5so19120114wrt.11 for ; Mon, 28 Jan 2019 10:11:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 22/26] tests/microbit-test: Add tests for nRF51 NVMC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Steffen G=C3=B6rtz Signed-off-by: Steffen G=C3=B6rtz Signed-off-by: Stefan Hajnoczi Acked-by: Thomas Huth Message-id: 20190124141147.8416-1-stefanha@redhat.com Signed-off-by: Peter Maydell --- tests/microbit-test.c | 108 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index 3bad947b6cd..04e199ec33f 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -21,6 +21,7 @@ #include "hw/arm/nrf51.h" #include "hw/char/nrf51_uart.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" #include "hw/i2c/microbit_i2c.h" =20 @@ -156,6 +157,112 @@ static void test_microbit_i2c(void) qtest_quit(qts); } =20 +#define FLASH_SIZE (256 * NRF51_PAGE_SIZE) + +static void fill_and_erase(QTestState *qts, hwaddr base, hwaddr size, + uint32_t address_reg) +{ + hwaddr i; + + /* Erase Page */ + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + qtest_writel(qts, NRF51_NVMC_BASE + address_reg, base); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + /* Check memory */ + for (i =3D 0; i < size / 4; i++) { + g_assert_cmpuint(qtest_readl(qts, base + i * 4), =3D=3D, 0xFFFFFFF= F); + } + + /* Fill memory */ + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < size / 4; i++) { + qtest_writel(qts, base + i * 4, i); + g_assert_cmpuint(qtest_readl(qts, base + i * 4), =3D=3D, i); + } + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); +} + +static void test_nrf51_nvmc(void) +{ + uint32_t value; + hwaddr i; + QTestState *qts =3D qtest_init("-M microbit"); + + /* Test always ready */ + value =3D qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_READY); + g_assert_cmpuint(value & 0x01, =3D=3D, 0x01); + + /* Test write-read config register */ + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x03); + g_assert_cmpuint(qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), + =3D=3D, 0x03); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + g_assert_cmpuint(qtest_readl(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), + =3D=3D, 0x00); + + /* Test PCR0 */ + fill_and_erase(qts, NRF51_FLASH_BASE, NRF51_PAGE_SIZE, + NRF51_NVMC_ERASEPCR0); + fill_and_erase(qts, NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0); + + /* Test PCR1 */ + fill_and_erase(qts, NRF51_FLASH_BASE, NRF51_PAGE_SIZE, + NRF51_NVMC_ERASEPCR1); + fill_and_erase(qts, NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1); + + /* Erase all */ + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < FLASH_SIZE / 4; i++) { + qtest_writel(qts, NRF51_FLASH_BASE + i * 4, i); + g_assert_cmpuint(qtest_readl(qts, NRF51_FLASH_BASE + i * 4), =3D= =3D, i); + } + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < FLASH_SIZE / 4; i++) { + g_assert_cmpuint(qtest_readl(qts, NRF51_FLASH_BASE + i * 4), + =3D=3D, 0xFFFFFFFF); + } + + /* Erase UICR */ + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), + =3D=3D, 0xFFFFFFFF); + } + + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + qtest_writel(qts, NRF51_UICR_BASE + i * 4, i); + g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), =3D=3D= , i); + } + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); + qtest_writel(qts, NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + g_assert_cmpuint(qtest_readl(qts, NRF51_UICR_BASE + i * 4), + =3D=3D, 0xFFFFFFFF); + } + + qtest_quit(qts); +} + static void test_nrf51_gpio(void) { size_t i; @@ -392,6 +499,7 @@ int main(int argc, char **argv) =20 qtest_add_func("/microbit/nrf51/uart", test_nrf51_uart); qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); qtest_add_func("/microbit/microbit/i2c", test_microbit_i2c); =20 --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=R/4vd1ag6pYGkr7XeNEY4GO1VSptJA7C37IWDHT1Zt4=; b=deTbDKrmZHDZ+l0XY6XpK6rJnxny5uo25bLg53D1upilT+1Ptb302z4DKnYHyaQRsG b0cpwL5Oh26roIqLLYAZFghem5J6iE+n8L9Fj74VOmuE7cQJuujJ890f9eiBjk9IyNVQ Qt33y4UgRHvtqVF5IrROHYzr1Zjv5Zhphnt3Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R/4vd1ag6pYGkr7XeNEY4GO1VSptJA7C37IWDHT1Zt4=; b=XlEJQ/IwZBdfzLW/xpmWniSCRwbWLhdPglnUPq1Dn4OpkXFqZPmbAftMBYBCYTGdI5 BJeTpvAjHK4zxCrLQlyIrnGkuQHw3/Bs/ubNicm7nWzJSC9V2ouyL4ry4N5p5gLpWKAc Cg6sRWIfjG5UTYiTYRwRn3pR/mQr9Bg+Zu5QPi5wtzSNWqRq0xmsGLC8Os6BC9lUQUZb qpn/rOUNFayM4VSrPH+dPMpktwINAh7QdtZOt0i46w2bR3relIlh2yYjf4k6h5rdeTu+ oZ7b2zRqDrCMEVJJv87Fv7BLoPBTGgOaSGc/x4AERAI6jTTnw+cG1Z0WANQsepdow/wR mKAw== X-Gm-Message-State: AJcUukeGJlrzxSuQvPZt8KOcFKM+vLXXf3Xv9oIRYe3ZNELfH+/4y8PY GydDmxsNO8xJwIEuW3kBhrsveVIsKZl8Fw== X-Google-Smtp-Source: ALg8bN4/0KoQFuyvePBMFUK4HALvERxITowYi7p3ogIFLzSzGm2smWsYaM9bn/KR+wN1oQ40uSAEug== X-Received: by 2002:a7b:cf30:: with SMTP id m16mr2740247wmg.22.1548699078767; Mon, 28 Jan 2019 10:11:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:44 +0000 Message-Id: <20190128181047.20781-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PULL 23/26] hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the cluster implementation doesn't have any constraints on the ordering of realizing the TYPE_CPU_CLUSTER and populating it with child objects. We want to impose a constraint that realize must happen only after all the child objects are added, so move the realize of rpu_cluster. (The apu_cluster is already realized after child population.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20190121152218.9592-2-peter.maydell@linaro.org --- hw/arm/xlnx-zynqmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 70cbe6bd475..4f8bc41d9d4 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -188,8 +188,6 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, = const char *boot_cpu, &error_abort, NULL); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); =20 - qdev_init_nofail(DEVICE(&s->rpu_cluster)); - for (i =3D 0; i < num_rpus; i++) { char *name; =20 @@ -217,6 +215,8 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, = const char *boot_cpu, return; } } + + qdev_init_nofail(DEVICE(&s->rpu_cluster)); } =20 static void xlnx_zynqmp_init(Object *obj) --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700991841838.7379169873841; Mon, 28 Jan 2019 10:43:11 -0800 (PST) Received: from localhost ([127.0.0.1]:36836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBsE-0003ic-KQ for importer@patchew.org; Mon, 28 Jan 2019 13:43:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNe-0003AX-Oi for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Y4-DX for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:53993) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000QW-5F for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wm1-x333.google.com with SMTP id d15so15040831wmb.3 for ; Mon, 28 Jan 2019 10:11:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oRVjJfEtFzX/5cZWSR/FAOkkZFICB7IbKExbJeRsgog=; b=XvhjrMa1FJe/+qbEgRcJBBHjc6kNQ5OSWEFi2DXMVzcUQg+bABI6NTsgGj0lbYUeih r4wnI4wxV/jvIIfbLNjQARkf5RLxfbAdLcbK4/dvUVpF1y+s/90uRGcj47wqDkw4t79r RyIXLt7Z/2xyY7Hj7iYkvYxPDnT1cTsic2quA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oRVjJfEtFzX/5cZWSR/FAOkkZFICB7IbKExbJeRsgog=; b=q/tjn4vabo3BwEfQ7ckujAvmbbrpccRq/eXUexxzV2IfGASYBkxzsERL2YiRcmfdDT bhaKtLYvJGenh4cYrPVaqG7CQbrLITAs/89mhfWZYy4Rd+zXTHCzyXdYGx9ZdZaCnzHg e4qtkGlWzIUucW2KpCj0o01eGE/YqVL8lRL4+7I21BeFaIw/YlxQyMeYUE+rBi81+0KO S14oaXQkDTMjMzo4015AsgElFjstnm0YqnrKUnPph+0VtB8jth1mU3y/YzN6MiV/DgiZ vViPhcP69PCwWTPjpcYfFsDGrBBV31fA62b2lVRxNKTEGLPgAjdqS5Km1y1UCgCkF8xz 9+aw== X-Gm-Message-State: AJcUukcGP9sVG6eJ1RP9RnSDE9+YFo617e+2rzDaLeLfhuuIOqsdJ1Q7 rpM5KHYz5k7NDpcjZ3nH9L7cPrwHmtVG6A== X-Google-Smtp-Source: ALg8bN6+pboZFIVv1F/LikEfvbK25MgEsZawzy1/r8uJa8BCQDXjEi2kEXZpNoauNkT/sbbxXje/+A== X-Received: by 2002:a1c:c303:: with SMTP id t3mr16945574wmf.94.1548699080198; Mon, 28 Jan 2019 10:11:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:45 +0000 Message-Id: <20190128181047.20781-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 Subject: [Qemu-devel] [PULL 24/26] qom/cpu: Add cluster_index to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. We can at least put in a check that the cluster contains at least one CPU, which should catch the typical cases of "realized cluster too early" or "forgot to parent the CPUs into it". The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20190121152218.9592-3-peter.maydell@linaro.org --- include/hw/cpu/cluster.h | 24 +++++++++++++++++++++ include/qom/cpu.h | 7 ++++++ hw/cpu/cluster.c | 46 ++++++++++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 78 insertions(+) diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..549c2d31d43 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,36 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPU= s do * not have the same view of memory (for example the main CPU and a manage= ment * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * The CPUs may be either direct children of the cluster object, or indire= ct + * children (e.g. children of children of the cluster object). + * + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realiz= ed + * object and no way for the parent to be notified when a new child is add= ed + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to. The cluster will assert that + * it contains at least one CPU, which should catch most inadvertent + * violations of this constraint.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ =20 #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) =20 +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and sh= ould diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 16bbed1ae09..4c2feb9c17b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -280,6 +280,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assign= ed + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_C= LUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -405,6 +410,7 @@ struct CPUState { =20 /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1111,5 +1117,6 @@ extern const struct VMStateDescription vmstate_cpu_co= mmon; #endif /* NEED_CPU_H */ =20 #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 =20 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..25f90702b16 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,65 @@ =20 #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" =20 static Property cpu_cluster_properties[] =3D { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; =20 +typedef struct CallbackData { + CPUClusterState *cluster; + int cpu_count; +} CallbackData; + +static int add_cpu_to_cluster(Object *obj, void *opaque) +{ + CallbackData *cbdata =3D opaque; + CPUState *cpu =3D (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + + if (cpu) { + cpu->cluster_index =3D cbdata->cluster->cluster_id; + cbdata->cpu_count++; + } + return 0; +} + +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster =3D CPU_CLUSTER(dev); + Object *cluster_obj =3D OBJECT(dev); + CallbackData cbdata =3D { + .cluster =3D cluster, + .cpu_count =3D 0, + }; + + if (cluster->cluster_id >=3D MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_child_foreach_recursive(cluster_obj, add_cpu_to_cluster, &cbdat= a); + + /* + * A cluster with no CPUs is a bug in the board/SoC code that created = it; + * if you hit this during development of new code, check that you have + * created the CPUs and parented them into the cluster object before + * realizing the cluster object. + */ + assert(cbdata.cpu_count > 0); +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->props =3D cpu_cluster_properties; + dc->realize =3D cpu_cluster_realize; } =20 static const TypeInfo cpu_cluster_type_info =3D { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc =3D CPU_GET_CLASS(obj); =20 cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; + cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */ --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548700926205259.7077567892021; Mon, 28 Jan 2019 10:42:06 -0800 (PST) Received: from localhost ([127.0.0.1]:36828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBrB-0002mE-73 for importer@patchew.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ti2xj1PcDq61eeji1venmmD+roppUY4rxNqkk9jPSqc=; b=LdAyYGshOHISJc/vmgJ863LIrpVt4YjxX5Y8GQeaOwb784Fn8oyO+oFPWEVNlj8qg1 xL5q7HNpulzxepq0epdNrpVO1jU6hCoGDFhikq/aoAgECtjSj3wkoKXC7wCAoz0TmuJJ hlvJU4OjLKUw5NHCxoL2X2Jp58BDHb2D3la6Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ti2xj1PcDq61eeji1venmmD+roppUY4rxNqkk9jPSqc=; b=CdkRmQvcCRrFQa7PfgS/yIFEGQPmUiQB+joSffYJbEzN95pKfzsOb7Pc6U2TtNMcdM kGpzNwgSdhbYLRqDd7o/t9faRcI+ysiPAQk0g61dERu6KAbjkc3NPS0gwNX6DVQ1cQf+ EdNdGN5qWBTGgUFCffBXGCPOQShvBM8VkhDa0I2VpvgMbPCCZcD1RUU5nRfm8L1s3A9m yLjZAHyGavLRy5LjGHFvcJUTOXJC6Gq2vjKOUQhRGj4v7ziy0rcI5S6u1Xbk5jqIzyTf 6B7TPUMfOOIu/ASgY0ac+SM9ZYLmaykrqTi6Hxyqjp3ckyQA87QN6divgR6h4SwdEKog Clbg== X-Gm-Message-State: AJcUukf3aRmT9HPYDY+G+bHKd/BgqieuzxjxdwFC9RKbmXesTKPoMW12 FEq0zYg8DFboymtQ6IW/Tb1oTBPpCWL3IA== X-Google-Smtp-Source: ALg8bN5wfu8fTw3LQr7QEoCQ8sFH7bx6DZWN/qIQ33oaN7KjWZwGoLyKpVHU2n+XFpOiQpMmGSWeSg== X-Received: by 2002:a7b:c1d7:: with SMTP id a23mr17169876wmj.48.1548699081545; Mon, 28 Jan 2019 10:11:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:46 +0000 Message-Id: <20190128181047.20781-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 25/26] accel/tcg: Add cluster number to TCG TB hash X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Include the cluster number in the hash we use to look up TBs. This is important because a TB that is valid for one cluster at a given physical address and set of CPU flags is not necessarily valid for another: the two clusters may have different views of physical memory, or may have different CPU features (eg FPU present or absent). We put the cluster number in the high 8 bits of the TB cflags. This gives us up to 256 clusters, which should be enough for anybody. If we ever need more, or need more bits in cflags for other purposes, we could make tb_hash_func() take more data (and expand qemu_xxhash7() to qemu_xxhash8()). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20190121152218.9592-4-peter.maydell@linaro.org --- include/exec/exec-all.h | 4 +++- accel/tcg/cpu-exec.c | 3 +++ accel/tcg/translate-all.c | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 815e5b1e838..aa7b81aaf01 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -351,9 +351,11 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held = */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 /* cflags' mask for hashing/comparison */ #define CF_HASH_MASK \ - (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL) + (CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL | CF_CLUSTER= _MASK) =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 870027d4359..6c4a33262f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -325,6 +325,9 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targe= t_ulong pc, struct tb_desc desc; uint32_t h; =20 + cf_mask &=3D ~CF_CLUSTER_MASK; + cf_mask |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; + desc.env =3D (CPUArchState *)cpu->env_ptr; desc.cs_base =3D cs_base; desc.flags =3D flags; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8cb8c8870e6..7364e8a071f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1688,6 +1688,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags |=3D CF_NOCACHE | 1; } =20 + cflags &=3D ~CF_CLUSTER_MASK; + cflags |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; + buffer_overflow: tb =3D tb_alloc(pc); if (unlikely(!tb)) { --=20 2.20.1 From nobody Wed Jun 26 10:54:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 154870171842484.01166925130917; Mon, 28 Jan 2019 10:55:18 -0800 (PST) Received: from localhost ([127.0.0.1]:37019 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goC3s-0004BO-CY for importer@patchew.org; Mon, 28 Jan 2019 13:55:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goBNe-0003AN-Jg for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goBNc-0000Z9-RJ for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:34 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39124) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goBNc-0000RX-HU for qemu-devel@nongnu.org; Mon, 28 Jan 2019 13:11:32 -0500 Received: by mail-wm1-x334.google.com with SMTP id y8so14923697wmi.4 for ; Mon, 28 Jan 2019 10:11:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b18sm97910681wrw.83.2019.01.28.10.11.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 28 Jan 2019 10:11:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nwGwMpkRmjjdlLHlXvvGrcmomf1JI1Bu3RSQ3qEja4k=; b=NreYdD4d896/HpdbtNpfU3CfXxu2t2+UeUoKTijBCTylJKgSoIf0hano+ykcMIivNc /rcwlwK6b7wsrCCAAlgg1gzoyzqMDyNqA3UcivfNDwBtK1dkZZQ96+uL/CtCLmmA/2qW Sfg0x1el+AVD51X8b9gpoKHeU0MuU/huLX1oM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nwGwMpkRmjjdlLHlXvvGrcmomf1JI1Bu3RSQ3qEja4k=; b=gFGLjMW5YIDH5g6cDVMcBHGXgs5MCcfQaLfJTEtTt+U3A+R90cTsA7N4AlhpkJ4TXT ikYETCWHJC6C6LxYv6yFiuDidbS0R/h/VcZkQ1d3rxY9xqOZKyr4B/SEtU7av4ji2dhW X0vEVSguvXQYnf/mUdz+KVfBJ+PuOzTfbcdf5xAPYNU2mpUuZPgudRuXz9Le1/ZuLsNS YDSVJc6dnvYvtF5Ozhw+S2wJ17xuRNmF+yAlvwMkf2D9VVsr3BsCP+dCIndGKJm0mD0Z c4uWnKIHdCvwOlJDD+LQ8IR+v8d8rgbA7MnSPzPxuaFFymNuX3RL066p1C3MEiH3VT2U vF0A== X-Gm-Message-State: AJcUukcNxLkyY8S/vHwSOqAUwAe7RMpo/49hJ3rXfdSjhAONpP67HLz3 qyk9Fb5ZL62/jdxhrv0cPiJ/0YnCqQ5uRw== X-Google-Smtp-Source: ALg8bN40El3H4euxZYf7xLdCpN/diEvv7BInxsznNhqveSEDNDcFnzehZhZlaAgy9MXqPj1m+lUvOg== X-Received: by 2002:a7b:c04e:: with SMTP id u14mr18475699wmc.113.1548699082979; Mon, 28 Jan 2019 10:11:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 18:10:47 +0000 Message-Id: <20190128181047.20781-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128181047.20781-1-peter.maydell@linaro.org> References: <20190128181047.20781-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 26/26] gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we're keeping the cluster index in the CPUState, we don't need to jump through hoops in gdb_get_cpu_pid() to find the associated cluster object. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Reviewed-by: Edgar E. Iglesias Message-id: 20190121152218.9592-5-peter.maydell@linaro.org --- gdbstub.c | 48 +++++------------------------------------------- 1 file changed, 5 insertions(+), 43 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index d4cc6ecf99b..3129b5c2842 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -644,50 +644,12 @@ static int memtox(char *buf, const char *mem, int len) =20 static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu) { -#ifndef CONFIG_USER_ONLY - gchar *path, *name =3D NULL; - Object *obj; - CPUClusterState *cluster; - uint32_t ret; - - path =3D object_get_canonical_path(OBJECT(cpu)); - - if (path =3D=3D NULL) { - /* Return the default process' PID */ - ret =3D s->processes[s->process_num - 1].pid; - goto out; - } - - name =3D object_get_canonical_path_component(OBJECT(cpu)); - assert(name !=3D NULL); - - /* - * Retrieve the CPU parent path by removing the last '/' and the CPU n= ame - * from the CPU canonical path. - */ - path[strlen(path) - strlen(name) - 1] =3D '\0'; - - obj =3D object_resolve_path_type(path, TYPE_CPU_CLUSTER, NULL); - - if (obj =3D=3D NULL) { - /* Return the default process' PID */ - ret =3D s->processes[s->process_num - 1].pid; - goto out; - } - - cluster =3D CPU_CLUSTER(obj); - ret =3D cluster->cluster_id + 1; - -out: - g_free(name); - g_free(path); - - return ret; - -#else /* TODO: In user mode, we should use the task state PID */ - return s->processes[s->process_num - 1].pid; -#endif + if (cpu->cluster_index =3D=3D UNASSIGNED_CLUSTER_INDEX) { + /* Return the default process' PID */ + return s->processes[s->process_num - 1].pid; + } + return cpu->cluster_index + 1; } =20 static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid) --=20 2.20.1