From nobody Tue Feb 10 04:17:37 2026 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15486973375488.896840191923616; Mon, 28 Jan 2019 09:42:17 -0800 (PST) Received: from localhost ([127.0.0.1]:35961 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAv2-0003cV-9b for importer@patchew.org; Mon, 28 Jan 2019 12:42:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAsu-00025b-Vi for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goAss-0003X8-A6 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:48 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:37581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goAsr-0003Uf-Rn for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:46 -0500 Received: by mail-wm1-x32e.google.com with SMTP id g67so14840787wmd.2 for ; Mon, 28 Jan 2019 09:39:44 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f191sm82872wmg.12.2019.01.28.09.39.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 09:39:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B69653E0733; Mon, 28 Jan 2019 17:39:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rtKjTx0NfXwlZhYnnXHxQ+aJeket67uwad3MWD6/3qo=; b=iuoXdebq6YPYmksh+Vq8g0LZ/VXj9FgxRORPav+CyhCsBjmiEPiZ5pWJzMb+knxFIH k+5sKyVK19W6W2tQST7oQ3HgCkE5wmPZ91TnjSlbOGHv4Iy7FObupw4r0SM+Mu01GoRw 0Wsx7bvGCZIsG0vBMOjUTRJlvhW+uH9QVwV/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rtKjTx0NfXwlZhYnnXHxQ+aJeket67uwad3MWD6/3qo=; b=FTLXyiJJ8TqD0Gs34QfNQoX5qv90jT1foOTKjl6PXrKrCC1w0hFxq68eXLEPc0JLva 7Yrwd/ltr06BIajRXXalN59QS1wRZxqjST2zlR6NlNYfaBZerWi2B8IFLzfVzsPrjT3B jLOhJS2fEzqhUiycTHimpYt65DUYch9xXEkoePyjh0PlGuGXL3Ay6uAAvfG65h2FMHtZ QRJ051FrLRBxens1brg6RWkjyn62kC1pG0wWydU3q5mlj8Qn7FFsDpqmp/w8wvSkdyUy bFwkDzo6jZL0B1fUh8WwAPpm938EmGGf9liZ/WUNKN62oyP8trnMr1qgbkv7J9bmI4ic ggeg== X-Gm-Message-State: AJcUukfaGCDwl9eGggBmv5gQosPP9FfTTXgclZ7QzQFq5PJ03ECHfO1Q 34ry9fBPTPrAZj2pK6uetp1nZA== X-Google-Smtp-Source: ALg8bN6c+CJSgwrpXEhvZeLN9rNf3YJLxfttuKM4vp1r0Osi7w6QWKT8d6/GFJ4nynKdhgLQwmcsmA== X-Received: by 2002:a1c:7dd7:: with SMTP id y206mr17917726wmc.50.1548697183666; Mon, 28 Jan 2019 09:39:43 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:38 +0000 Message-Id: <20190128173940.25813-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PATCH v1 2/4] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. For this we use the PL0U_R permission mask which allows this access in CONFIG_USER mode. Some registers only return a subset of their contents so we need specific CONFIG_USER_ONLY logic to do this. Signed-off-by: Alex Benn=C3=A9e --- v4 - tweak commit message - use PL0U_R instead of PL1U_R to be less confusing - more CONFIG_USER logic for special cases - mask a bunch of bits for some registers --- target/arm/helper.c | 51 ++++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 42c1c0b144..68808e7293 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3543,7 +3543,7 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, + .access =3D PL0U_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW = }, REGINFO_SENTINEL }; =20 @@ -5488,6 +5488,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) return pfr1; } =20 +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -5498,6 +5499,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } return pfr0; } +#endif =20 /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -5799,18 +5801,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] =3D { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. For + * user-mode HWCAP_CPUID emulation the GIC bits are masked + * anyway. */ { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, +#ifndef CONFIG_USER_ONLY .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .readfn =3D id_aa64pfr0_read, - .writefn =3D arm_cp_write_ignore }, + .writefn =3D arm_cp_write_ignore +#else + .access =3D PL0U_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->isar.id_aa64pfr0 & 0x000f000f0ff0000ULL +#endif + }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64pfr1}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, @@ -5839,11 +5849,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, @@ -5871,11 +5881,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, +#ifdef CONFIG_USER_ONLY + .resetvalue =3D cpu->isar.id_aa64isar0 & 0x000fffffff0ffff0U= LL +#else + .resetvalue =3D cpu->isar.id_aa64isar0 +#endif + }, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64isar1 }, { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, @@ -5903,11 +5918,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64mmfr0 }, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64mmfr1 }, { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, @@ -6211,7 +6226,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .access =3D PL0U_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D= cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ @@ -6223,7 +6238,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, +#ifdef CONFIG_USER_ONLY + .access =3D PL0U_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 /* HW_CPUID IMPDEF fields are 0 */ }, +#else + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->revidr }, +#endif REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { --=20 2.17.1