From nobody Fri Nov 7 15:31:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154869737144658.65969706175633; Mon, 28 Jan 2019 09:42:51 -0800 (PST) Received: from localhost ([127.0.0.1]:35967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAvq-0004Ip-AY for importer@patchew.org; Mon, 28 Jan 2019 12:42:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAst-00024b-QO for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goAss-0003Wm-5z for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:47 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:52761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goAsr-0003Ty-HL for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:45 -0500 Received: by mail-wm1-x342.google.com with SMTP id m1so14933824wml.2 for ; Mon, 28 Jan 2019 09:39:43 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id t199sm348163wmt.1.2019.01.28.09.39.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 09:39:40 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8D6913E050B; Mon, 28 Jan 2019 17:39:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Ma4KyFZWMZDWKwrBGwmM0xc8BBD1DkWp6hR/NBgppo=; b=gAuz06FKTv9Y8r9Da05CsvEAmSMjpl8j8HcIrtT9DshKG2mT3OAF9rzXpyStPlRL+a U+4795imPXuovl0bqoeHeqAsYYT8kfGxl4ug5zf4Y7Ag5H4MJWAzpBtHKEWpicxHhb06 9fEucmscjteZp9q3BNn8pEcvTMZsfhmK5Uc/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Ma4KyFZWMZDWKwrBGwmM0xc8BBD1DkWp6hR/NBgppo=; b=BgUM+z7cpPINT00fB47d6YGtFQjWR6TKaqsbY8bioWecH1hqBirwjwtvdAQuQkNgwm jWHIr4GiHs/ZEorAbPTpLPPVMbMEa+FpbkEbp+AxhKMGypZ1aAxY4T9cHsKAcO+j2Zkm 01cGH/WAVsuEz9UjNgf3BpZtRZ3PZSRDoK4l36NBJ/bWnICaJN2LIIDHCVmUsJUV8umY FIOx2s9rJUPPh58oikeoz94zqxJ2jaaIQZTYGrULDigH4PUIalDRPXVazOX51MoU23hA qHZr5osMoa0eN8paZrlRn8rQprFIAfcmQ4DAyOK1ojipJlVR3sd9rpY2IeLvtBdLVJ+M 97xA== X-Gm-Message-State: AJcUukeCVTVKPD7sDYyfq/dyzZ4s+HgreTrYerFeV1AHiTJrFsAo7Atz V+9DrKGAlqoYtIy3X7FfnYkI2A== X-Google-Smtp-Source: ALg8bN7WYsgXH9+L1IJjfekfx2wanZZuDC520yUiRV14pxfwMrx8v7G1MVBU7194bdzCLJJ3cRx9Jw== X-Received: by 2002:a7b:ce84:: with SMTP id q4mr18921037wmj.105.1548697182179; Mon, 28 Jan 2019 09:39:42 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:37 +0000 Message-Id: <20190128173940.25813-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v1 1/4] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 12 ++++++++++++ target/arm/helper.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff81db420d..3b3c359cca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2202,6 +2202,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) =20 +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index 92666e5208..42c1c0b144 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6731,7 +6731,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state !=3D ARM_CP_STATE_AA32) { int mask =3D 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask =3D PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask =3D PL1_RW; break; --=20 2.17.1 From nobody Fri Nov 7 15:31:48 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15486973375488.896840191923616; Mon, 28 Jan 2019 09:42:17 -0800 (PST) Received: from localhost ([127.0.0.1]:35961 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAv2-0003cV-9b for importer@patchew.org; Mon, 28 Jan 2019 12:42:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAsu-00025b-Vi for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goAss-0003X8-A6 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:48 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:37581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goAsr-0003Uf-Rn for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:46 -0500 Received: by mail-wm1-x32e.google.com with SMTP id g67so14840787wmd.2 for ; Mon, 28 Jan 2019 09:39:44 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f191sm82872wmg.12.2019.01.28.09.39.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 09:39:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B69653E0733; Mon, 28 Jan 2019 17:39:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rtKjTx0NfXwlZhYnnXHxQ+aJeket67uwad3MWD6/3qo=; b=iuoXdebq6YPYmksh+Vq8g0LZ/VXj9FgxRORPav+CyhCsBjmiEPiZ5pWJzMb+knxFIH k+5sKyVK19W6W2tQST7oQ3HgCkE5wmPZ91TnjSlbOGHv4Iy7FObupw4r0SM+Mu01GoRw 0Wsx7bvGCZIsG0vBMOjUTRJlvhW+uH9QVwV/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rtKjTx0NfXwlZhYnnXHxQ+aJeket67uwad3MWD6/3qo=; b=FTLXyiJJ8TqD0Gs34QfNQoX5qv90jT1foOTKjl6PXrKrCC1w0hFxq68eXLEPc0JLva 7Yrwd/ltr06BIajRXXalN59QS1wRZxqjST2zlR6NlNYfaBZerWi2B8IFLzfVzsPrjT3B jLOhJS2fEzqhUiycTHimpYt65DUYch9xXEkoePyjh0PlGuGXL3Ay6uAAvfG65h2FMHtZ QRJ051FrLRBxens1brg6RWkjyn62kC1pG0wWydU3q5mlj8Qn7FFsDpqmp/w8wvSkdyUy bFwkDzo6jZL0B1fUh8WwAPpm938EmGGf9liZ/WUNKN62oyP8trnMr1qgbkv7J9bmI4ic ggeg== X-Gm-Message-State: AJcUukfaGCDwl9eGggBmv5gQosPP9FfTTXgclZ7QzQFq5PJ03ECHfO1Q 34ry9fBPTPrAZj2pK6uetp1nZA== X-Google-Smtp-Source: ALg8bN6c+CJSgwrpXEhvZeLN9rNf3YJLxfttuKM4vp1r0Osi7w6QWKT8d6/GFJ4nynKdhgLQwmcsmA== X-Received: by 2002:a1c:7dd7:: with SMTP id y206mr17917726wmc.50.1548697183666; Mon, 28 Jan 2019 09:39:43 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:38 +0000 Message-Id: <20190128173940.25813-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e Subject: [Qemu-devel] [PATCH v1 2/4] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. For this we use the PL0U_R permission mask which allows this access in CONFIG_USER mode. Some registers only return a subset of their contents so we need specific CONFIG_USER_ONLY logic to do this. Signed-off-by: Alex Benn=C3=A9e --- v4 - tweak commit message - use PL0U_R instead of PL1U_R to be less confusing - more CONFIG_USER logic for special cases - mask a bunch of bits for some registers --- target/arm/helper.c | 51 ++++++++++++++++++++++++++++++++------------- 1 file changed, 36 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 42c1c0b144..68808e7293 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3543,7 +3543,7 @@ static uint64_t mpidr_read(CPUARMState *env, const AR= MCPRegInfo *ri) static const ARMCPRegInfo mpidr_cp_reginfo[] =3D { { .name =3D "MPIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW }, + .access =3D PL0U_R, .readfn =3D mpidr_read, .type =3D ARM_CP_NO_RAW = }, REGINFO_SENTINEL }; =20 @@ -5488,6 +5488,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const = ARMCPRegInfo *ri) return pfr1; } =20 +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -5498,6 +5499,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } return pfr0; } +#endif =20 /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -5799,18 +5801,26 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] =3D { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST for system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. For + * user-mode HWCAP_CPUID emulation the GIC bits are masked + * anyway. */ { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, +#ifndef CONFIG_USER_ONLY .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .readfn =3D id_aa64pfr0_read, - .writefn =3D arm_cp_write_ignore }, + .writefn =3D arm_cp_write_ignore +#else + .access =3D PL0U_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->isar.id_aa64pfr0 & 0x000f000f0ff0000ULL +#endif + }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64pfr1}, { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, @@ -5839,11 +5849,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, @@ -5871,11 +5881,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64isar0 }, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, +#ifdef CONFIG_USER_ONLY + .resetvalue =3D cpu->isar.id_aa64isar0 & 0x000fffffff0ffff0U= LL +#else + .resetvalue =3D cpu->isar.id_aa64isar0 +#endif + }, { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64isar1 }, { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, @@ -5903,11 +5918,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D 0 }, { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64mmfr0 }, { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, + .access =3D PL0U_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.id_aa64mmfr1 }, { .name =3D "ID_AA64MMFR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, @@ -6211,7 +6226,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .access =3D PL0U_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D= cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ @@ -6223,7 +6238,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .resetvalue =3D cpu->midr }, { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D c= pu->revidr }, +#ifdef CONFIG_USER_ONLY + .access =3D PL0U_R, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 /* HW_CPUID IMPDEF fields are 0 */ }, +#else + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->revidr }, +#endif REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { --=20 2.17.1 From nobody Fri Nov 7 15:31:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548697531561978.75656650087; Mon, 28 Jan 2019 09:45:31 -0800 (PST) Received: from localhost ([127.0.0.1]:36005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAyN-0006bQ-FX for importer@patchew.org; Mon, 28 Jan 2019 12:45:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAsw-00027e-TB for qemu-devel@nongnu.org; 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Mon, 28 Jan 2019 09:39:42 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:39 +0000 Message-Id: <20190128173940.25813-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v1 3/4] linux-user/elfload: enable HWCAP_CPUID for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Acked-by: Laurent Vivier --- linux-user/elfload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 4cff9e1a31..e95c162097 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -571,6 +571,7 @@ static uint32_t get_elf_hwcap(void) =20 hwcaps |=3D ARM_HWCAP_A64_FP; hwcaps |=3D ARM_HWCAP_A64_ASIMD; + hwcaps |=3D ARM_HWCAP_A64_CPUID; =20 /* probe for the extra features */ #define GET_FEATURE_ID(feat, hwcap) \ --=20 2.17.1 From nobody Fri Nov 7 15:31:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548697432402496.48639906630706; Mon, 28 Jan 2019 09:43:52 -0800 (PST) Received: from localhost ([127.0.0.1]:35983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAwg-00054o-Vw for importer@patchew.org; Mon, 28 Jan 2019 12:43:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1goAsw-00027u-W8 for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1goAss-0003XJ-Cs for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:50 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43177) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1goAsr-0003VA-Su for qemu-devel@nongnu.org; Mon, 28 Jan 2019 12:39:46 -0500 Received: by mail-wr1-x441.google.com with SMTP id r10so19003391wrs.10 for ; Mon, 28 Jan 2019 09:39:45 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f14sm97017077wrv.56.2019.01.28.09.39.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 09:39:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 1BA6E3E07DF; Mon, 28 Jan 2019 17:39:41 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uNZOim1otVCdMzCZrGI3QsadJO/8xlW0Xrr3vFSwptQ=; b=Ip5aWhziAeS9F4J6mgEhiaBhHqZeZ3TfQJvRd2NF0ACc6AHMFkRd+CKpQl8na5755b 3W3tIYmDlCm2wtNp6YIV79qrZg6W1Mye1yufgqRNwN0I2yivuy2dNi52hVEMl0Nt0vc4 CaLWiaFZkCyiAmj9jfPxnQk23zGIhQP5sKdcs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uNZOim1otVCdMzCZrGI3QsadJO/8xlW0Xrr3vFSwptQ=; b=qwKDNuzkyWgNNl5IM3v+ARhZFNnxXQqfy1ylcLqMKNihkgO1HMjlMuKzEvnVVZLAU2 7O7x43O5UCHHDQd5iWL0RbrrmGG43i0VolTZbaBNeMgrkwysxX0FTf+khyU6r2Tx5PCf 0sS0U5ojhBnvSY8It0H7bU7ZMgz8PpkapWhUMpObbLlCfVzqLCTAT6XCKaiSEw3viA3S HDoolafwasxyx2CjxwFIzLpmzoMOArr3LLFBGYRKAokOUkXiLrU/W9mRiepxoI1zZqzM hUhGoPup/Xwa86zJWd4VkWKRoHNrIk+wHMzi4Oxxq65YopJCfWVi5M7XQV0/X10fkxvG 2BQg== X-Gm-Message-State: AHQUAuaKLP4PQZr/PJ0lrgVqlP0IqadJJeg+UXnValuzAxG8beKKwX/J mnau6vv2u9NJcPB2/Pn9juROGg== X-Google-Smtp-Source: AHgI3IaJ8UHkDJ/SD3Lta8fhbe5LF3Gof/FvmXssIWLaFqBc6FsPiliNHNQ+n/cAljG1wLky8nWmoA== X-Received: by 2002:adf:a58a:: with SMTP id g10mr1329386wrc.3.1548697184278; Mon, 28 Jan 2019 09:39:44 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 17:39:40 +0000 Message-Id: <20190128173940.25813-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190128173940.25813-1-alex.bennee@linaro.org> References: <20190128173940.25813-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v1 4/4] tests/tcg/aarch64: userspace system register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. Signed-off-by: Alex Benn=C3=A9e --- v4 - also test for extra bits that shouldn't be exposed --- tests/tcg/aarch64/Makefile.target | 2 +- tests/tcg/aarch64/sysregs.c | 120 ++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/sysregs.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 08c45b8470..cc1a7eb486 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -7,7 +7,7 @@ VPATH +=3D $(AARCH64_SRC) =20 # we don't build any of the ARM tests AARCH64_TESTS=3D$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=3Dfcvt +AARCH64_TESTS+=3Dfcvt sysregs TESTS:=3D$(AARCH64_TESTS) =20 fcvt: LDFLAGS+=3D-lm diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 0000000000..8e11288ee3 --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,120 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registe= rs.txt + */ + +#include +#include +#include +#include +#include +#include + +int failed_mask_count; + +#define get_cpu_reg(id) ({ \ + unsigned long __val =3D 0xdeadbeef; \ + asm("mrs %0, "#id : "=3Dr" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval =3D get_cpu_reg(id); \ + unsigned long __extra =3D __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); = \ + failed_mask_count++; \ + } \ +}) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc =3D (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc =3D (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] =3D pc; + } + uc->uc_mcontext.pc +=3D 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags =3D SA_SIGINFO; + sa.sa_sigaction =3D &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) !=3D 0) { + perror("sigaction"); + return 1; + } + + /* since 4.12 */ + printf("Checking CNT registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* when (getauxval(AT_HWCAP) & HWCAP_CPUID), since 4.11*/ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMDEF is exported as 0 to user-space. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, 0x000fffffff0ffff0ULL); + get_cpu_reg_check_mask(id_aa64isar1_el1, 0x00000000ffffffffULL); + get_cpu_reg(id_aa64mmfr0_el1); + get_cpu_reg(id_aa64mmfr1_el1); + get_cpu_reg_check_mask(id_aa64pfr0_el1, 0x000f000f0ff0000ULL); + get_cpu_reg(id_aa64pfr1_el1); + get_cpu_reg(id_aa64dfr0_el1); + get_cpu_reg(id_aa64dfr1_el1); + + get_cpu_reg_check_mask(midr_el1, 0x00000000ffffffffULL); + get_cpu_reg(mpidr_el1); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_mask(revidr_el1, 0x0); + + printf("Remaining registers should fail\n"); + should_fail =3D true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + + if (should_not_fail_count > 0) { + int i; + for (i =3D 0; i < should_not_fail_count; i++) { + uintptr_t pc =3D failed_pc[i]; + uint32_t insn =3D *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_mask_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count =3D=3D 1 ? 0 : 1; +} --=20 2.17.1