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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id p2sm45518687pfp.125.2019.01.28.07.59.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 07:59:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u1h6Y+1jeyggZCDYjdrFQDBu8S/E6FnZ3feRJf5H+uM=; b=dLSxUdTCzq5+3zQc76tDGeEPS6ODRGSmjKlJTz+ivzRNlXOioJUkHPnjQKo5pyqUmW IEfPbSW89gv8jfg0OcwbcNXBX2YDpyXxTP8ITtXzArRiN+MVLtdaun1tu+XiAy9geDrH QzARw8OHDuEz50CtckKGb0O1lSK23c90XWFaM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u1h6Y+1jeyggZCDYjdrFQDBu8S/E6FnZ3feRJf5H+uM=; b=qEjnbBYK2vBXCGOhvNY/7vK564pggNWOz+zmSnbDuy7BeTwg32TVNd8DGvD9lwFkwV FkZfiJyTuLvWgr9jAPzfmCTY4320UfEf1OkYWCBiRhrl9EYrW+dhsI+CLEsCDlsEyAl0 KVteBXnw3wOmrMEi8ZPkaIA1QPGNtZ5tu88VnzUC7+NX0JQXEQsYTkKvRcXpzTWrgp5H bwl3grANcHS9dVLzAdkjjm/mS6qvAywZbspEGRcKNicKlQgvV3dYnqRShHXRy4uQGa6K 1DCuwopbToA1G6Whe+dNDTJwFdiK6J8F1VSMer2WPSRV0FxddizmrrNxoXL7OuMRQoVu hmNw== X-Gm-Message-State: AJcUuke1EuJXOWl8/nPqZh8SFRZ5/0unZ8pwonJbVjqQ8q+M7iC7k3QI mrOZ/In9yjg5l/pDpTuiPIO7vJpwL2A= X-Google-Smtp-Source: ALg8bN4P5cKeXBKu4BLCnRDkurjnXBI5X2XZb7kzTeHYEJhauaQWkCAg5F23kjbiV95zPu4jBO6xnQ== X-Received: by 2002:a63:b94c:: with SMTP id v12mr20263483pgo.221.1548691174301; Mon, 28 Jan 2019 07:59:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 07:59:01 -0800 Message-Id: <20190128155907.20607-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128155907.20607-1-richard.henderson@linaro.org> References: <20190128155907.20607-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PULL 17/23] tcg/s390: enable dynamic TLB sizing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++---------------------- 2 files changed, 20 insertions(+), 27 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 394b545369..357528dd97 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -27,7 +27,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 -#define TCG_TARGET_IMPLEMENTS_DYN_TLB 0 +#define TCG_TARGET_IMPLEMENTS_DYN_TLB 1 =20 typedef enum TCGReg { TCG_REG_R0 =3D 0, diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 39ecf609a1..7db90b3bae 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1537,10 +1537,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGMemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" =20 -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. - Using the offset of the second entry in the last tlb table ensures - that we can index all of the elements of the first entry. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) +/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1]) + > 0x7ffff); +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) > 0x7ffff); =20 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB @@ -1552,48 +1552,41 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGRe= g addr_reg, TCGMemOp opc, unsigned a_bits =3D get_alignment_bits(opc); unsigned s_mask =3D (1 << s_bits) - 1; unsigned a_mask =3D (1 << a_bits) - 1; + int mask_off =3D offsetof(CPUArchState, tlb_mask[mem_index]); + int table_off =3D offsetof(CPUArchState, tlb_table[mem_index]); int ofs, a_off; uint64_t tlb_mask; =20 + tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); + tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + /* For aligned accesses, we check the first byte and include the align= ment bits within the address. For unaligned access, we check that we do= n't cross pages using the address of the last byte of the access. */ a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - - if (s390_facilities & FACILITY_GEN_INST_EXT) { - tcg_out_risbg(s, TCG_REG_R2, addr_reg, - 64 - CPU_TLB_BITS - CPU_TLB_ENTRY_BITS, - 63 - CPU_TLB_ENTRY_BITS, - 64 + CPU_TLB_ENTRY_BITS - TARGET_PAGE_BITS, 1); - if (a_off) { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_= off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); - } else { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); - } + if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); } else { - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_I64, TCG_REG_R2, - (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); } =20 if (is_ld) { - ofs =3D offsetof(CPUArchState, tlb_table[mem_index][0].addr_read); + ofs =3D offsetof(CPUTLBEntry, addr_read); } else { - ofs =3D offsetof(CPUArchState, tlb_table[mem_index][0].addr_write); + ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_mem(s, RX_C, RXY_CY, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, of= s); + tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); } else { - tcg_out_mem(s, 0, RXY_CG, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, ofs); + tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); } =20 - ofs =3D offsetof(CPUArchState, tlb_table[mem_index][0].addend); - tcg_out_mem(s, 0, RXY_LG, TCG_REG_R2, TCG_REG_R2, TCG_AREG0, ofs); + tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); =20 if (TARGET_LONG_BITS =3D=3D 32) { tgen_ext32u(s, TCG_REG_R3, addr_reg); --=20 2.17.2