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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id p2sm45518687pfp.125.2019.01.28.07.59.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 07:59:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AGAWWFtB255WL3QD01Pm/ADB1O2A0MpRDbzf5uqk7D0=; b=Znk9xUOkNSDt5PqCRG1bXq2BZ5vUMPjzxYdjhNrsfsyo5pT7kXcf8+iuGb+qmS+sQY mkGQobm8gXV85HSNh0Pdr4IG6oEvuPy7oz1rQfUQhsHC9JC79GlreEI+iMTikbQ5thq+ I5BWArl8z9IE5JJUPQWedIdMMV1neCKWYSgbg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AGAWWFtB255WL3QD01Pm/ADB1O2A0MpRDbzf5uqk7D0=; b=c2NuwlPcdn3SHpKG/zczhXZwroUYKgvajj+Txcr4hsodx/owbtnDU/SoH8aJMOtTjy ze46Fl7tmogM8WqHUzs6onMvBHSimN+B1JPWph1rPx0rrZHJMgyZQbgbe0qgLulPWKIa 6H0lNzK6vwpDfIumPwNf5M9xqBJG2TCWCLxqByJlKPFbwxaLJyzngvQDEREuhW40/Fh+ IscsRILuutcl3bQbBMWF7sUqzFzntLURJHbpI13Au/IjrZ9kMc1BF3S486RHqSXqkIGl NrR0Nc/a3XKRKdFsZSSwx6QBRHewZkrDZpHZtaWXjuSinh/N5nG4Ya6uaurM+zPZyayb 6scA== X-Gm-Message-State: AJcUukcjUZtsEzejwPLEV8pwixUQZYz35JtVP5YGuG7YImFkRu3g273k 45KAv7UVaMx53izIsFpowWHCPuXS+uU= X-Google-Smtp-Source: ALg8bN4Dgu4ax98Lig4LgGqQJcZy5aNONcPi8ZrcDBPRaHawwTN+QQau8lqIOamrvMajmr75yHApOA== X-Received: by 2002:a17:902:b112:: with SMTP id q18mr22373102plr.255.1548691166105; Mon, 28 Jan 2019 07:59:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 07:58:55 -0800 Message-Id: <20190128155907.20607-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128155907.20607-1-richard.henderson@linaro.org> References: <20190128155907.20607-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PULL 11/23] cputlb: do not evict empty entries to the vtlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: "Emilio G. Cota" Currently we evict an entry to the victim TLB when it doesn't match the current address. But it could be that there's no match because the current entry is empty (i.e. all -1's, for instance via tlb_flush). Do not evict the entry to the vtlb in that case. This change will help us keep track of the TLB's use rate, which we'll use to implement a policy for dynamic TLB sizing. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20190116170114.26802-2-cota@braap.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index af6bd8ccf9..10f1150c62 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -224,6 +224,15 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *t= lb_entry, tlb_hit_page(tlb_entry->addr_code, page); } =20 +/** + * tlb_entry_is_empty - return true if the entry is not in use + * @te: pointer to CPUTLBEntry + */ +static inline bool tlb_entry_is_empty(const CPUTLBEntry *te) +{ + return te->addr_read =3D=3D -1 && te->addr_write =3D=3D -1 && te->addr= _code =3D=3D -1; +} + /* Called with tlb_c.lock held */ static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) @@ -591,7 +600,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * Only evict the old entry to the victim tlb if it's for a * different page; otherwise just overwrite the stale data. */ - if (!tlb_hit_page_anyprot(te, vaddr_page)) { + if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) { unsigned vidx =3D env->tlb_d[mmu_idx].vindex++ % CPU_VTLB_SIZE; CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; =20 --=20 2.17.2