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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id p2sm45518687pfp.125.2019.01.28.07.59.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 07:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1RVpvwteSuePPKo6wNsZRQ/0lJBH3U2L6QXC6WM1wUc=; b=b8ph8MkvD61zEpPq732b6uuUxIbtM9zeg7aZidBt3qAvXlKBhfK3FgJlQDof5jYGAP PoGOpA9msWA9jUEMFfOW1AWqXY+hVT0aY4WV44+9SjEyYRQqjyOeCMwlZZkCTBVQQHUy PK/gBtF+2R4A7/TOCQ6S8USwNVBXEOvCHED9Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1RVpvwteSuePPKo6wNsZRQ/0lJBH3U2L6QXC6WM1wUc=; b=TrrbYDqVMYPJ3grtp+5TWtEhb3qC11x1QMjnSN+j6STw+jNgaBymwRMZE7Z1qtKtjT U0JLElVPEnQZEtY+WjVlK12yNA6rMHKW0i+IJUQZXwGs0SiCD6fx9ibqlMOxulv9JiJy rSsr7Q8oNR911DsMkoj2vqDc/oBga9HEhUzBNax9YHa11QvPXI7nAyBaboZvsa2n55SC YqqIVVQRxlQt0pcFVno+2+ad3gSLpECmFZ3t/Mj5knWKTMs4OzUN+fTp6icWfq7KqAXk Q/2yoD/cl72Im4N4uomrxkCJ/fY6SKr3LyyMfoLiA87XZSOG2vJmq0yEjHr69xmlsmnz r6Qw== X-Gm-Message-State: AJcUukclFRgpe9hjxNLZybkiL10zcRTd/0FzrGyRHKpD/LKx1N6n07iC BmdeAYAkvxRwH01uXFWkKTcKflXh7z4= X-Google-Smtp-Source: ALg8bN6y/iRtm0BMAZBr1c6X2PeYnJNbLaMxLKX/chorjGO+0PaNSD2rUkNxEOJo71c+MSggKKcUjw== X-Received: by 2002:a17:902:690c:: with SMTP id j12mr22120166plk.206.1548691164649; Mon, 28 Jan 2019 07:59:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 07:58:54 -0800 Message-Id: <20190128155907.20607-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128155907.20607-1-richard.henderson@linaro.org> References: <20190128155907.20607-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PULL 10/23] tcg/aarch64: Implement vector minmax arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index a1884543d0..2d93cf404e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -136,7 +136,7 @@ typedef enum { #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 1 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index b2b011f130..ee0d5819af 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -528,8 +528,12 @@ typedef enum { I3616_CMHI =3D 0x2e203400, I3616_CMHS =3D 0x2e203c00, I3616_CMEQ =3D 0x2e208c00, + I3616_SMAX =3D 0x0e206400, + I3616_SMIN =3D 0x0e206c00, I3616_SQADD =3D 0x0e200c00, I3616_SQSUB =3D 0x0e202c00, + I3616_UMAX =3D 0x2e206400, + I3616_UMIN =3D 0x2e206c00, I3616_UQADD =3D 0x2e200c00, I3616_UQSUB =3D 0x2e202c00, =20 @@ -2153,6 +2157,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_ussub_vec: tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); break; + case INDEX_op_smax_vec: + tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); + break; + case INDEX_op_smin_vec: + tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2); + break; + case INDEX_op_umax_vec: + tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2); + break; + case INDEX_op_umin_vec: + tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2); + break; case INDEX_op_not_vec: tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; @@ -2227,6 +2243,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return 1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2410,6 +2430,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_sssub_vec: case INDEX_op_usadd_vec: case INDEX_op_ussub_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: --=20 2.17.2