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[50.233.235.3]) by smtp.gmail.com with ESMTPSA id p2sm45518687pfp.125.2019.01.28.07.59.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 07:59:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bjBWCHW6CsJ6peflKASsBY6j3Bp2s4dyGDxZEiyy4vc=; b=ViPpwfi/ASvNUaxPhC+rJKQjqg0Rkfr9Dh8dAaLxj1csG4RoeG1xgQWLhyQ2/l4hEV xrLrnKM4vwyijmleLBog847X555NxbE0PJDa0JsxllygV0Zkg2CE01/zddmVQPnbJBkp em6eNBF28efl0UZtmxDGci/cxKR4e0r9oXNDw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bjBWCHW6CsJ6peflKASsBY6j3Bp2s4dyGDxZEiyy4vc=; b=N0dL3+qzkBZdGU9dlb9E1OGEzUtw3TiH8KwEfBNc+QEmLTUNUWV1QlZFd/Ik1FKV3n 7KkVnMUTgZO4qnq13GJMJ7VCOEjFUkj6ml251R8lKEJTaVFIzmXkqPOjcRSavoxzs+Wm rUecrZuaz/MQbD48JJBKH0McEeIyt+N+zNpW1HVfRjEMMx3hdiRsoMoFAMG/ceJrYjmG KV9lHmF+Zq2KoX0OweBTXuz1TYkl2Jt4mMPIGbM3/0pLzgsPyrdKRpY89oESotMajhXl XOYrlphLvhvGAko9u2czkYjY+XF6SGSUFSvvum/saJ+PKYjvrKK6lXWQBqqvh4FrQx1a YuNg== X-Gm-Message-State: AJcUukdwED8OCeyunQH1M6T2CHfGkZa9PmnwWUGNd+60C7cy1IOZk1Bx 21bBTH1uyrk83f9o2bt34bIsIvlFRTs= X-Google-Smtp-Source: ALg8bN7R436BnutUDm9Pcc/R7UUFcjN81n8vBrOzHZ3W4Kdvy45wNRf4jS2UWlD8yxGVKRVMzyntJg== X-Received: by 2002:a63:68c4:: with SMTP id d187mr20146108pgc.11.1548691163307; Mon, 28 Jan 2019 07:59:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 28 Jan 2019 07:58:53 -0800 Message-Id: <20190128155907.20607-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190128155907.20607-1-richard.henderson@linaro.org> References: <20190128155907.20607-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52c Subject: [Qemu-devel] [PULL 09/23] tcg/aarch64: Implement vector saturating arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 545a6eec75..a1884543d0 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -135,7 +135,7 @@ typedef enum { #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_cmp_vec 1 #define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 0562e0aa40..b2b011f130 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -528,6 +528,10 @@ typedef enum { I3616_CMHI =3D 0x2e203400, I3616_CMHS =3D 0x2e203c00, I3616_CMEQ =3D 0x2e208c00, + I3616_SQADD =3D 0x0e200c00, + I3616_SQSUB =3D 0x0e202c00, + I3616_UQADD =3D 0x2e200c00, + I3616_UQSUB =3D 0x2e202c00, =20 /* AdvSIMD two-reg misc. */ I3617_CMGT0 =3D 0x0e208800, @@ -2137,6 +2141,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_orc_vec: tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); break; + case INDEX_op_ssadd_vec: + tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_sssub_vec: + tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + break; + case INDEX_op_usadd_vec: + tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_ussub_vec: + tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + break; case INDEX_op_not_vec: tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; @@ -2207,6 +2223,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,= unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2386,6 +2406,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_xor_vec: case INDEX_op_andc_vec: case INDEX_op_orc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: --=20 2.17.2