From nobody Fri Nov 7 17:10:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548454426130877.6960235469652; Fri, 25 Jan 2019 14:13:46 -0800 (PST) Received: from localhost ([127.0.0.1]:51406 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gn9jM-0001jR-8d for importer@patchew.org; Fri, 25 Jan 2019 17:13:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gn9co-0005Fd-0I for qemu-devel@nongnu.org; Fri, 25 Jan 2019 17:06:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gn9cm-0006aq-45 for qemu-devel@nongnu.org; Fri, 25 Jan 2019 17:06:57 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47568) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gn9ck-0006Yr-6X for qemu-devel@nongnu.org; Fri, 25 Jan 2019 17:06:55 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6BFBF3993; Fri, 25 Jan 2019 22:06:53 +0000 (UTC) Received: from probe.bos.redhat.com (dhcp-17-168.bos.redhat.com [10.18.17.168]) by smtp.corp.redhat.com (Postfix) with ESMTP id D9C2B61520; Fri, 25 Jan 2019 22:06:52 +0000 (UTC) From: John Snow To: qemu-devel@nongnu.org Date: Fri, 25 Jan 2019 17:06:43 -0500 Message-Id: <20190125220648.28164-4-jsnow@redhat.com> In-Reply-To: <20190125220648.28164-1-jsnow@redhat.com> References: <20190125220648.28164-1-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 25 Jan 2019 22:06:53 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 3/8] cmd646: Move PCI IDE specific functions to ide/pci.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, jsnow@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: BALATON Zoltan The io mem ops callbacks are not specific to CMD646 but really follow the PCI IDE spec so move these from cmd646.c to pci.c to allow other PCI IDE implementations to use them. Signed-off-by: BALATON Zoltan Tested-by: Mark Cave-Ayland Reviewed-by: John Snow Message-id: a2b1b2b74afdc78330b8b75605687f683a249635.1547166960.git.balaton= @eik.bme.hu Signed-off-by: John Snow --- hw/ide/cmd646.c | 71 ++------------------------------------------ hw/ide/pci.c | 65 ++++++++++++++++++++++++++++++++++++++++ include/hw/ide/pci.h | 2 ++ 3 files changed, 69 insertions(+), 69 deletions(-) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index c24f71e219..95f0df9742 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -50,81 +50,14 @@ =20 static void cmd646_update_irq(PCIDevice *pd); =20 -static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr, - unsigned size) -{ - IDEBus *bus =3D opaque; - - if (addr !=3D 2 || size !=3D 1) { - return ((uint64_t)1 << (size * 8)) - 1; - } - return ide_status_read(bus, addr + 2); -} - -static void cmd646_cmd_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - IDEBus *bus =3D opaque; - - if (addr !=3D 2 || size !=3D 1) { - return; - } - ide_cmd_write(bus, addr + 2, data); -} - -static const MemoryRegionOps cmd646_cmd_ops =3D { - .read =3D cmd646_cmd_read, - .write =3D cmd646_cmd_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static uint64_t cmd646_data_read(void *opaque, hwaddr addr, - unsigned size) -{ - IDEBus *bus =3D opaque; - - if (size =3D=3D 1) { - return ide_ioport_read(bus, addr); - } else if (addr =3D=3D 0) { - if (size =3D=3D 2) { - return ide_data_readw(bus, addr); - } else { - return ide_data_readl(bus, addr); - } - } - return ((uint64_t)1 << (size * 8)) - 1; -} - -static void cmd646_data_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - IDEBus *bus =3D opaque; - - if (size =3D=3D 1) { - ide_ioport_write(bus, addr, data); - } else if (addr =3D=3D 0) { - if (size =3D=3D 2) { - ide_data_writew(bus, addr, data); - } else { - ide_data_writel(bus, addr, data); - } - } -} - -static const MemoryRegionOps cmd646_data_ops =3D { - .read =3D cmd646_data_read, - .write =3D cmd646_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static void setup_cmd646_bar(PCIIDEState *d, int bus_num) { IDEBus *bus =3D &d->bus[bus_num]; CMD646BAR *bar =3D &d->cmd646_bar[bus_num]; =20 - memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bus, + memory_region_init_io(&bar->cmd, OBJECT(d), &pci_ide_cmd_le_ops, bus, "cmd646-cmd", 4); - memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bus, + memory_region_init_io(&bar->data, OBJECT(d), &pci_ide_data_le_ops, bus, "cmd646-data", 8); } =20 diff --git a/hw/ide/pci.c b/hw/ide/pci.c index b75154f99f..942613a9a9 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -36,6 +36,71 @@ (IDE_RETRY_DMA | IDE_RETRY_PIO | \ IDE_RETRY_READ | IDE_RETRY_FLUSH) =20 +static uint64_t pci_ide_cmd_read(void *opaque, hwaddr addr, unsigned size) +{ + IDEBus *bus =3D opaque; + + if (addr !=3D 2 || size !=3D 1) { + return ((uint64_t)1 << (size * 8)) - 1; + } + return ide_status_read(bus, addr + 2); +} + +static void pci_ide_cmd_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + IDEBus *bus =3D opaque; + + if (addr !=3D 2 || size !=3D 1) { + return; + } + ide_cmd_write(bus, addr + 2, data); +} + +const MemoryRegionOps pci_ide_cmd_le_ops =3D { + .read =3D pci_ide_cmd_read, + .write =3D pci_ide_cmd_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t pci_ide_data_read(void *opaque, hwaddr addr, unsigned size) +{ + IDEBus *bus =3D opaque; + + if (size =3D=3D 1) { + return ide_ioport_read(bus, addr); + } else if (addr =3D=3D 0) { + if (size =3D=3D 2) { + return ide_data_readw(bus, addr); + } else { + return ide_data_readl(bus, addr); + } + } + return ((uint64_t)1 << (size * 8)) - 1; +} + +static void pci_ide_data_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + IDEBus *bus =3D opaque; + + if (size =3D=3D 1) { + ide_ioport_write(bus, addr, data); + } else if (addr =3D=3D 0) { + if (size =3D=3D 2) { + ide_data_writew(bus, addr, data); + } else { + ide_data_writel(bus, addr, data); + } + } +} + +const MemoryRegionOps pci_ide_data_le_ops =3D { + .read =3D pci_ide_data_read, + .write =3D pci_ide_data_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static void bmdma_start_dma(IDEDMA *dma, IDEState *s, BlockCompletionFunc *dma_cb) { diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 013d7937d2..3110633e4c 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -71,4 +71,6 @@ extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table); =20 extern const VMStateDescription vmstate_ide_pci; +extern const MemoryRegionOps pci_ide_cmd_le_ops; +extern const MemoryRegionOps pci_ide_data_le_ops; #endif --=20 2.17.2