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Wed, 23 Jan 2019 21:23:28 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 5/5] tests/microbit-test: Add tests for nRF51 NVMC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Stefan Hajnoczi , qemu-block@nongnu.org, Peter Crosthwaite , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , jim@groklearning.com, Max Reitz , qemu-arm@nongnu.org, Joel Stanley , Kevin Wolf , Paolo Bonzini , jusual@mail.ru, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Steffen G=C3=B6rtz Signed-off-by: Steffen G=C3=B6rtz Signed-off-by: Stefan Hajnoczi --- tests/microbit-test.c | 97 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/tests/microbit-test.c b/tests/microbit-test.c index 0c125535f6..d3edd38643 100644 --- a/tests/microbit-test.c +++ b/tests/microbit-test.c @@ -20,8 +20,104 @@ =20 #include "hw/arm/nrf51.h" #include "hw/gpio/nrf51_gpio.h" +#include "hw/nvram/nrf51_nvm.h" #include "hw/timer/nrf51_timer.h" =20 +#define FLASH_SIZE (256 * NRF51_PAGE_SIZE) + +static void fill_and_erase(hwaddr base, hwaddr size, uint32_t address_reg) +{ + hwaddr i; + + /* Erase Page */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + address_reg, base); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + /* Check memory */ + for (i =3D 0; i < size / 4; i++) { + g_assert_cmpuint(readl(base + i * 4), =3D=3D, 0xFFFFFFFF); + } + + /* Fill memory */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < size / 4; i++) { + writel(base + i * 4, i); + g_assert_cmpuint(readl(base + i * 4), =3D=3D, i); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); +} + +static void test_nrf51_nvmc(void) +{ + uint32_t value; + hwaddr i; + + /* Test always ready */ + value =3D readl(NRF51_NVMC_BASE + NRF51_NVMC_READY); + g_assert_cmpuint(value & 0x01, =3D=3D, 0x01); + + /* Test write-read config register */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x03); + g_assert_cmpuint(readl(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), =3D=3D, 0= x03); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + g_assert_cmpuint(readl(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG), =3D=3D, 0= x00); + + /* Test PCR0 */ + fill_and_erase(NRF51_FLASH_BASE, NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0= ); + fill_and_erase(NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR0); + + /* Test PCR1 */ + fill_and_erase(NRF51_FLASH_BASE, NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1= ); + fill_and_erase(NRF51_FLASH_BASE + NRF51_PAGE_SIZE, + NRF51_PAGE_SIZE, NRF51_NVMC_ERASEPCR1); + + /* Erase all */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < FLASH_SIZE / 4; i++) { + writel(NRF51_FLASH_BASE + i * 4, i); + g_assert_cmpuint(readl(NRF51_FLASH_BASE + i * 4), =3D=3D, i); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEALL, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < FLASH_SIZE / 4; i++) { + g_assert_cmpuint(readl(NRF51_FLASH_BASE + i * 4), =3D=3D, 0xFFFFFF= FF); + } + + /* Erase UICR */ + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + g_assert_cmpuint(readl(NRF51_UICR_BASE + i * 4), =3D=3D, 0xFFFFFFF= F); + } + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x01); + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + writel(NRF51_UICR_BASE + i * 4, i); + g_assert_cmpuint(readl(NRF51_UICR_BASE + i * 4), =3D=3D, i); + } + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x02); + writel(NRF51_NVMC_BASE + NRF51_NVMC_ERASEUICR, 0x01); + writel(NRF51_NVMC_BASE + NRF51_NVMC_CONFIG, 0x00); + + for (i =3D 0; i < NRF51_UICR_SIZE / 4; i++) { + g_assert_cmpuint(readl(NRF51_UICR_BASE + i * 4), =3D=3D, 0xFFFFFFF= F); + } +} + static void test_nrf51_gpio(void) { size_t i; @@ -246,6 +342,7 @@ int main(int argc, char **argv) global_qtest =3D qtest_initf("-machine microbit"); =20 qtest_add_func("/microbit/nrf51/gpio", test_nrf51_gpio); + qtest_add_func("/microbit/nrf51/nvmc", test_nrf51_nvmc); qtest_add_func("/microbit/nrf51/timer", test_nrf51_timer); =20 ret =3D g_test_run(); --=20 2.20.1