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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v3 08/11] include/fpu/softfloat: Fix compilation with Clang on s390x X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Thomas Huth Clang v7.0.1 does not like the __int128 variable type for inline assembly on s390x: In file included from fpu/softfloat.c:97: include/fpu/softfloat-macros.h:647:9: error: inline asm error: This value type register class is not natively supported! asm("dlgr %0, %1" : "+r"(n) : "r"(d)); ^ Disable this code part there now when compiling with Clang, so that the generic code gets used instead. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Acked-by: Cornelia Huck Signed-off-by: Alex Benn=C3=A9e --- include/fpu/softfloat-macros.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index b1d772e6d4..bd5b6418e3 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -641,7 +641,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t= n1, uint64_t q; asm("divq %4" : "=3Da"(q), "=3Dd"(*r) : "0"(n0), "1"(n1), "rm"(d)); return q; -#elif defined(__s390x__) +#elif defined(__s390x__) && !defined(__clang__) /* Need to use a TImode type to get an even register pair for DLGR. */ unsigned __int128 n =3D (unsigned __int128)n1 << 64 | n0; asm("dlgr %0, %1" : "+r"(n) : "r"(d)); --=20 2.17.1