From nobody Fri Nov 7 15:31:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548253006285918.8737939010716; Wed, 23 Jan 2019 06:16:46 -0800 (PST) Received: from localhost ([127.0.0.1]:35603 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmJKf-0001MG-8x for importer@patchew.org; Wed, 23 Jan 2019 09:16:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gmJHb-0007gh-0o for qemu-devel@nongnu.org; Wed, 23 Jan 2019 09:13:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gmJHZ-0006i1-Kr for qemu-devel@nongnu.org; Wed, 23 Jan 2019 09:13:34 -0500 Received: from mga12.intel.com ([192.55.52.136]:53088) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gmJHU-0006aZ-He for qemu-devel@nongnu.org; Wed, 23 Jan 2019 09:13:30 -0500 Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jan 2019 06:13:20 -0800 Received: from local-michael-cet-test.sh.intel.com ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 23 Jan 2019 06:13:18 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,511,1539673200"; d="scan'208";a="110416510" From: Yang Weijiang To: pbonzini@redhat.com, cdupontd@redhat.com, rkrcmar@redhat.com, qemu-devel@nongnu.org, mst@redhat.com, yu-cheng.yu@intel.com, yi.z.zhang@intel.com, hjl.tools@gmail.com Date: Wed, 23 Jan 2019 05:06:46 +0800 Message-Id: <20190122210648.26320-3-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190122210648.26320-1-weijiang.yang@intel.com> References: <20190122210648.26320-1-weijiang.yang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 Subject: [Qemu-devel] [PATCH v2 2/4] Add CET SHSTK and IBT CPUID feature-word definitions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: weijiang.yang@intel.com, Zhang Yi Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" XSS[bit 11] and XSS[bit 12] correspond to CET user mode area and supervisor mode area respectively. Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f81d35e1f9..f6c7bdf6fe 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1018,7 +1018,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, NULL, "avx512vbmi2", NULL, + NULL /* ospke */, NULL, "avx512vbmi2", "shstk", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -1041,7 +1041,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "pconfig", NULL, - NULL, NULL, NULL, NULL, + "ibt", NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, NULL, "arch-capabilities", NULL, "ssbd", }, @@ -1162,6 +1162,25 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { } }, }, + /* Below are CET supervisor xsave features */ + [FEAT_XSAVE_SV_LO] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_ECX, + }, + }, + [FEAT_XSAVE_SV_HI] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_EDX + }, + } }; =20 typedef struct X86RegisterInfo32 { @@ -1233,6 +1252,14 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .offset =3D offsetof(X86XSaveArea, pkru_state), .size =3D sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0 /*supervisor mode component, offset =3D 0 */, + .size =3D sizeof(XSaveCETU) }, + [XSTATE_CET_S_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0 /*supervisor mode component, offset =3D 0 */, + .size =3D sizeof(XSaveCETS) }, }; =20 static uint32_t xsave_area_size(uint64_t mask) @@ -1243,6 +1270,9 @@ static uint32_t xsave_area_size(uint64_t mask) for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; if ((mask >> i) & 1) { + if (i >=3D 2 && !esa->offset) { + continue; + } ret =3D MAX(ret, esa->offset + esa->size); } } @@ -4657,6 +4687,9 @@ static void x86_cpu_reset(CPUState *s) } for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + if (!esa->offset) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |=3D 1ull << i; } --=20 2.17.1