From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151767792451.34843181702047; Tue, 22 Jan 2019 02:09:27 -0800 (PST) Received: from localhost ([127.0.0.1]:42046 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glszm-00063F-NV for importer@patchew.org; Tue, 22 Jan 2019 05:09:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVs-00068S-JE for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNS-0004bg-Cg for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:52 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60770) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNQ-0004Zt-Bz; Tue, 22 Jan 2019 04:29:49 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1glsNL-0006AW-84; Tue, 22 Jan 2019 10:29:43 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3095049-3; Tue, 22 Jan 2019 09:29:42 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:35 +0100 Message-Id: <20190122092909.5341-2-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 312bf298b3..c4a4d8115c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -52,6 +52,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + CPURISCVState *env; } DisasContext; =20 /* convert riscv funct3 to qemu memop for load/store */ @@ -1797,19 +1798,19 @@ static void decode_RV32_64G(CPURISCVState *env, Dis= asContext *ctx) } } =20 -static void decode_opc(CPURISCVState *env, DisasContext *ctx) +static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) !=3D 3) { - if (!riscv_has_ext(env, RVC)) { + if (!riscv_has_ext(ctx->env, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_RV32_64C(env, ctx); + decode_RV32_64C(ctx->env, ctx); } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_RV32_64G(env, ctx); + decode_RV32_64G(ctx->env, ctx); } } =20 @@ -1854,10 +1855,10 @@ static bool riscv_tr_breakpoint_check(DisasContextB= ase *dcbase, CPUState *cpu, static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPURISCVState *env =3D cpu->env_ptr; + ctx->env =3D cpu->env_ptr; =20 - ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); - decode_opc(env, ctx); + ctx->opcode =3D cpu_ldl_code(ctx->env, ctx->base.pc_next); + decode_opc(ctx); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151904728354.2585207308564; Tue, 22 Jan 2019 02:11:44 -0800 (PST) Received: from localhost ([127.0.0.1]:42112 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glt1r-00085c-I4 for importer@patchew.org; Tue, 22 Jan 2019 05:11:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59350) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVo-0006M9-Lf for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNU-0004j8-FD for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:54 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:54908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNQ-0004aJ-C7; Tue, 22 Jan 2019 04:29:50 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1glsNM-0001r9-5m; Tue, 22 Jan 2019 10:29:44 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098398-2; Tue, 22 Jan 2019 09:29:43 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:36 +0100 Message-Id: <20190122092909.5341-3-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson Acked-by: Alistair Francis Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/Makefile.objs | 10 +++++++ target/riscv/insn32.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++ target/riscv/translate.c | 31 ++++++++++++---------- 4 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 4072abe3e4..bf0a268033 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1,11 @@ obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o g= dbstub.o pmp.o + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py + +target/riscv/decode_insn32.inc.c: \ + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode new file mode 100644 index 0000000000..44d4e922b6 --- /dev/null +++ b/target/riscv/insn32.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# Fields: +%rd 7:5 + +# immediates: +%imm_u 12:s20 !function=3Dex_shift_12 + +# Formats 32: +@u .................... ..... ....... imm=3D%imm_u = %rd + +# *** RV32I Base Instruction Set *** +lui .................... ..... 0110111 @u +auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c new file mode 100644 index 0000000000..9885a8d275 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -0,0 +1,35 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_lui(DisasContext *ctx, arg_lui *a) +{ + if (a->rd !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a) +{ + if (a->rd !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c4a4d8115c..99829a600d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1677,6 +1677,19 @@ static void decode_RV32_64C(CPURISCVState *env, Disa= sContext *ctx) } } =20 +#define EX_SH(amount) \ + static int ex_shift_##amount(int imm) \ + { \ + return imm << amount; \ + } +EX_SH(12) + +bool decode_insn32(DisasContext *ctx, uint32_t insn); +/* Include the auto-generated decoder for 32 bit insn */ +#include "decode_insn32.inc.c" +/* Include insn module translation function */ +#include "insn_trans/trans_rvi.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1; @@ -1697,19 +1710,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_LUI: - if (rd =3D=3D 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12= ); - break; - case OPC_RISC_AUIPC: - if (rd =3D=3D 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 1= 2) + - ctx->base.pc_next); - break; case OPC_RISC_JAL: imm =3D GET_JAL_IMM(ctx->opcode); gen_jal(env, ctx, rd, imm); @@ -1810,7 +1810,10 @@ static void decode_opc(DisasContext *ctx) } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_RV32_64G(ctx->env, ctx); + if (!decode_insn32(ctx, ctx->opcode)) { + /* fallback to old decoder */ + decode_RV32_64G(ctx->env, ctx); + } } } =20 --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154815206739435.363303495813625; Tue, 22 Jan 2019 02:14:27 -0800 (PST) Received: from localhost ([127.0.0.1]:42144 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glt4Y-0001xo-Cp for importer@patchew.org; Tue, 22 Jan 2019 05:14:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVo-0006NI-Fb for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNU-0004jN-G7 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:54 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60658) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNQ-0004at-DG; Tue, 22 Jan 2019 04:29:50 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1glsNO-0003G2-O3; Tue, 22 Jan 2019 10:29:46 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100911-5; Tue, 22 Jan 2019 09:29:45 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:37 +0100 Message-Id: <20190122092909.5341-4-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 19 ++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 49 +++++++++++++++++++++++++ target/riscv/translate.c | 12 +----- 3 files changed, 69 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 44d4e922b6..81f56c16b4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,14 +17,33 @@ # this program. If not, see . =20 # Fields: +%rs2 20:5 +%rs1 15:5 %rd 7:5 =20 # immediates: +%imm_i 20:s12 +%imm_b 31:s1 7:1 25:6 8:4 !function=3Dex_shift_1 +%imm_j 31:s1 12:8 20:1 21:10 !function=3Dex_shift_1 %imm_u 12:s20 !function=3Dex_shift_12 =20 +# Argument sets: +&b imm rs2 rs1 + # Formats 32: +@i ............ ..... ... ..... ....... imm=3D%imm_i = %rs1 %rd +@b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd +@j .................... ..... ....... imm=3D%imm_j = %rd =20 # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u +jal .................... ..... 1101111 @j +jalr ............ ..... 000 ..... 1100111 @i +beq ....... ..... ..... 000 ..... 1100011 @b +bne ....... ..... ..... 001 ..... 1100011 @b +blt ....... ..... ..... 100 ..... 1100011 @b +bge ....... ..... ..... 101 ..... 1100011 @b +bltu ....... ..... ..... 110 ..... 1100011 @b +bgeu ....... ..... ..... 111 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 9885a8d275..0347461ee6 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -33,3 +33,52 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a) } return true; } + +static bool trans_jal(DisasContext *ctx, arg_jal *a) +{ + gen_jal(ctx->env, ctx, a->rd, a->imm); + return true; +} + +static bool trans_jalr(DisasContext *ctx, arg_jalr *a) +{ + gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_beq(DisasContext *ctx, arg_beq *a) +{ + gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bne(DisasContext *ctx, arg_bne *a) +{ + gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_blt(DisasContext *ctx, arg_blt *a) +{ + gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bge(DisasContext *ctx, arg_bge *a) +{ + gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bltu(DisasContext *ctx, arg_bltu *a) +{ + gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) +{ + + gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 99829a600d..b81297f23e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1682,6 +1682,7 @@ static void decode_RV32_64C(CPURISCVState *env, Disas= Context *ctx) { \ return imm << amount; \ } +EX_SH(1) EX_SH(12) =20 bool decode_insn32(DisasContext *ctx, uint32_t insn); @@ -1710,17 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_JAL: - imm =3D GET_JAL_IMM(ctx->opcode); - gen_jal(env, ctx, rd, imm); - break; - case OPC_RISC_JALR: - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_BRANCH: - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, - GET_B_IMM(ctx->opcode)); - break; case OPC_RISC_LOAD: gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); break; --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 22 Jan 2019 04:29:54 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41758) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNS-0004bC-B2; Tue, 22 Jan 2019 04:29:52 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1glsNP-000161-SE; Tue, 22 Jan 2019 10:29:47 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069616-4; Tue, 22 Jan 2019 09:29:46 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:38 +0100 Message-Id: <20190122092909.5341-5-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 10 ++++++ target/riscv/insn_trans/trans_rvi.inc.c | 48 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 81f56c16b4..076de873c4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -23,6 +23,7 @@ =20 # immediates: %imm_i 20:s12 +%imm_s 25:s7 7:5 %imm_b 31:s1 7:1 25:6 8:4 !function=3Dex_shift_1 %imm_j 31:s1 12:8 20:1 21:10 !function=3Dex_shift_1 %imm_u 12:s20 !function=3Dex_shift_12 @@ -33,6 +34,7 @@ # Formats 32: @i ............ ..... ... ..... ....... imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 +@s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd @j .................... ..... ....... imm=3D%imm_j = %rd =20 @@ -47,3 +49,11 @@ blt ....... ..... ..... 100 ..... 1100011 @b bge ....... ..... ..... 101 ..... 1100011 @b bltu ....... ..... ..... 110 ..... 1100011 @b bgeu ....... ..... ..... 111 ..... 1100011 @b +lb ............ ..... 000 ..... 0000011 @i +lh ............ ..... 001 ..... 0000011 @i +lw ............ ..... 010 ..... 0000011 @i +lbu ............ ..... 100 ..... 0000011 @i +lhu ............ ..... 101 ..... 0000011 @i +sb ....... ..... ..... 000 ..... 0100011 @s +sh ....... ..... ..... 001 ..... 0100011 @s +sw ....... ..... ..... 010 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 0347461ee6..f3b88ebb69 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -82,3 +82,51 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); return true; } + +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lh(DisasContext *ctx, arg_lh *a) +{ + gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lw(DisasContext *ctx, arg_lw *a) +{ + gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lbu(DisasContext *ctx, arg_lbu *a) +{ + gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_lhu(DisasContext *ctx, arg_lhu *a) +{ + gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sh(DisasContext *ctx, arg_sh *a) +{ + gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); + return true; +} + +static bool trans_sw(DisasContext *ctx, arg_sw *a) +{ + gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); + return true; +} --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151718954142.1523316461214; Tue, 22 Jan 2019 02:08:38 -0800 (PST) Received: from localhost ([127.0.0.1]:42044 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsyz-0005Mw-T7 for importer@patchew.org; Tue, 22 Jan 2019 05:08:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVj-0006NI-7I for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNX-0004ta-Kk for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:56 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:53484) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNU-0004bY-9H; Tue, 22 Jan 2019 04:29:54 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1glsNR-0004ii-K2; Tue, 22 Jan 2019 10:29:49 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069617-4; Tue, 22 Jan 2019 09:29:48 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:39 +0100 Message-Id: <20190122092909.5341-6-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 05/35] target/riscv: Convert RV64I load/store insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/Makefile.objs | 8 +++++--- target/riscv/insn32-64.decode | 25 +++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++ target/riscv/translate.c | 7 ------- 4 files changed, 50 insertions(+), 10 deletions(-) create mode 100644 target/riscv/insn32-64.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index bf0a268033..05087a91bb 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -2,10 +2,12 @@ obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr= .o fpu_helper.o gdbstub.o =20 DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py =20 -target/riscv/decode_insn32.inc.c: \ - $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) +decode32-y =3D $(SRC_PATH)/target/riscv/insn32.decode +decode32-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn32-64.decode + +target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) =20 target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode new file mode 100644 index 0000000000..439d4e2c58 --- /dev/null +++ b/target/riscv/insn32-64.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the RV Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# This is concatenated with insn32.decode for risc64 targets. +# Most of the fields and formats are there. + +# *** RV64I Base Instruction Set (in addition to RV32I) *** +lwu ............ ..... 110 ..... 0000011 @i +ld ............ ..... 011 ..... 0000011 @i +sd ....... ..... ..... 011 ..... 0100011 @s diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index f3b88ebb69..39a20a70e8 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -130,3 +130,23 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); return true; } + +#ifdef TARGET_RISCV64 +static bool trans_lwu(DisasContext *ctx, arg_lwu *a) +{ + gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_ld(DisasContext *ctx, arg_ld *a) +{ + gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sd(DisasContext *ctx, arg_sd *a) +{ + gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b81297f23e..609207f785 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1711,13 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_LOAD: - gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_STORE: - gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2, - GET_STORE_IMM(ctx->opcode)); - break; case OPC_RISC_ARITH_IMM: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_IMM_W: --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151593688170.73101569399728; Tue, 22 Jan 2019 02:06:33 -0800 (PST) Received: from localhost ([127.0.0.1]:42003 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glswy-0003ki-Ha for importer@patchew.org; Tue, 22 Jan 2019 05:06:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVk-00068S-QI for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNW-0004rP-Ou for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:56 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:54946) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNW-0004gv-E2; Tue, 22 Jan 2019 04:29:54 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1glsNS-0001rh-5D; Tue, 22 Jan 2019 10:29:50 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3095050-3; Tue, 22 Jan 2019 09:29:49 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:40 +0100 Message-Id: <20190122092909.5341-7-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn32-64.decode | 13 ++ target/riscv/insn32.decode | 25 ++++ target/riscv/insn_trans/trans_rvi.inc.c | 168 ++++++++++++++++++++++++ target/riscv/translate.c | 9 -- 4 files changed, 206 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 439d4e2c58..9a35f2aa19 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -19,7 +19,20 @@ # This is concatenated with insn32.decode for risc64 targets. # Most of the fields and formats are there. =20 +%sh5 20:5 + +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5 = %rs1 %rd + # *** RV64I Base Instruction Set (in addition to RV32I) *** lwu ............ ..... 110 ..... 0000011 @i ld ............ ..... 011 ..... 0000011 @i sd ....... ..... ..... 011 ..... 0100011 @s +addiw ............ ..... 000 ..... 0011011 @i +slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 +srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 +sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 +addw 0000000 ..... ..... 000 ..... 0111011 @r +subw 0100000 ..... ..... 000 ..... 0111011 @r +sllw 0000000 ..... ..... 001 ..... 0111011 @r +srlw 0000000 ..... ..... 101 ..... 0111011 @r +sraw 0100000 ..... ..... 101 ..... 0111011 @r diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 076de873c4..1f5bf1f6f9 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -21,6 +21,8 @@ %rs1 15:5 %rd 7:5 =20 +%sh10 20:10 + # immediates: %imm_i 20:s12 %imm_s 25:s7 7:5 @@ -30,14 +32,18 @@ =20 # Argument sets: &b imm rs2 rs1 +&shift shamt rs1 rd =20 # Formats 32: +@r ....... ..... ..... ... ..... ....... %rs2 %r= s1 %rd @i ............ ..... ... ..... ....... imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd @j .................... ..... ....... imm=3D%imm_j = %rd =20 +@sh ...... ...... ..... ... ..... ....... &shift shamt=3D%sh10 = %rs1 %rd + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u @@ -57,3 +63,22 @@ lhu ............ ..... 101 ..... 0000011 @i sb ....... ..... ..... 000 ..... 0100011 @s sh ....... ..... ..... 001 ..... 0100011 @s sw ....... ..... ..... 010 ..... 0100011 @s +addi ............ ..... 000 ..... 0010011 @i +slti ............ ..... 010 ..... 0010011 @i +sltiu ............ ..... 011 ..... 0010011 @i +xori ............ ..... 100 ..... 0010011 @i +ori ............ ..... 110 ..... 0010011 @i +andi ............ ..... 111 ..... 0010011 @i +slli 00.... ...... ..... 001 ..... 0010011 @sh +srli 00.... ...... ..... 101 ..... 0010011 @sh +srai 01.... ...... ..... 101 ..... 0010011 @sh +add 0000000 ..... ..... 000 ..... 0110011 @r +sub 0100000 ..... ..... 000 ..... 0110011 @r +sll 0000000 ..... ..... 001 ..... 0110011 @r +slt 0000000 ..... ..... 010 ..... 0110011 @r +sltu 0000000 ..... ..... 011 ..... 0110011 @r +xor 0000000 ..... ..... 100 ..... 0110011 @r +srl 0000000 ..... ..... 101 ..... 0110011 @r +sra 0100000 ..... ..... 101 ..... 0110011 @r +or 0000000 ..... ..... 110 ..... 0110011 @r +and 0000000 ..... ..... 111 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 39a20a70e8..01f751650a 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -150,3 +150,171 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a) return true; } #endif + +static bool trans_addi(DisasContext *ctx, arg_addi *a) +{ + gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_slti(DisasContext *ctx, arg_slti *a) +{ + gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) +{ + gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_xori(DisasContext *ctx, arg_xori *a) +{ + gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_ori(DisasContext *ctx, arg_ori *a) +{ + gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_andi(DisasContext *ctx, arg_andi *a) +{ + gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm); + return true; +} +static bool trans_slli(DisasContext *ctx, arg_slli *a) +{ + gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srli(DisasContext *ctx, arg_srli *a) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srai(DisasContext *ctx, arg_srai *a) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0= x400); + return true; +} + +static bool trans_add(DisasContext *ctx, arg_add *a) +{ + gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sub(DisasContext *ctx, arg_sub *a) +{ + gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sll(DisasContext *ctx, arg_sll *a) +{ + gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_slt(DisasContext *ctx, arg_slt *a) +{ + gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sltu(DisasContext *ctx, arg_sltu *a) +{ + gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_xor(DisasContext *ctx, arg_xor *a) +{ + gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_srl(DisasContext *ctx, arg_srl *a) +{ + gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sra(DisasContext *ctx, arg_sra *a) +{ + gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_or(DisasContext *ctx, arg_or *a) +{ + gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_and(DisasContext *ctx, arg_and *a) +{ + gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2); + return true; +} + +#ifdef TARGET_RISCV64 +static bool trans_addiw(DisasContext *ctx, arg_addiw *a) +{ + gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_slliw(DisasContext *ctx, arg_slliw *a) +{ + gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_srliw(DisasContext *ctx, arg_srliw *a) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt); + return true; +} + +static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) +{ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1, + a->shamt | 0x400); + return true; +} + +static bool trans_addw(DisasContext *ctx, arg_addw *a) +{ + gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_subw(DisasContext *ctx, arg_subw *a) +{ + gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sllw(DisasContext *ctx, arg_sllw *a) +{ + gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_srlw(DisasContext *ctx, arg_srlw *a) +{ + gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_sraw(DisasContext *ctx, arg_sraw *a) +{ + gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 609207f785..c16eba8ec8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1711,15 +1711,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_ARITH_IMM: -#if defined(TARGET_RISCV64) - case OPC_RISC_ARITH_IMM_W: -#endif - if (rd =3D=3D 0) { - break; /* NOP */ - } - gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm); - break; case OPC_RISC_ARITH: #if defined(TARGET_RISCV64) case OPC_RISC_ARITH_W: --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151395996944.4965753865476; Tue, 22 Jan 2019 02:03:15 -0800 (PST) Received: from localhost ([127.0.0.1]:41949 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glstm-00019h-Py for importer@patchew.org; Tue, 22 Jan 2019 05:03:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59350) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVk-0006M9-Se for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNW-0004rI-LT for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:55 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41888) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNW-0004oA-DX; Tue, 22 Jan 2019 04:29:54 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1glsNU-0004Ib-Gf; Tue, 22 Jan 2019 10:29:52 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3095051-3; Tue, 22 Jan 2019 09:29:51 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:41 +0100 Message-Id: <20190122092909.5341-8-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- v4 -> v5: - fixed rebase error target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvi.inc.c | 19 +++++++++++++++++++ target/riscv/translate.c | 12 ------------ 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1f5bf1f6f9..804b721ca5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r +fence ---- pred:4 succ:4 ----- 000 ----- 0001111 +fence_i ---- ---- ---- ----- 001 ----- 0001111 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 01f751650a..b468a0ac0e 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) return true; } #endif + +static bool trans_fence(DisasContext *ctx, arg_fence *a) +{ + /* FENCE is a full memory barrier. */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) +{ + /* + * FENCE_I is a no-op in QEMU, + * however we need to end the translation block + */ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c16eba8ec8..9899f10be4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1750,18 +1750,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2, GET_RM(ctx->opcode)); break; - case OPC_RISC_FENCE: - if (ctx->opcode & 0x1000) { - /* FENCE_I is a no-op in QEMU, - * however we need to end the translation block */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - tcg_gen_exit_tb(NULL, 0); - ctx->base.is_jmp =3D DISAS_NORETURN; - } else { - /* FENCE is a full memory barrier. */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - } - break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, (ctx->opcode & 0xFFF00000) >> 20); --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151209308550.4755220846354; Tue, 22 Jan 2019 02:00:09 -0800 (PST) Received: from localhost ([127.0.0.1]:41884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsqm-0007Bz-7v for importer@patchew.org; Tue, 22 Jan 2019 05:00:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVj-0006XP-4E for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNZ-00050v-5q for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:58 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60686) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNX-0004rb-GX; Tue, 22 Jan 2019 04:29:55 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1glsNV-0003GV-OB; Tue, 22 Jan 2019 10:29:53 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069618-4; Tue, 22 Jan 2019 09:29:52 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:42 +0100 Message-Id: <20190122092909.5341-9-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 08/35] target/riscv: Convert RVXI csr insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvi.inc.c | 79 +++++++++++++++++++++++++ target/riscv/translate.c | 43 +------------- 3 files changed, 88 insertions(+), 42 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 804b721ca5..977b1b10a3 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -22,6 +22,7 @@ %rd 7:5 =20 %sh10 20:10 +%csr 20:12 =20 # immediates: %imm_i 20:s12 @@ -43,6 +44,7 @@ @j .................... ..... ....... imm=3D%imm_j = %rd =20 @sh ...... ...... ..... ... ..... ....... &shift shamt=3D%sh10 = %rs1 %rd +@csr ............ ..... ... ..... ....... %csr %r= s1 %rd =20 # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u @@ -84,3 +86,9 @@ or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r fence ---- pred:4 succ:4 ----- 000 ----- 0001111 fence_i ---- ---- ---- ----- 001 ----- 0001111 +csrrw ............ ..... 001 ..... 1110011 @csr +csrrs ............ ..... 010 ..... 1110011 @csr +csrrc ............ ..... 011 ..... 1110011 @csr +csrrwi ............ ..... 101 ..... 1110011 @csr +csrrsi ............ ..... 110 ..... 1110011 @csr +csrrci ............ ..... 111 ..... 1110011 @csr diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index b468a0ac0e..b0f35cef14 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -337,3 +337,82 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence= _i *a) ctx->base.is_jmp =3D DISAS_NORETURN; return true; } + +#define RISCV_OP_CSR_PRE do {\ + source1 =3D tcg_temp_new(); \ + csr_store =3D tcg_temp_new(); \ + dest =3D tcg_temp_new(); \ + rs1_pass =3D tcg_temp_new(); \ + gen_get_gpr(source1, a->rs1); \ + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \ + tcg_gen_movi_tl(rs1_pass, a->rs1); \ + tcg_gen_movi_tl(csr_store, a->csr); \ + gen_io_start();\ +} while (0) + +#define RISCV_OP_CSR_POST do {\ + gen_io_end(); \ + gen_set_gpr(a->rd, dest); \ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \ + tcg_gen_exit_tb(NULL, 0); \ + ctx->base.is_jmp =3D DISAS_NORETURN; \ + tcg_temp_free(source1); \ + tcg_temp_free(csr_store); \ + tcg_temp_free(dest); \ + tcg_temp_free(rs1_pass); \ +} while (0) + + +static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrw(dest, cpu_env, source1, csr_store); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} + +static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a) +{ + TCGv source1, csr_store, dest, rs1_pass; + RISCV_OP_CSR_PRE; + gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass); + RISCV_OP_CSR_POST; + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9899f10be4..a020305556 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1279,16 +1279,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_= t opc, int rd, static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, int rd, int rs1, int csr) { - TCGv source1, csr_store, dest, rs1_pass, imm_rs1; + TCGv source1, dest; source1 =3D tcg_temp_new(); - csr_store =3D tcg_temp_new(); dest =3D tcg_temp_new(); - rs1_pass =3D tcg_temp_new(); - imm_rs1 =3D tcg_temp_new(); gen_get_gpr(source1, rs1); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - tcg_gen_movi_tl(rs1_pass, rs1); - tcg_gen_movi_tl(csr_store, csr); /* copy into temp reg to feed to help= er */ =20 #ifndef CONFIG_USER_ONLY /* Extract funct7 value and check whether it matches SFENCE.VMA */ @@ -1359,45 +1354,9 @@ static void gen_system(CPURISCVState *env, DisasCont= ext *ctx, uint32_t opc, break; } break; - default: - tcg_gen_movi_tl(imm_rs1, rs1); - gen_io_start(); - switch (opc) { - case OPC_RISC_CSRRW: - gen_helper_csrrw(dest, cpu_env, source1, csr_store); - break; - case OPC_RISC_CSRRS: - gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass); - break; - case OPC_RISC_CSRRC: - gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass); - break; - case OPC_RISC_CSRRWI: - gen_helper_csrrw(dest, cpu_env, imm_rs1, csr_store); - break; - case OPC_RISC_CSRRSI: - gen_helper_csrrs(dest, cpu_env, imm_rs1, csr_store, rs1_pass); - break; - case OPC_RISC_CSRRCI: - gen_helper_csrrc(dest, cpu_env, imm_rs1, csr_store, rs1_pass); - break; - default: - gen_exception_illegal(ctx); - return; - } - gen_io_end(); - gen_set_gpr(rd, dest); - /* end tb since we may be changing priv modes, to get mmu_index ri= ght */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp =3D DISAS_NORETURN; - break; } tcg_temp_free(source1); - tcg_temp_free(csr_store); tcg_temp_free(dest); - tcg_temp_free(rs1_pass); - tcg_temp_free(imm_rs1); } =20 static void decode_RV32_64C0(DisasContext *ctx) --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151575370477.0822037256884; Tue, 22 Jan 2019 02:06:15 -0800 (PST) Received: from localhost ([127.0.0.1]:42001 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glswg-0003Xx-4d for importer@patchew.org; Tue, 22 Jan 2019 05:06:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVh-0006NI-1b for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNa-00054x-Ln for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:29:59 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60824) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNY-0004wy-Vg; Tue, 22 Jan 2019 04:29:57 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1glsNX-0006BO-6h; Tue, 22 Jan 2019 10:29:55 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069619-4; Tue, 22 Jan 2019 09:29:53 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:43 +0100 Message-Id: <20190122092909.5341-10-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 09/35] target/riscv: Convert RVXM insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn32-64.decode | 7 ++ target/riscv/insn32.decode | 10 +++ target/riscv/insn_trans/trans_rvm.inc.c | 100 ++++++++++++++++++++++++ target/riscv/translate.c | 10 +-- 4 files changed, 118 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 9a35f2aa19..008f100546 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r sllw 0000000 ..... ..... 001 ..... 0111011 @r srlw 0000000 ..... ..... 101 ..... 0111011 @r sraw 0100000 ..... ..... 101 ..... 0111011 @r + +# *** RV64M Standard Extension (in addition to RV32M) *** +mulw 0000001 ..... ..... 000 ..... 0111011 @r +divw 0000001 ..... ..... 100 ..... 0111011 @r +divuw 0000001 ..... ..... 101 ..... 0111011 @r +remw 0000001 ..... ..... 110 ..... 0111011 @r +remuw 0000001 ..... ..... 111 ..... 0111011 @r diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 977b1b10a3..e53944bf0e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr csrrwi ............ ..... 101 ..... 1110011 @csr csrrsi ............ ..... 110 ..... 1110011 @csr csrrci ............ ..... 111 ..... 1110011 @csr + +# *** RV32M Standard Extension *** +mul 0000001 ..... ..... 000 ..... 0110011 @r +mulh 0000001 ..... ..... 001 ..... 0110011 @r +mulhsu 0000001 ..... ..... 010 ..... 0110011 @r +mulhu 0000001 ..... ..... 011 ..... 0110011 @r +div 0000001 ..... ..... 100 ..... 0110011 @r +divu 0000001 ..... ..... 101 ..... 0110011 @r +rem 0000001 ..... ..... 110 ..... 0110011 @r +remu 0000001 ..... ..... 111 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_tr= ans/trans_rvm.inc.c new file mode 100644 index 0000000000..ec3197ede8 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -0,0 +1,100 @@ +/* + * RISC-V translation routines for the RV64M Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + + +static bool trans_mul(DisasContext *ctx, arg_mul *a) +{ + gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulh(DisasContext *ctx, arg_mulh *a) +{ + gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) +{ + gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) +{ + gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_div(DisasContext *ctx, arg_div *a) +{ + gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divu(DisasContext *ctx, arg_divu *a) +{ + gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_rem(DisasContext *ctx, arg_rem *a) +{ + gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remu(DisasContext *ctx, arg_remu *a) +{ + gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2); + return true; +} + +#ifdef TARGET_RISCV64 +static bool trans_mulw(DisasContext *ctx, arg_mulw *a) +{ + gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divw(DisasContext *ctx, arg_divw *a) +{ + gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_divuw(DisasContext *ctx, arg_divuw *a) +{ + gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remw(DisasContext *ctx, arg_remw *a) +{ + gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2); + return true; +} + +static bool trans_remuw(DisasContext *ctx, arg_remuw *a) +{ + gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a020305556..666c039662 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1649,6 +1649,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "decode_insn32.inc.c" /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" +#include "insn_trans/trans_rvm.inc.c" =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { @@ -1670,15 +1671,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_ARITH: -#if defined(TARGET_RISCV64) - case OPC_RISC_ARITH_W: -#endif - if (rd =3D=3D 0) { - break; /* NOP */ - } - gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2); - break; case OPC_RISC_FP_LOAD: gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); break; --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151532398236.43563895244017; Tue, 22 Jan 2019 02:05:32 -0800 (PST) Received: from localhost ([127.0.0.1]:41968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsvu-0002jZ-B3 for importer@patchew.org; Tue, 22 Jan 2019 05:05:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVg-0006N0-Hz for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsNa-00055A-TU for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:00 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41902) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsNa-000542-KQ; Tue, 22 Jan 2019 04:29:58 -0500 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1glsNY-0004Ir-HT; Tue, 22 Jan 2019 10:29:56 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3095052-3; Tue, 22 Jan 2019 09:29:55 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:44 +0100 Message-Id: <20190122092909.5341-11-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 10/35] target/riscv: Convert RV32A insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 17 +++ target/riscv/insn_trans/trans_rva.inc.c | 149 ++++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 167 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rva.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e53944bf0e..00b9e2d9a5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -34,6 +34,7 @@ # Argument sets: &b imm rs2 rs1 &shift shamt rs1 rd +&atomic aq rl rs2 rs1 rd =20 # Formats 32: @r ....... ..... ..... ... ..... ....... %rs2 %r= s1 %rd @@ -46,6 +47,9 @@ @sh ...... ...... ..... ... ..... ....... &shift shamt=3D%sh10 = %rs1 %rd @csr ............ ..... ... ..... ....... %csr %r= s1 %rd =20 +@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=3D0 = %rs1 %rd +@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %r= s1 %rd + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u @@ -102,3 +106,16 @@ div 0000001 ..... ..... 100 ..... 0110011 @r divu 0000001 ..... ..... 101 ..... 0110011 @r rem 0000001 ..... ..... 110 ..... 0110011 @r remu 0000001 ..... ..... 111 ..... 0110011 @r + +# *** RV32A Standard Extension *** +lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld +sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st +amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st +amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st +amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st +amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st +amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st +amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st +amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st +amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st +amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_tr= ans/trans_rva.inc.c new file mode 100644 index 0000000000..ab6ccf0e90 --- /dev/null +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -0,0 +1,149 @@ +/* + * RISC-V translation routines for the RV64A Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) +{ + TCGv src1 =3D tcg_temp_new(); + /* Put addr in load_res, data in load_val. */ + gen_get_gpr(src1, a->rs1); + if (a->rl) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); + if (a->aq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + tcg_gen_mov_tl(load_res, src1); + gen_set_gpr(a->rd, load_val); + + tcg_temp_free(src1); + return true; +} + +static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) +{ + TCGv src1 =3D tcg_temp_new(); + TCGv src2 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + TCGLabel *l1 =3D gen_new_label(); + TCGLabel *l2 =3D gen_new_label(); + + gen_get_gpr(src1, a->rs1); + tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); + + gen_get_gpr(src2, a->rs2); + /* + * Note that the TCG atomic primitives are SC, + * so we can ignore AQ/RL along this path. + */ + tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, + ctx->mem_idx, mop); + tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); + gen_set_gpr(a->rd, dat); + tcg_gen_br(l2); + + gen_set_label(l1); + /* + * Address comparion failure. However, we still need to + * provide the memory barrier implied by AQ/RL. + */ + tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL); + tcg_gen_movi_tl(dat, 1); + gen_set_gpr(a->rd, dat); + + gen_set_label(l2); + tcg_temp_free(dat); + tcg_temp_free(src1); + tcg_temp_free(src2); + return true; +} + +static bool gen_amo(DisasContext *ctx, arg_atomic *a, + void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp), + TCGMemOp mop) +{ + TCGv src1 =3D tcg_temp_new(); + TCGv src2 =3D tcg_temp_new(); + + gen_get_gpr(src1, a->rs1); + gen_get_gpr(src2, a->rs2); + + (*func)(src2, src1, src2, ctx->mem_idx, mop); + + gen_set_gpr(a->rd, src2); + tcg_temp_free(src1); + tcg_temp_free(src2); + return true; +} + +static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) +{ + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) +{ + return gen_sc(ctx, a, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)); +} + +static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= SL)); +} + +static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= SL)); +} + +static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= SL)); +} + +static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TES= L)); +} + +static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= ESL)); +} + +static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= ESL)); +} + +static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= ESL)); +} + +static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 666c039662..98180002ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1650,6 +1650,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" +#include "insn_trans/trans_rva.inc.c" =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 22 Jan 2019 10:29:57 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069620-4; Tue, 22 Jan 2019 09:29:56 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:45 +0100 Message-Id: <20190122092909.5341-12-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 11/35] target/riscv: Convert RV64A insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn32-64.decode | 13 +++ target/riscv/insn_trans/trans_rva.inc.c | 58 ++++++++++ target/riscv/translate.c | 140 ------------------------ 3 files changed, 71 insertions(+), 140 deletions(-) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 008f100546..0bee95c984 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -43,3 +43,16 @@ divw 0000001 ..... ..... 100 ..... 0111011 @r divuw 0000001 ..... ..... 101 ..... 0111011 @r remw 0000001 ..... ..... 110 ..... 0111011 @r remuw 0000001 ..... ..... 111 ..... 0111011 @r + +# *** RV64A Standard Extension (in addition to RV32A) *** +lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld +sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st +amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st +amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st +amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st +amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st +amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st +amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st +amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st +amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st +amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_tr= ans/trans_rva.inc.c index ab6ccf0e90..11620e030e 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -147,3 +147,61 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amo= maxu_w *a) { return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= ESL)); } + +#ifdef TARGET_RISCV64 + +static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) +{ + return gen_lr(ctx, a, MO_ALIGN | MO_TEQ); +} + +static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a) +{ + return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ)); +} + +static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TE= Q)); +} + +static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TE= Q)); +} + +static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TE= Q)); +} + +static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ= )); +} + +static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_T= EQ)); +} + +static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_T= EQ)); +} + +static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_T= EQ)); +} + +static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) +{ + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_T= EQ)); +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 98180002ef..944836dd7c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -711,143 +711,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t = opc, int rs1, tcg_temp_free(t0); } =20 -static void gen_atomic(DisasContext *ctx, uint32_t opc, - int rd, int rs1, int rs2) -{ - TCGv src1, src2, dat; - TCGLabel *l1, *l2; - TCGMemOp mop; - bool aq, rl; - - /* Extract the size of the atomic operation. */ - switch (extract32(opc, 12, 3)) { - case 2: /* 32-bit */ - mop =3D MO_ALIGN | MO_TESL; - break; -#if defined(TARGET_RISCV64) - case 3: /* 64-bit */ - mop =3D MO_ALIGN | MO_TEQ; - break; -#endif - default: - gen_exception_illegal(ctx); - return; - } - rl =3D extract32(opc, 25, 1); - aq =3D extract32(opc, 26, 1); - - src1 =3D tcg_temp_new(); - src2 =3D tcg_temp_new(); - - switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) { - case OPC_RISC_LR: - /* Put addr in load_res, data in load_val. */ - gen_get_gpr(src1, rs1); - if (rl) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); - if (aq) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - tcg_gen_mov_tl(load_res, src1); - gen_set_gpr(rd, load_val); - break; - - case OPC_RISC_SC: - l1 =3D gen_new_label(); - l2 =3D gen_new_label(); - dat =3D tcg_temp_new(); - - gen_get_gpr(src1, rs1); - tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); - - gen_get_gpr(src2, rs2); - /* Note that the TCG atomic primitives are SC, - so we can ignore AQ/RL along this path. */ - tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2, - ctx->mem_idx, mop); - tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val); - gen_set_gpr(rd, dat); - tcg_gen_br(l2); - - gen_set_label(l1); - /* Address comparion failure. However, we still need to - provide the memory barrier implied by AQ/RL. */ - tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL); - tcg_gen_movi_tl(dat, 1); - gen_set_gpr(rd, dat); - - gen_set_label(l2); - tcg_temp_free(dat); - break; - - case OPC_RISC_AMOSWAP: - /* Note that the TCG atomic primitives are SC, - so we can ignore AQ/RL along this path. */ - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOADD: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOXOR: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOAND: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOOR: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOMIN: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOMAX: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOMINU: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - case OPC_RISC_AMOMAXU: - gen_get_gpr(src1, rs1); - gen_get_gpr(src2, rs2); - tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(rd, src2); - break; - - default: - gen_exception_illegal(ctx); - break; - } - - tcg_temp_free(src1); - tcg_temp_free(src2); -} - static void gen_set_rm(DisasContext *ctx, int rm) { TCGv_i32 t0; @@ -1679,9 +1542,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disas= Context *ctx) gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2, GET_STORE_IMM(ctx->opcode)); break; - case OPC_RISC_ATOMIC: - gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2); - break; case OPC_RISC_FMADD: gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2, GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150855990683.510839687823; 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Tue, 22 Jan 2019 09:29:58 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:46 +0100 Message-Id: <20190122092909.5341-13-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 12/35] target/riscv: Convert RV32F insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 35 +++ target/riscv/insn_trans/trans_rvf.inc.c | 334 ++++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 370 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 00b9e2d9a5..e40836bf03 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,12 +17,14 @@ # this program. If not, see . =20 # Fields: +%rs3 27:5 %rs2 20:5 %rs1 15:5 %rd 7:5 =20 %sh10 20:10 %csr 20:12 +%rm 12:3 =20 # immediates: %imm_i 20:s12 @@ -50,6 +52,11 @@ @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=3D0 = %rs1 %rd @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %r= s1 %rd =20 +@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd +@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd +@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd +@r2 ....... ..... ..... ... ..... ....... %rs1 %rd + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u @@ -119,3 +126,31 @@ amomin_w 10000 . . ..... ..... 010 ..... 0101111 @at= om_st amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st + +# *** RV32F Standard Extension *** +flw ............ ..... 010 ..... 0000111 @i +fsw ....... ..... ..... 010 ..... 0100111 @s +fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm +fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm +fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm +fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm +fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm +fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm +fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r +fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r +fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r +fmin_s 0010100 ..... ..... 000 ..... 1010011 @r +fmax_s 0010100 ..... ..... 001 ..... 1010011 @r +fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm +fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 +feq_s 1010000 ..... ..... 010 ..... 1010011 @r +flt_s 1010000 ..... ..... 001 ..... 1010011 @r +fle_s 1010000 ..... ..... 000 ..... 1010011 @r +fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 +fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm +fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm +fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_tr= ans/trans_rvf.inc.c new file mode 100644 index 0000000000..b101593ac4 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -0,0 +1,334 @@ +/* + * RISC-V translation routines for the RV64F Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_FPU do {\ + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \ + return false; \ +} while (0) + +static bool trans_flw(DisasContext *ctx, arg_flw *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); + /* RISC-V requires NaN-boxing of narrower width floating point values = */ + tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], 0xffffffff00000000ULL); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fsw(DisasContext *ctx, arg_fsw *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + return true; +} + +static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) +{ + REQUIRE_FPU; + if (a->rs1 =3D=3D a->rs2) { /* FMOV */ + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { /* FSGNJ */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs= 1], + 0, 31); + } + return true; +} + +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a) +{ + REQUIRE_FPU; + if (a->rs1 =3D=3D a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a) +{ + REQUIRE_FPU; + if (a->rs1 =3D=3D a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) +{ + REQUIRE_FPU; + + gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) +{ + REQUIRE_FPU; + + gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + return true; +} + +static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a) +{ + /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + +#if defined(TARGET_RISCV64) + tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); +#else + tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); +#endif + + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) +{ + REQUIRE_FPU; + TCGv t0 =3D tcg_temp_new(); + gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) +{ + REQUIRE_FPU; + TCGv t0 =3D tcg_temp_new(); + gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) +{ + REQUIRE_FPU; + TCGv t0 =3D tcg_temp_new(); + gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + + gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); + + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a) +{ + /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + +#if defined(TARGET_RISCV64) + tcg_gen_mov_i64(cpu_fpr[a->rd], t0); +#else + tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0); +#endif + + tcg_temp_free(t0); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 944836dd7c..933ca9fb69 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1514,6 +1514,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" #include "insn_trans/trans_rva.inc.c" +#include "insn_trans/trans_rvf.inc.c" =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150664021816.7506417893783; Tue, 22 Jan 2019 01:51:04 -0800 (PST) Received: from localhost ([127.0.0.1]:41745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glshw-0008Fr-3c for importer@patchew.org; Tue, 22 Jan 2019 04:51:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVc-0006NI-FN for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsO8-0005ZV-Cb for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:34 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:53662) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsO0-0005Fx-18; Tue, 22 Jan 2019 04:30:29 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1glsNc-0004lM-LV; Tue, 22 Jan 2019 10:30:00 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069621-4; Tue, 22 Jan 2019 09:29:59 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:47 +0100 Message-Id: <20190122092909.5341-14-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 13/35] target/riscv: Convert RV64F insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 54 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 0bee95c984..6319f872ac 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -56,3 +56,9 @@ amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_= st amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st + +# *** RV64F Standard Extension (in addition to RV32F) *** +fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm +fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_tr= ans/trans_rvf.inc.c index b101593ac4..b667c576d4 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -332,3 +332,57 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w= _x *a) =20 return true; } + +#ifdef TARGET_RISCV64 +static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + + tcg_temp_free(t0); + return true; +} +#endif --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151144802932.5710939186079; Tue, 22 Jan 2019 01:59:04 -0800 (PST) Received: from localhost ([127.0.0.1]:41882 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glspj-0006Ic-NR for importer@patchew.org; Tue, 22 Jan 2019 04:59:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVa-0006N0-As for qemu-devel@nongnu.org; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 14/35] target/riscv: Convert RV32D insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 28 +++ target/riscv/insn_trans/trans_rvd.inc.c | 315 ++++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 344 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e40836bf03..e64b2b5e34 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -154,3 +154,31 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 + +# *** RV32D Standard Extension *** +fld ............ ..... 011 ..... 0000111 @i +fsd ....... ..... ..... 011 ..... 0100111 @s +fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm +fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm +fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm +fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm +fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm +fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm +fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r +fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r +fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r +fmin_d 0010101 ..... ..... 000 ..... 1010011 @r +fmax_d 0010101 ..... ..... 001 ..... 1010011 @r +fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm +feq_d 1010001 ..... ..... 010 ..... 1010011 @r +flt_d 1010001 ..... ..... 001 ..... 1010011 @r +fle_d 1010001 ..... ..... 000 ..... 1010011 @r +fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 +fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm +fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_tr= ans/trans_rvd.inc.c new file mode 100644 index 0000000000..a7e2335ffa --- /dev/null +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -0,0 +1,315 @@ +/* + * RISC-V translation routines for the RV64D Standard Extension. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_fld(DisasContext *ctx, arg_fld *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fsd(DisasContext *ctx, arg_fsd *a) +{ + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + REQUIRE_FPU; + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(t0); + return true; +} + +static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) +{ + REQUIRE_FPU; + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + return true; +} + +static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) +{ + if (a->rs1 =3D=3D a->rs2) { /* FMOV */ + tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], + cpu_fpr[a->rs1], 0, 63); + } + return true; +} + +static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) +{ + REQUIRE_FPU; + if (a->rs1 =3D=3D a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); + tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) +{ + REQUIRE_FPU; + if (a->rs1 =3D=3D a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); + } else { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); + tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_temp_free_i64(t0); + } + return true; +} + +static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) +{ + REQUIRE_FPU; + + gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) +{ + REQUIRE_FPU; + + gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + + return true; +} + +static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) +{ + REQUIRE_FPU; + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + return true; +} + +static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + return true; +} + +static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 933ca9fb69..7f3443db20 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1515,6 +1515,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvm.inc.c" #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" +#include "insn_trans/trans_rvd.inc.c" =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150478456930.3679811084826; Tue, 22 Jan 2019 01:47:58 -0800 (PST) Received: from localhost ([127.0.0.1]:41689 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsez-0005hn-9L for importer@patchew.org; Tue, 22 Jan 2019 04:47:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVZ-0006NI-7y for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOF-0005co-01 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:40 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsO1-0005Ih-Ji; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 15/35] target/riscv: Convert RV64D insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32-64.decode | 8 + target/riscv/insn_trans/trans_rvd.inc.c | 73 ++++ target/riscv/translate.c | 487 +----------------------- 3 files changed, 82 insertions(+), 486 deletions(-) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 6319f872ac..380bf791bc 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm + +# *** RV64D Standard Extension (in addition to RV32D) *** +fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm +fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 +fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm +fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_tr= ans/trans_rvd.inc.c index a7e2335ffa..2e45c8ed7e 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -313,3 +313,76 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcv= t_d_wu *a) =20 return true; } + +#ifdef TARGET_RISCV64 + +static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a) +{ + REQUIRE_FPU; + + gen_set_gpr(a->rd, cpu_fpr[a->rs1]); + return true; +} + +static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); + tcg_temp_free(t0); + return true; +} + +static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a) +{ + REQUIRE_FPU; + + TCGv t0 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + + tcg_gen_mov_tl(cpu_fpr[a->rd], t0); + tcg_temp_free(t0); + return true; +} +#endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7f3443db20..4dda78d7c1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -180,44 +180,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(rh); } =20 -static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1, - uint32_t rs2, int rm, uint64_t min) -{ - switch (rm) { - case 0: /* fsgnj */ - if (rs1 =3D=3D rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]); - } else { - tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1], - 0, min =3D=3D INT32_MIN ? 31 : 63); - } - break; - case 1: /* fsgnjn */ - if (rs1 =3D=3D rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min); - } else { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[rs2]); - tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1], - 0, min =3D=3D INT32_MIN ? 31 : 63); - tcg_temp_free_i64(t0); - } - break; - case 2: /* fsgnjx */ - if (rs1 =3D=3D rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min); - } else { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[rs2], min); - tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0); - tcg_temp_free_i64(t0); - } - break; - default: - gen_exception_illegal(ctx); - } -} - static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2) { @@ -724,421 +686,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } =20 -static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd, - int rs1, int rs2, int rs3, int rm) -{ - switch (opc) { - case OPC_RISC_FMADD_S: - gen_set_rm(ctx, rm); - gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - case OPC_RISC_FMADD_D: - gen_set_rm(ctx, rm); - gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - default: - gen_exception_illegal(ctx); - break; - } -} - -static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd, - int rs1, int rs2, int rs3, int rm) -{ - switch (opc) { - case OPC_RISC_FMSUB_S: - gen_set_rm(ctx, rm); - gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - case OPC_RISC_FMSUB_D: - gen_set_rm(ctx, rm); - gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - default: - gen_exception_illegal(ctx); - break; - } -} - -static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd, - int rs1, int rs2, int rs3, int rm) -{ - switch (opc) { - case OPC_RISC_FNMSUB_S: - gen_set_rm(ctx, rm); - gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - case OPC_RISC_FNMSUB_D: - gen_set_rm(ctx, rm); - gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - default: - gen_exception_illegal(ctx); - break; - } -} - -static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd, - int rs1, int rs2, int rs3, int rm) -{ - switch (opc) { - case OPC_RISC_FNMADD_S: - gen_set_rm(ctx, rm); - gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - case OPC_RISC_FNMADD_D: - gen_set_rm(ctx, rm); - gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], - cpu_fpr[rs2], cpu_fpr[rs3]); - break; - default: - gen_exception_illegal(ctx); - break; - } -} - -static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, - int rs1, int rs2, int rm) -{ - TCGv t0 =3D NULL; - - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { - goto do_illegal; - } - - switch (opc) { - case OPC_RISC_FADD_S: - gen_set_rm(ctx, rm); - gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FSUB_S: - gen_set_rm(ctx, rm); - gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FMUL_S: - gen_set_rm(ctx, rm); - gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FDIV_S: - gen_set_rm(ctx, rm); - gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FSQRT_S: - gen_set_rm(ctx, rm); - gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]); - break; - case OPC_RISC_FSGNJ_S: - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN); - break; - - case OPC_RISC_FMIN_S: - /* also handles: OPC_RISC_FMAX_S */ - switch (rm) { - case 0x0: - gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[= rs2]); - break; - case 0x1: - gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[= rs2]); - break; - default: - goto do_illegal; - } - break; - - case OPC_RISC_FEQ_S: - /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */ - t0 =3D tcg_temp_new(); - switch (rm) { - case 0x0: - gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - case 0x1: - gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - case 0x2: - gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - default: - goto do_illegal; - } - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - - case OPC_RISC_FCVT_W_S: - /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S = */ - t0 =3D tcg_temp_new(); - switch (rs2) { - case 0: /* FCVT_W_S */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]); - break; - case 1: /* FCVT_WU_S */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]); - break; -#if defined(TARGET_RISCV64) - case 2: /* FCVT_L_S */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]); - break; - case 3: /* FCVT_LU_S */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]); - break; -#endif - default: - goto do_illegal; - } - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - - case OPC_RISC_FCVT_S_W: - /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU = */ - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - switch (rs2) { - case 0: /* FCVT_S_W */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0); - break; - case 1: /* FCVT_S_WU */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0); - break; -#if defined(TARGET_RISCV64) - case 2: /* FCVT_S_L */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0); - break; - case 3: /* FCVT_S_LU */ - gen_set_rm(ctx, rm); - gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0); - break; -#endif - default: - goto do_illegal; - } - tcg_temp_free(t0); - break; - - case OPC_RISC_FMV_X_S: - /* also OPC_RISC_FCLASS_S */ - t0 =3D tcg_temp_new(); - switch (rm) { - case 0: /* FMV */ -#if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]); -#else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]); -#endif - break; - case 1: - gen_helper_fclass_s(t0, cpu_fpr[rs1]); - break; - default: - goto do_illegal; - } - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - - case OPC_RISC_FMV_S_X: - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); -#if defined(TARGET_RISCV64) - tcg_gen_mov_i64(cpu_fpr[rd], t0); -#else - tcg_gen_extu_i32_i64(cpu_fpr[rd], t0); -#endif - tcg_temp_free(t0); - break; - - /* double */ - case OPC_RISC_FADD_D: - gen_set_rm(ctx, rm); - gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FSUB_D: - gen_set_rm(ctx, rm); - gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FMUL_D: - gen_set_rm(ctx, rm); - gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FDIV_D: - gen_set_rm(ctx, rm); - gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]= ); - break; - case OPC_RISC_FSQRT_D: - gen_set_rm(ctx, rm); - gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]); - break; - case OPC_RISC_FSGNJ_D: - gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN); - break; - - case OPC_RISC_FMIN_D: - /* also OPC_RISC_FMAX_D */ - switch (rm) { - case 0: - gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[= rs2]); - break; - case 1: - gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[= rs2]); - break; - default: - goto do_illegal; - } - break; - - case OPC_RISC_FCVT_S_D: - switch (rs2) { - case 1: - gen_set_rm(ctx, rm); - gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]); - break; - default: - goto do_illegal; - } - break; - - case OPC_RISC_FCVT_D_S: - switch (rs2) { - case 0: - gen_set_rm(ctx, rm); - gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]); - break; - default: - goto do_illegal; - } - break; - - case OPC_RISC_FEQ_D: - /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */ - t0 =3D tcg_temp_new(); - switch (rm) { - case 0: - gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - case 1: - gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - case 2: - gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]); - break; - default: - goto do_illegal; - } - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - - case OPC_RISC_FCVT_W_D: - /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D = */ - t0 =3D tcg_temp_new(); - switch (rs2) { - case 0: - gen_set_rm(ctx, rm); - gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]); - break; - case 1: - gen_set_rm(ctx, rm); - gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]); - break; -#if defined(TARGET_RISCV64) - case 2: - gen_set_rm(ctx, rm); - gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]); - break; - case 3: - gen_set_rm(ctx, rm); - gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]); - break; -#endif - default: - goto do_illegal; - } - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - - case OPC_RISC_FCVT_D_W: - /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU = */ - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - switch (rs2) { - case 0: - gen_set_rm(ctx, rm); - gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0); - break; - case 1: - gen_set_rm(ctx, rm); - gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0); - break; -#if defined(TARGET_RISCV64) - case 2: - gen_set_rm(ctx, rm); - gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0); - break; - case 3: - gen_set_rm(ctx, rm); - gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0); - break; -#endif - default: - goto do_illegal; - } - tcg_temp_free(t0); - break; - - case OPC_RISC_FMV_X_D: - /* also OPC_RISC_FCLASS_D */ - switch (rm) { -#if defined(TARGET_RISCV64) - case 0: /* FMV */ - gen_set_gpr(rd, cpu_fpr[rs1]); - break; -#endif - case 1: - t0 =3D tcg_temp_new(); - gen_helper_fclass_d(t0, cpu_fpr[rs1]); - gen_set_gpr(rd, t0); - tcg_temp_free(t0); - break; - default: - goto do_illegal; - } - break; - -#if defined(TARGET_RISCV64) - case OPC_RISC_FMV_D_X: - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_mov_tl(cpu_fpr[rd], t0); - tcg_temp_free(t0); - break; -#endif - - default: - do_illegal: - if (t0) { - tcg_temp_free(t0); - } - gen_exception_illegal(ctx); - break; - } -} - static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, int rd, int rs1, int csr) { @@ -1519,11 +1066,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { - int rs1; - int rs2; - int rd; + int rs1, rd; uint32_t op; - target_long imm; =20 /* We do not do misaligned address check here: the address should neve= r be * misaligned at this point. Instructions that set PC must do the chec= k, @@ -1532,38 +1076,9 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) =20 op =3D MASK_OP_MAJOR(ctx->opcode); rs1 =3D GET_RS1(ctx->opcode); - rs2 =3D GET_RS2(ctx->opcode); rd =3D GET_RD(ctx->opcode); - imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_FP_LOAD: - gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_FP_STORE: - gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2, - GET_STORE_IMM(ctx->opcode)); - break; - case OPC_RISC_FMADD: - gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2, - GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); - break; - case OPC_RISC_FMSUB: - gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2, - GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); - break; - case OPC_RISC_FNMSUB: - gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2, - GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); - break; - case OPC_RISC_FNMADD: - gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2, - GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); - break; - case OPC_RISC_FP_ARITH: - gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2, - GET_RM(ctx->opcode)); - break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, (ctx->opcode & 0xFFF00000) >> 20); --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151032428236.58238825640785; Tue, 22 Jan 2019 01:57:12 -0800 (PST) Received: from localhost ([127.0.0.1]:41859 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsnv-0004o2-6j for importer@patchew.org; Tue, 22 Jan 2019 04:57:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVa-00068S-CA for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOE-0005cj-Va for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:40 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60880) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsO4-0005JJ-0Z; Tue, 22 Jan 2019 04:30:29 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1glsNh-0006Ch-7C; Tue, 22 Jan 2019 10:30:05 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100913-5; Tue, 22 Jan 2019 09:30:03 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:50 +0100 Message-Id: <20190122092909.5341-17-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 16/35] target/riscv: Convert RV priv insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Acked-by: Alistair Francis Tested-by: Alistair Francis --- target/riscv/insn32.decode | 15 +++ .../riscv/insn_trans/trans_privileged.inc.c | 110 ++++++++++++++++++ target/riscv/translate.c | 57 +-------- 3 files changed, 126 insertions(+), 56 deletions(-) create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e64b2b5e34..ecc46a50cc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -57,6 +57,21 @@ @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd =20 +@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + + +# *** Privileged Instructions *** +ecall 000000000000 00000 000 00000 1110011 +ebreak 000000000001 00000 000 00000 1110011 +uret 0000000 00010 00000 000 00000 1110011 +sret 0001000 00010 00000 000 00000 1110011 +hret 0010000 00010 00000 000 00000 1110011 +mret 0011000 00010 00000 000 00000 1110011 +wfi 0001000 00101 00000 000 00000 1110011 +sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma +sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c new file mode 100644 index 0000000000..fb2da8f5f0 --- /dev/null +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -0,0 +1,110 @@ +/* + * RISC-V translation routines for the RISC-V privileged instructions. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_ecall(DisasContext *ctx, arg_ecall *a) +{ + /* always generates U-level ECALL, fixed in do_interrupt handler */ + generate_exception(ctx, RISCV_EXCP_U_ECALL); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} + +static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) +{ + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} + +static bool trans_uret(DisasContext *ctx, arg_uret *a) +{ + return false; +} + +static bool trans_sret(DisasContext *ctx, arg_sret *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + + if (riscv_has_ext(ctx->env, RVS)) { + gen_helper_sret(cpu_pc, cpu_env, cpu_pc); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + } else { + return false; + } + return true; +#else + return false; +#endif +} + +static bool trans_hret(DisasContext *ctx, arg_hret *a) +{ + return false; +} + +static bool trans_mret(DisasContext *ctx, arg_mret *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_mret(cpu_pc, cpu_env, cpu_pc); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + +static bool trans_wfi(DisasContext *ctx, arg_wfi *a) +{ +#ifndef CONFIG_USER_ONLY + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_helper_wfi(cpu_env); + return true; +#else + return false; +#endif +} + +static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->env->priv_ver =3D=3D PRIV_VERSION_1_10_0) { + gen_helper_tlb_flush(cpu_env); + return true; + } +#endif + return false; +} + +static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) +{ +#ifndef CONFIG_USER_ONLY + if (ctx->env->priv_ver <=3D PRIV_VERSION_1_09_1) { + gen_helper_tlb_flush(cpu_env); + return true; + } +#endif + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4dda78d7c1..ff15e0f7ed 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -689,26 +689,8 @@ static void gen_set_rm(DisasContext *ctx, int rm) static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, int rd, int rs1, int csr) { - TCGv source1, dest; - source1 =3D tcg_temp_new(); - dest =3D tcg_temp_new(); - gen_get_gpr(source1, rs1); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); =20 -#ifndef CONFIG_USER_ONLY - /* Extract funct7 value and check whether it matches SFENCE.VMA */ - if ((opc =3D=3D OPC_RISC_ECALL) && ((csr >> 5) =3D=3D 9)) { - if (env->priv_ver =3D=3D PRIV_VERSION_1_10_0) { - /* sfence.vma */ - /* TODO: handle ASID specific fences */ - gen_helper_tlb_flush(cpu_env); - return; - } else { - gen_exception_illegal(ctx); - } - } -#endif - switch (opc) { case OPC_RISC_ECALL: switch (csr) { @@ -723,50 +705,12 @@ static void gen_system(CPURISCVState *env, DisasConte= xt *ctx, uint32_t opc, tcg_gen_exit_tb(NULL, 0); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; break; -#ifndef CONFIG_USER_ONLY - case 0x002: /* URET */ - gen_exception_illegal(ctx); - break; - case 0x102: /* SRET */ - if (riscv_has_ext(env, RVS)) { - gen_helper_sret(cpu_pc, cpu_env, cpu_pc); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp =3D DISAS_NORETURN; - } else { - gen_exception_illegal(ctx); - } - break; - case 0x202: /* HRET */ - gen_exception_illegal(ctx); - break; - case 0x302: /* MRET */ - gen_helper_mret(cpu_pc, cpu_env, cpu_pc); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp =3D DISAS_NORETURN; - break; - case 0x7b2: /* DRET */ - gen_exception_illegal(ctx); - break; - case 0x105: /* WFI */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - gen_helper_wfi(cpu_env); - break; - case 0x104: /* SFENCE.VM */ - if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { - gen_helper_tlb_flush(cpu_env); - } else { - gen_exception_illegal(ctx); - } - break; -#endif default: gen_exception_illegal(ctx); break; } break; } - tcg_temp_free(source1); - tcg_temp_free(dest); } =20 static void decode_RV32_64C0(DisasContext *ctx) @@ -1063,6 +1007,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rva.inc.c" #include "insn_trans/trans_rvf.inc.c" #include "insn_trans/trans_rvd.inc.c" +#include "insn_trans/trans_privileged.inc.c" =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548151122381465.95206789978; Tue, 22 Jan 2019 01:58:42 -0800 (PST) Received: from localhost ([127.0.0.1]:41873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glspN-0005yX-A4 for importer@patchew.org; Tue, 22 Jan 2019 04:58:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVb-0006AI-1n for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOB-0005ah-54 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:37 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41918) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsO5-0005Lo-TJ; Tue, 22 Jan 2019 04:30:31 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1glsNi-0004Jq-Ij; Tue, 22 Jan 2019 10:30:07 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069624-4; Tue, 22 Jan 2019 09:30:05 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:51 +0100 Message-Id: <20190122092909.5341-18-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++++++++++++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 75 +++++++++++++++++++++++++ target/riscv/translate.c | 53 ++++++----------- 4 files changed, 154 insertions(+), 38 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 05087a91bb..9c6c109327 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -10,4 +10,11 @@ target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODE= TREE) $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) =20 -target/riscv/translate.o: target/riscv/decode_insn32.inc.c +target/riscv/decode_insn16.inc.c: \ + $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<,= \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ + target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode new file mode 100644 index 0000000000..558c0c41f0 --- /dev/null +++ b/target/riscv/insn16.decode @@ -0,0 +1,55 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# Fields: +%rd 7:5 +%rs1_3 7:3 !function=3Dex_rvc_register +%rs2_3 2:3 !function=3Dex_rvc_register + +# Immediates: +%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=3Dex_shift_2 +%uimm_cl_d 5:2 10:3 !function=3Dex_shift_3 +%uimm_cl_w 5:1 10:3 6:1 !function=3Dex_shift_2 + + +# Argument sets: +&cl rs1 rd +&cl_dw uimm rs1 rd +&ciw nzuimm rd +&cs rs1 rs2 +&cs_dw uimm rs1 rs2 + + +# Formats 16: +@ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 +@cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 +@cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 +@cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 + + +# *** RV64C Standard Extension (Quadrant 0) *** +c_addi4spn 000 ........ ... 00 @ciw +c_fld 001 ... ... .. ... 00 @cl_d +c_lw 010 ... ... .. ... 00 @cl_w +c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually +c_fsd 101 ... ... .. ... 00 @cs_d +c_sw 110 ... ... .. ... 00 @cs_w +c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c new file mode 100644 index 0000000000..93ec8aa30b --- /dev/null +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -0,0 +1,75 @@ +/* + * RISC-V translation routines for the RVC Compressed Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) +{ + if (a->nzuimm =3D=3D 0) { + /* Reserved in ISA */ + return false; + } + arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->nzuimm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) +{ + arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) +{ + arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLW ( RV32FC-only ) */ + return false; +#else + /* C.LD ( RV64C/RV128C-only ) */ + return false; +#endif +} + +static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) +{ + arg_fsd arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) +{ + arg_sw arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSW ( RV32FC-only ) */ + return false; +#else + /* C.SD ( RV64C/RV128C-only ) */ + return false; +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ff15e0f7ed..1ee13c1907 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -720,27 +720,6 @@ static void decode_RV32_64C0(DisasContext *ctx) uint8_t rs1s =3D GET_C_RS1S(ctx->opcode); =20 switch (funct3) { - case 0: - /* illegal */ - if (ctx->opcode =3D=3D 0) { - gen_exception_illegal(ctx); - } else { - /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2, - GET_C_ADDI4SPN_IMM(ctx->opcode)); - } - break; - case 1: - /* C.FLD -> fld rd', offset[7:3](rs1')*/ - gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); - /* C.LQ(RV128) */ - break; - case 2: - /* C.LW -> lw rd', offset[6:2](rs1') */ - gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); - break; case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ @@ -752,21 +731,6 @@ static void decode_RV32_64C0(DisasContext *ctx) GET_C_LW_IMM(ctx->opcode)); #endif break; - case 4: - /* reserved */ - gen_exception_illegal(ctx); - break; - case 5: - /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */ - gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); - /* C.SQ (RV128) */ - break; - case 6: - /* C.SW -> sw rs2', offset[6:2](rs1')*/ - gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); - break; case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ @@ -996,8 +960,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasC= ontext *ctx) return imm << amount; \ } EX_SH(1) +EX_SH(2) +EX_SH(3) EX_SH(12) =20 +static int ex_rvc_register(int reg) +{ + return 8 + reg; +} + bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" @@ -1009,6 +980,11 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn); #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 +bool decode_insn16(DisasContext *ctx, uint16_t insn); +/* auto-generated decoder*/ +#include "decode_insn16.inc.c" +#include "insn_trans/trans_rvc.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1, rd; @@ -1042,7 +1018,10 @@ static void decode_opc(DisasContext *ctx) gen_exception_illegal(ctx); } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - decode_RV32_64C(ctx->env, ctx); + if (!decode_insn16(ctx, ctx->opcode)) { + /* fall back to old decoder */ + decode_RV32_64C(ctx->env, ctx); + } } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn16.decode | 43 +++++++ target/riscv/insn_trans/trans_rvc.inc.c | 151 ++++++++++++++++++++++++ target/riscv/translate.c | 118 +----------------- 3 files changed, 195 insertions(+), 117 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 558c0c41f0..29dade0fa1 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -22,28 +22,53 @@ %rs2_3 2:3 !function=3Dex_rvc_register =20 # Immediates: +%imm_ci 12:s1 2:5 %nzuimm_ciw 7:4 11:2 5:1 6:1 !function=3Dex_shift_2 %uimm_cl_d 5:2 10:3 !function=3Dex_shift_3 %uimm_cl_w 5:1 10:3 6:1 !function=3Dex_shift_2 +%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=3Dex_shift_1 +%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 + +%nzuimm_6bit 12:1 2:5 + +%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 +%imm_lui 12:s1 2:5 !function=3Dex_shift_12 + =20 =20 # Argument sets: &cl rs1 rd &cl_dw uimm rs1 rd +&ci imm rd &ciw nzuimm rd &cs rs1 rs2 &cs_dw uimm rs1 rs2 +&cb imm rs1 +&cr rd rs2 +&c_j imm +&c_shift shamt rd + =20 +&c_addi16sp_lui imm_lui imm_addi16sp rd =20 # Formats 16: +@ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 @cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 +@cs_2 ... ... ... .. ... .. &cr rd=3D%rs1_3 rs= 2=3D%rs2_3 @cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 +@cj ... ........... .. &c_j imm=3D%imm_cj =20 +@c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16= sp %rd + +@c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit + +@c_andi ... . .. ... ..... .. &ci imm=3D%imm_ci rd=3D%rs1_3 =20 # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw @@ -53,3 +78,21 @@ c_flw_ld 011 --- ... -- ... 00 @cl #Note: M= ust parse uimm manually c_fsd 101 ... ... .. ... 00 @cs_d c_sw 110 ... ... .. ... 00 @cs_w c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually + +# *** RV64C Standard Extension (Quadrant 1) *** +c_addi 000 . ..... ..... 01 @ci +c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually +c_li 010 . ..... ..... 01 @ci +c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI +c_srli 100 . 00 ... ..... 01 @c_shift +c_srai 100 . 01 ... ..... 01 @c_shift +c_andi 100 . 10 ... ..... 01 @c_andi +c_sub 100 0 11 ... 00 ... 01 @cs_2 +c_xor 100 0 11 ... 01 ... 01 @cs_2 +c_or 100 0 11 ... 10 ... 01 @cs_2 +c_and 100 0 11 ... 11 ... 01 @cs_2 +c_subw 100 1 11 ... 00 ... 01 @cs_2 +c_addw 100 1 11 ... 01 ... 01 @cs_2 +c_j 101 ........... 01 @cj +c_beqz 110 ... ... ..... 01 @cb +c_bnez 111 ... ... ..... 01 @cb diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index 93ec8aa30b..b06c435c98 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -73,3 +73,154 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw= _sd *a) return false; #endif } + +static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) +{ + if (a->imm =3D=3D 0) { + /* Hint: insn is valid but does not affect state */ + return true; + } + arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) +{ +#ifdef TARGET_RISCV32 + /* C.JAL */ + arg_jal arg =3D { .rd =3D 1, .imm =3D a->imm }; + return trans_jal(ctx, &arg); +#else + /* C.ADDIW */ + arg_addiw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; + return trans_addiw(ctx, &arg); +#endif +} + +static bool trans_c_li(DisasContext *ctx, arg_c_li *a) +{ + if (a->rd =3D=3D 0) { + /* Hint: insn is valid but does not affect state */ + return true; + } + arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 0, .imm =3D a->imm }; + return trans_addi(ctx, &arg); +} + +static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) +{ + if (a->rd =3D=3D 2) { + /* C.ADDI16SP */ + arg_addi arg =3D { .rd =3D 2, .rs1 =3D 2, .imm =3D a->imm_addi16sp= }; + return trans_addi(ctx, &arg); + } else if (a->imm_lui !=3D 0) { + /* C.LUI */ + if (a->rd =3D=3D 0) { + /* Hint: insn is valid but does not affect state */ + return true; + } + arg_lui arg =3D { .rd =3D a->rd, .imm =3D a->imm_lui }; + return trans_lui(ctx, &arg); + } + return false; +} + +static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a) +{ + int shamt =3D a->shamt; + if (shamt =3D=3D 0) { + /* For RV128 a shamt of 0 means a shift by 64 */ + shamt =3D 64; + } + /* Ensure, that shamt[5] is zero for RV32 */ + if (shamt >=3D TARGET_LONG_BITS) { + return false; + } + + arg_srli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; + return trans_srli(ctx, &arg); +} + +static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) +{ + int shamt =3D a->shamt; + if (shamt =3D=3D 0) { + /* For RV128 a shamt of 0 means a shift by 64 */ + shamt =3D 64; + } + /* Ensure, that shamt[5] is zero for RV32 */ + if (shamt >=3D TARGET_LONG_BITS) { + return false; + } + + arg_srai arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; + return trans_srai(ctx, &arg); +} + +static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) +{ + arg_andi arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; + return trans_andi(ctx, &arg); +} + +static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) +{ + arg_sub arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_sub(ctx, &arg); +} + +static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) +{ + arg_xor arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_xor(ctx, &arg); +} + +static bool trans_c_or(DisasContext *ctx, arg_c_or *a) +{ + arg_or arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_or(ctx, &arg); +} + +static bool trans_c_and(DisasContext *ctx, arg_c_and *a) +{ + arg_and arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_and(ctx, &arg); +} + +static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) +{ +#ifdef TARGET_RISCV64 + arg_subw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_subw(ctx, &arg); +#else + return false; +#endif +} + +static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) +{ +#ifdef TARGET_RISCV64 + arg_addw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; + return trans_addw(ctx, &arg); +#else + return false; +#endif +} + +static bool trans_c_j(DisasContext *ctx, arg_c_j *a) +{ + arg_jal arg =3D { .rd =3D 0, .imm =3D a->imm }; + return trans_jal(ctx, &arg); +} + +static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a) +{ + arg_beq arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; + return trans_beq(ctx, &arg); +} + +static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a) +{ + arg_bne arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; + return trans_bne(ctx, &arg); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1ee13c1907..498fbc20ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -745,120 +745,6 @@ static void decode_RV32_64C0(DisasContext *ctx) } } =20 -static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx) -{ - uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); - uint8_t rd_rs1 =3D GET_C_RS1(ctx->opcode); - uint8_t rs1s, rs2s; - uint8_t funct2; - - switch (funct3) { - case 0: - /* C.ADDI -> addi rd, rd, nzimm[5:0] */ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1, - GET_C_IMM(ctx->opcode)); - break; - case 1: -#if defined(TARGET_RISCV64) - /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/ - gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1, - GET_C_IMM(ctx->opcode)); -#else - /* C.JAL(RV32) -> jal x1, offset[11:1] */ - gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode)); -#endif - break; - case 2: - /* C.LI -> addi rd, x0, imm[5:0]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode= )); - break; - case 3: - if (rd_rs1 =3D=3D 2) { - /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/ - gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2, - GET_C_ADDI16SP_IMM(ctx->opcode)); - } else if (rd_rs1 !=3D 0) { - /* C.LUI (rs1/rd =3D/=3D {0,2}) -> lui rd, nzimm[17:12]*/ - tcg_gen_movi_tl(cpu_gpr[rd_rs1], - GET_C_IMM(ctx->opcode) << 12); - } - break; - case 4: - funct2 =3D extract32(ctx->opcode, 10, 2); - rs1s =3D GET_C_RS1S(ctx->opcode); - switch (funct2) { - case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */ - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s, - GET_C_ZIMM(ctx->opcode)); - /* C.SRLI64(RV128) */ - break; - case 1: - /* C.SRAI -> srai rd', rd', shamt[5:0]*/ - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s, - GET_C_ZIMM(ctx->opcode) | 0x400); - /* C.SRAI64(RV128) */ - break; - case 2: - /* C.ANDI -> andi rd', rd', imm[5:0]*/ - gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s, - GET_C_IMM(ctx->opcode)); - break; - case 3: - funct2 =3D extract32(ctx->opcode, 5, 2); - rs2s =3D GET_C_RS2S(ctx->opcode); - switch (funct2) { - case 0: - /* C.SUB -> sub rd', rd', rs2' */ - if (extract32(ctx->opcode, 12, 1) =3D=3D 0) { - gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s); - } -#if defined(TARGET_RISCV64) - else { - gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s); - } -#endif - break; - case 1: - /* C.XOR -> xor rs1', rs1', rs2' */ - if (extract32(ctx->opcode, 12, 1) =3D=3D 0) { - gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s); - } -#if defined(TARGET_RISCV64) - else { - /* C.ADDW (RV64/128) */ - gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s); - } -#endif - break; - case 2: - /* C.OR -> or rs1', rs1', rs2' */ - gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s); - break; - case 3: - /* C.AND -> and rs1', rs1', rs2' */ - gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s); - break; - } - break; - } - break; - case 5: - /* C.J -> jal x0, offset[11:1]*/ - gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode)); - break; - case 6: - /* C.BEQZ -> beq rs1', x0, offset[8:1]*/ - rs1s =3D GET_C_RS1S(ctx->opcode); - gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcod= e)); - break; - case 7: - /* C.BNEZ -> bne rs1', x0, offset[8:1]*/ - rs1s =3D GET_C_RS1S(ctx->opcode); - gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcod= e)); - break; - } -} - static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx) { uint8_t rd, rs2; @@ -945,9 +831,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasCo= ntext *ctx) case 0: decode_RV32_64C0(ctx); break; - case 1: - decode_RV32_64C1(env, ctx); - break; case 2: decode_RV32_64C2(env, ctx); break; @@ -962,6 +845,7 @@ static void decode_RV32_64C(CPURISCVState *env, DisasCo= ntext *ctx) EX_SH(1) EX_SH(2) EX_SH(3) +EX_SH(4) EX_SH(12) =20 static int ex_rvc_register(int reg) --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150401309804.9971591550775; Tue, 22 Jan 2019 01:46:41 -0800 (PST) Received: from localhost ([127.0.0.1]:41683 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsdg-0004j3-To for importer@patchew.org; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Reviewed-by: Richard Henderson Tested-by: Alistair Francis --- target/riscv/insn16.decode | 31 ++++++++ target/riscv/insn_trans/trans_rvc.inc.c | 101 ++++++++++++++++++++++++ target/riscv/translate.c | 83 +------------------ 3 files changed, 134 insertions(+), 81 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 29dade0fa1..0829e3bc59 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -20,6 +20,7 @@ %rd 7:5 %rs1_3 7:3 !function=3Dex_rvc_register %rs2_3 2:3 !function=3Dex_rvc_register +%rs2_5 2:5 =20 # Immediates: %imm_ci 12:s1 2:5 @@ -30,6 +31,10 @@ %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 %nzuimm_6bit 12:1 2:5 +%uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 +%uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 +%uimm_6bit_sd 7:3 10:3 !function=3Dex_shift_3 +%uimm_6bit_sw 7:2 9:4 !function=3Dex_shift_2 =20 %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 %imm_lui 12:s1 2:5 !function=3Dex_shift_12 @@ -48,10 +53,15 @@ &c_j imm &c_shift shamt rd =20 +&c_ld uimm rd +&c_sd uimm rs2 =20 &c_addi16sp_lui imm_lui imm_addi16sp rd +&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd +&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2 =20 # Formats 16: +@cr .... ..... ..... .. &cr rs2=3D%rs2_5 %rd @ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @@ -64,9 +74,19 @@ @cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 @cj ... ........... .. &c_j imm=3D%imm_cj =20 +@c_ld ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_ld %rd +@c_lw ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_lw %rd +@c_sd ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sd rs2=3D%rs= 2_5 +@c_sw ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sw rs2=3D%rs= 2_5 + @c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16= sp %rd +@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=3D%uimm_6bi= t_lw \ + uimm_ldsp=3D%uimm_6bit_ld %rd +@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=3D%uimm_6bi= t_sw \ + uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit +@c_shift2 ... . .. ... ..... .. &c_shift rd=3D%rd shamt=3D%nzuimm= _6bit =20 @c_andi ... . .. ... ..... .. &ci imm=3D%imm_ci rd=3D%rs1_3 =20 @@ -96,3 +116,14 @@ c_addw 100 1 11 ... 01 ... 01 @cs_2 c_j 101 ........... 01 @cj c_beqz 110 ... ... ..... 01 @cb c_bnez 111 ... ... ..... 01 @cb + +# *** RV64C Standard Extension (Quadrant 2) *** +c_slli 000 . ..... ..... 10 @c_shift2 +c_fldsp 001 . ..... ..... 10 @c_ld +c_lwsp 010 . ..... ..... 10 @c_lw +c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 +c_jr_mv 100 0 ..... ..... 10 @cr +c_ebreak_jalr_add 100 1 ..... ..... 10 @cr +c_fsdsp 101 ...... ..... 10 @c_sd +c_swsp 110 . ..... ..... 10 @c_sw +c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index b06c435c98..bcdf64d3b7 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -224,3 +224,104 @@ static bool trans_c_bnez(DisasContext *ctx, arg_c_bne= z *a) arg_bne arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; return trans_bne(ctx, &arg); } + +static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) +{ + int shamt =3D a->shamt; + if (shamt =3D=3D 0) { + /* For RV128 a shamt of 0 means a shift by 64 */ + shamt =3D 64; + } + /* Ensure, that shamt[5] is zero for RV32 */ + if (shamt >=3D TARGET_LONG_BITS) { + return false; + } + + arg_slli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; + return trans_slli(ctx, &arg); +} + +static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) +{ + arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; + return trans_fld(ctx, &arg); +} + +static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) +{ + arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; + return trans_lw(ctx, &arg); +} + +static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) +{ +#ifdef TARGET_RISCV32 + /* C.FLWSP */ + arg_flw arg_flw =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_flws= p }; + return trans_flw(ctx, &arg_flw); +#else + /* C.LDSP */ + arg_ld arg_ld =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_ldsp }; + return trans_ld(ctx, &arg_ld); +#endif + return false; +} + +static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) +{ + if (a->rd !=3D 0 && a->rs2 =3D=3D 0) { + /* C.JR */ + arg_jalr arg =3D { .rd =3D 0, .rs1 =3D a->rd, .imm =3D 0 }; + return trans_jalr(ctx, &arg); + } else if (a->rd !=3D 0 && a->rs2 !=3D 0) { + /* C.MV */ + arg_add arg =3D { .rd =3D a->rd, .rs1 =3D 0, .rs2 =3D a->rs2 }; + return trans_add(ctx, &arg); + } + return false; +} + +static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_a= dd *a) +{ + if (a->rd =3D=3D 0 && a->rs2 =3D=3D 0) { + /* C.EBREAK */ + arg_ebreak arg =3D { }; + return trans_ebreak(ctx, &arg); + } else if (a->rd !=3D 0) { + if (a->rs2 =3D=3D 0) { + /* C.JALR */ + arg_jalr arg =3D { .rd =3D 1, .rs1 =3D a->rd, .imm =3D 0 }; + return trans_jalr(ctx, &arg); + } else { + /* C.ADD */ + arg_add arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->r= s2 }; + return trans_add(ctx, &arg); + } + } + return false; +} + +static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) +{ + arg_fsd arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_fsd(ctx, &arg); +} + +static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) +{ + arg_sw arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; + return trans_sw(ctx, &arg); +} + +static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) +{ +#ifdef TARGET_RISCV32 + /* C.FSWSP */ + arg_fsw a_fsw =3D { .rs1 =3D a->rs2, .rs2 =3D 2, .imm =3D a->uimm_fsws= p }; + return trans_fsw(ctx, &a_fsw); +#else + /* C.SDSP */ + arg_sd a_sd =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm_sdsp }; + return trans_sd(ctx, &a_sd); +#endif +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 498fbc20ef..53febc60b0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -614,6 +614,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, = int rs1, int rs2, tcg_temp_free(dat); } =20 +#ifdef TARGET_RISCV32 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -672,6 +673,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t op= c, int rs1, =20 tcg_temp_free(t0); } +#endif =20 static void gen_set_rm(DisasContext *ctx, int rm) { @@ -745,84 +747,6 @@ static void decode_RV32_64C0(DisasContext *ctx) } } =20 -static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx) -{ - uint8_t rd, rs2; - uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); - - - rd =3D GET_RD(ctx->opcode); - - switch (funct3) { - case 0: /* C.SLLI -> slli rd, rd, shamt[5:0] - C.SLLI64 -> */ - gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode)); - break; - case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */ - gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); - break; - case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */ - gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); - break; - case 3: -#if defined(TARGET_RISCV64) - /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */ - gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); -#else - /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */ - gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); -#endif - break; - case 4: - rs2 =3D GET_C_RS2(ctx->opcode); - - if (extract32(ctx->opcode, 12, 1) =3D=3D 0) { - if (rs2 =3D=3D 0) { - /* C.JR -> jalr x0, rs1, 0*/ - gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0); - } else { - /* C.MV -> add rd, x0, rs2 */ - gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2); - } - } else { - if (rd =3D=3D 0) { - /* C.EBREAK -> ebreak*/ - gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1); - } else { - if (rs2 =3D=3D 0) { - /* C.JALR -> jalr x1, rs1, 0*/ - gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0); - } else { - /* C.ADD -> add rd, rd, rs2 */ - gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2); - } - } - } - break; - case 5: - /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/ - gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode), - GET_C_SDSP_IMM(ctx->opcode)); - /* C.SQSP */ - break; - case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/ - gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode), - GET_C_SWSP_IMM(ctx->opcode)); - break; - case 7: -#if defined(TARGET_RISCV64) - /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/ - gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode), - GET_C_SDSP_IMM(ctx->opcode)); -#else - /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */ - gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode), - GET_C_SWSP_IMM(ctx->opcode)); -#endif - break; - } -} - static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) { uint8_t op =3D extract32(ctx->opcode, 0, 2); @@ -831,9 +755,6 @@ static void decode_RV32_64C(CPURISCVState *env, DisasCo= ntext *ctx) case 0: decode_RV32_64C0(ctx); break; - case 2: - decode_RV32_64C2(env, ctx); - break; } } =20 --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150288525585.4490117956955; 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Tue, 22 Jan 2019 09:30:09 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:54 +0100 Message-Id: <20190122092909.5341-21-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 20/35] target/riscv: Remove gen_jalr() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Alistair Francis , peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++- target/riscv/translate.c | 38 ------------------------- 2 files changed, 27 insertions(+), 39 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index b0f35cef14..3b3aff4803 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a) =20 static bool trans_jalr(DisasContext *ctx, arg_jalr *a) { - gen_jalr(ctx->env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); + /* no chaining with JALR */ + TCGLabel *misaligned =3D NULL; + TCGv t0 =3D tcg_temp_new(); + + + gen_get_gpr(cpu_pc, a->rs1); + tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm); + tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); + + if (!riscv_has_ext(ctx->env, RVC)) { + misaligned =3D gen_new_label(); + tcg_gen_andi_tl(t0, cpu_pc, 0x2); + tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); + } + + if (a->rd !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); + } + tcg_gen_lookup_and_goto_ptr(); + + if (misaligned) { + gen_set_label(misaligned); + gen_exception_inst_addr_mis(ctx); + } + ctx->base.is_jmp =3D DISAS_NORETURN; + + tcg_temp_free(t0); return true; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 53febc60b0..1f59b02c84 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -489,44 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *= ctx, int rd, ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs1, target_long imm) -{ - /* no chaining with JALR */ - TCGLabel *misaligned =3D NULL; - TCGv t0 =3D tcg_temp_new(); - - switch (opc) { - case OPC_RISC_JALR: - gen_get_gpr(cpu_pc, rs1); - tcg_gen_addi_tl(cpu_pc, cpu_pc, imm); - tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); - - if (!riscv_has_ext(env, RVC)) { - misaligned =3D gen_new_label(); - tcg_gen_andi_tl(t0, cpu_pc, 0x2); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); - } - - if (rd !=3D 0) { - tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); - } - tcg_gen_lookup_and_goto_ptr(); - - if (misaligned) { - gen_set_label(misaligned); - gen_exception_inst_addr_mis(ctx); - } - ctx->base.is_jmp =3D DISAS_NORETURN; - break; - - default: - gen_exception_illegal(ctx); - break; - } - tcg_temp_free(t0); -} - static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long bimm) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150586205324.3892689362908; Tue, 22 Jan 2019 01:49:46 -0800 (PST) Received: from localhost ([127.0.0.1]:41713 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsgi-0007G4-Qy for importer@patchew.org; Tue, 22 Jan 2019 04:49:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVW-0006AI-G6 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOP-0005pg-NV for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:51 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:53814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOP-0005OG-DA; Tue, 22 Jan 2019 04:30:49 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1glsNo-0004oY-Ki; Tue, 22 Jan 2019 10:30:12 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098399-2; Tue, 22 Jan 2019 09:30:11 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:55 +0100 Message-Id: <20190122092909.5341-22-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92416, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 21/35] target/riscv: Remove manual decoding from gen_branch() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++------- target/riscv/translate.c | 47 ------------------------- 2 files changed, 33 insertions(+), 60 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 3b3aff4803..0db1f79d20 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) return true; } =20 -static bool trans_beq(DisasContext *ctx, arg_beq *a) +static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { - gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + TCGLabel *l =3D gen_new_label(); + TCGv source1, source2; + source1 =3D tcg_temp_new(); + source2 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_brcond_tl(cond, source1, source2, l); + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(l); /* branch taken */ + + if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0= x3)) { + /* misaligned */ + gen_exception_inst_addr_mis(ctx); + } else { + gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); + } + ctx->base.is_jmp =3D DISAS_NORETURN; + + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; } =20 +static bool trans_beq(DisasContext *ctx, arg_beq *a) +{ + return gen_branch(ctx, a, TCG_COND_EQ); +} + static bool trans_bne(DisasContext *ctx, arg_bne *a) { - gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); - return true; + return gen_branch(ctx, a, TCG_COND_NE); } =20 static bool trans_blt(DisasContext *ctx, arg_blt *a) { - gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); - return true; + return gen_branch(ctx, a, TCG_COND_LT); } =20 static bool trans_bge(DisasContext *ctx, arg_bge *a) { - gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); - return true; + return gen_branch(ctx, a, TCG_COND_GE); } =20 static bool trans_bltu(DisasContext *ctx, arg_bltu *a) { - gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); - return true; + return gen_branch(ctx, a, TCG_COND_LTU); } =20 static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) { - - gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); - return true; + return gen_branch(ctx, a, TCG_COND_GEU); } =20 static bool trans_lb(DisasContext *ctx, arg_lb *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1f59b02c84..a0e96b94a9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *= ctx, int rd, ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rs1, int rs2, target_long bimm) -{ - TCGLabel *l =3D gen_new_label(); - TCGv source1, source2; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); - gen_get_gpr(source1, rs1); - gen_get_gpr(source2, rs2); - - switch (opc) { - case OPC_RISC_BEQ: - tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l); - break; - case OPC_RISC_BNE: - tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l); - break; - case OPC_RISC_BLT: - tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l); - break; - case OPC_RISC_BGE: - tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l); - break; - case OPC_RISC_BLTU: - tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l); - break; - case OPC_RISC_BGEU: - tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l); - break; - default: - gen_exception_illegal(ctx); - return; - } - tcg_temp_free(source1); - tcg_temp_free(source2); - - gen_goto_tb(ctx, 1, ctx->pc_succ_insn); - gen_set_label(l); /* branch taken */ - if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { - /* misaligned */ - gen_exception_inst_addr_mis(ctx); - } else { - gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm); - } - ctx->base.is_jmp =3D DISAS_NORETURN; -} - static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150572529625.0114289972282; Tue, 22 Jan 2019 01:49:32 -0800 (PST) Received: from localhost ([127.0.0.1]:41709 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsgV-000730-GU for importer@patchew.org; Tue, 22 Jan 2019 04:49:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59388) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVU-0006N0-D9 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOQ-0005tM-K8 for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:56 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:55038) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOP-0005P3-86; Tue, 22 Jan 2019 04:30:49 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1glsNp-0001to-5k; Tue, 22 Jan 2019 10:30:13 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098400-2; Tue, 22 Jan 2019 09:30:12 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:56 +0100 Message-Id: <20190122092909.5341-23-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92416, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 22/35] target/riscv: Remove manual decoding from gen_load() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++---------- target/riscv/translate.c | 6 +++-- 2 files changed, 25 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 0db1f79d20..1ad00bd776 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -129,34 +129,43 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) return gen_branch(ctx, a, TCG_COND_GEU); } =20 -static bool trans_lb(DisasContext *ctx, arg_lb *a) +static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop) { - gen_load(ctx, OPC_RISC_LB, a->rd, a->rs1, a->imm); + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); + gen_set_gpr(a->rd, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); return true; } =20 +static bool trans_lb(DisasContext *ctx, arg_lb *a) +{ + return gen_load(ctx, a, MO_SB); +} + static bool trans_lh(DisasContext *ctx, arg_lh *a) { - gen_load(ctx, OPC_RISC_LH, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESW); } =20 static bool trans_lw(DisasContext *ctx, arg_lw *a) { - gen_load(ctx, OPC_RISC_LW, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TESL); } =20 static bool trans_lbu(DisasContext *ctx, arg_lbu *a) { - gen_load(ctx, OPC_RISC_LBU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_UB); } =20 static bool trans_lhu(DisasContext *ctx, arg_lhu *a) { - gen_load(ctx, OPC_RISC_LHU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUW); } =20 static bool trans_sb(DisasContext *ctx, arg_sb *a) @@ -180,14 +189,12 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a) #ifdef TARGET_RISCV64 static bool trans_lwu(DisasContext *ctx, arg_lwu *a) { - gen_load(ctx, OPC_RISC_LWU, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEUL); } =20 static bool trans_ld(DisasContext *ctx, arg_ld *a) { - gen_load(ctx, OPC_RISC_LD, a->rd, a->rs1, a->imm); - return true; + return gen_load(ctx, a, MO_TEQ); } =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a0e96b94a9..d0fefa8fb9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -489,7 +489,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *c= tx, int rd, ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, +#ifdef TARGET_RISCV64 +static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { TCGv t0 =3D tcg_temp_new(); @@ -508,6 +509,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, i= nt rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } +#endif =20 static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) @@ -640,7 +642,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ - gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s, + gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, GET_C_LD_IMM(ctx->opcode)); #else /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150780748673.5121433614132; Tue, 22 Jan 2019 01:53:00 -0800 (PST) Received: from localhost ([127.0.0.1]:41789 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsjr-0001Gj-KA for importer@patchew.org; Tue, 22 Jan 2019 04:52:59 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVZ-00068S-1l for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsON-0005h8-7C for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:48 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60800) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsON-0005PW-0x; Tue, 22 Jan 2019 04:30:47 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1glsNr-0003Iu-NS; Tue, 22 Jan 2019 10:30:15 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100914-5; Tue, 22 Jan 2019 09:30:14 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:57 +0100 Message-Id: <20190122092909.5341-24-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 23/35] target/riscv: Remove manual decoding from gen_store() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.inc.c | 27 +++++++++++++++++-------- target/riscv/translate.c | 8 +++++--- 2 files changed, 24 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 1ad00bd776..da843b4e99 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -168,22 +168,34 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } =20 -static bool trans_sb(DisasContext *ctx, arg_sb *a) +static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) { - gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); + TCGv t0 =3D tcg_temp_new(); + TCGv dat =3D tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_addi_tl(t0, t0, a->imm); + gen_get_gpr(dat, a->rs2); + + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); + tcg_temp_free(t0); + tcg_temp_free(dat); return true; } =20 + +static bool trans_sb(DisasContext *ctx, arg_sb *a) +{ + return gen_store(ctx, a, MO_SB); +} + static bool trans_sh(DisasContext *ctx, arg_sh *a) { - gen_store(ctx, OPC_RISC_SH, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESW); } =20 static bool trans_sw(DisasContext *ctx, arg_sw *a) { - gen_store(ctx, OPC_RISC_SW, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TESL); } =20 #ifdef TARGET_RISCV64 @@ -199,8 +211,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a) =20 static bool trans_sd(DisasContext *ctx, arg_sd *a) { - gen_store(ctx, OPC_RISC_SD, a->rs1, a->rs2, a->imm); - return true; + return gen_store(ctx, a, MO_TEQ); } #endif =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0fefa8fb9..59452be191 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,6 +55,7 @@ typedef struct DisasContext { CPURISCVState *env; } DisasContext; =20 +#ifdef TARGET_RISCV64 /* convert riscv funct3 to qemu memop for load/store */ static const int tcg_memop_lookup[8] =3D { [0 ... 7] =3D -1, @@ -68,6 +69,7 @@ static const int tcg_memop_lookup[8] =3D { [6] =3D MO_TEUL, #endif }; +#endif =20 #ifdef TARGET_RISCV64 #define CASE_OP_32_64(X) case X: case glue(X, W) @@ -509,9 +511,8 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc,= int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } -#endif =20 -static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, +static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) { TCGv t0 =3D tcg_temp_new(); @@ -530,6 +531,7 @@ static void gen_store(DisasContext *ctx, uint32_t opc, = int rs1, int rs2, tcg_temp_free(t0); tcg_temp_free(dat); } +#endif =20 #ifdef TARGET_RISCV32 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, @@ -653,7 +655,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ - gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, + gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, GET_C_LD_IMM(ctx->opcode)); #else /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150962031533.871020945296; Tue, 22 Jan 2019 01:56:02 -0800 (PST) Received: from localhost ([127.0.0.1]:41851 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsmn-0003tj-0y for importer@patchew.org; Tue, 22 Jan 2019 04:56:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVY-00065q-Qr for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOP-0005o2-Dp for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:50 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:55050) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOP-0005QA-2z; Tue, 22 Jan 2019 04:30:49 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1glsNt-0001u2-3k; Tue, 22 Jan 2019 10:30:17 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069627-4; Tue, 22 Jan 2019 09:30:15 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:58 +0100 Message-Id: <20190122092909.5341-25-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Reviewed-by: Richard Henderson Tested-by: Alistair Francis --- v4 -> v5: - moved TARGET_LONG_BITS check of shift instructions before rd =3D=3D 0= check - removed extra sign extension of sraiw target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 98 +++++++++++++++++----- target/riscv/translate.c | 107 ++++++------------------ 3 files changed, 108 insertions(+), 100 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ecc46a50cc..d6b4197841 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -35,12 +35,13 @@ =20 # Argument sets: &b imm rs2 rs1 +&i imm rs1 rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 # Formats 32: @r ....... ..... ..... ... ..... ....... %rs2 %r= s1 %rd -@i ............ ..... ... ..... ....... imm=3D%imm_i = %rs1 %rd +@i ............ ..... ... ..... ....... &i imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index da843b4e99..dc6e395863 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -217,52 +217,96 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a) =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { - gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm); - return true; + return gen_arith_imm(ctx, a, &tcg_gen_add_tl); } =20 static bool trans_slti(DisasContext *ctx, arg_slti *a) { - gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm); + TCGv source1; + source1 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); return true; } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm); + TCGv source1; + source1 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); return true; } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) { - gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm); - return true; + return gen_arith_imm(ctx, a, &tcg_gen_xor_tl); } static bool trans_ori(DisasContext *ctx, arg_ori *a) { - gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm); - return true; + return gen_arith_imm(ctx, a, &tcg_gen_or_tl); } static bool trans_andi(DisasContext *ctx, arg_andi *a) { - gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm); - return true; + return gen_arith_imm(ctx, a, &tcg_gen_and_tl); } static bool trans_slli(DisasContext *ctx, arg_slli *a) { - gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt); + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + if (a->rd !=3D 0) { + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_shli_tl(t, t, a->shamt); + + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ return true; } =20 static bool trans_srli(DisasContext *ctx, arg_srli *a) { - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt); + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + if (a->rd !=3D 0) { + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_shri_tl(t, t, a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ return true; } =20 static bool trans_srai(DisasContext *ctx, arg_srai *a) { - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0= x400); + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + if (a->rd !=3D 0) { + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + + tcg_gen_sari_tl(t, t, a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + } /* NOP otherwise */ return true; } =20 @@ -329,26 +373,42 @@ static bool trans_and(DisasContext *ctx, arg_and *a) #ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { - gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm); - return true; + return gen_arith_imm(ctx, a, &gen_addw); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) { - gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt); + TCGv source1; + source1 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_shli_tl(source1, source1, a->shamt); + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + + tcg_temp_free(source1); return true; } =20 static bool trans_srliw(DisasContext *ctx, arg_srliw *a) { - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt); + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt); + /* sign-extend for W instructions */ + tcg_gen_ext32s_tl(t, t); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); return true; } =20 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a) { - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1, - a->shamt | 0x400); + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); return true; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 59452be191..55b10fdd64 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -390,86 +390,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, tcg_temp_free(source2); } =20 -static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd, - int rs1, target_long imm) -{ - TCGv source1 =3D tcg_temp_new(); - int shift_len =3D TARGET_LONG_BITS; - int shift_a; - - gen_get_gpr(source1, rs1); - - switch (opc) { - case OPC_RISC_ADDI: -#if defined(TARGET_RISCV64) - case OPC_RISC_ADDIW: -#endif - tcg_gen_addi_tl(source1, source1, imm); - break; - case OPC_RISC_SLTI: - tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm); - break; - case OPC_RISC_SLTIU: - tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm); - break; - case OPC_RISC_XORI: - tcg_gen_xori_tl(source1, source1, imm); - break; - case OPC_RISC_ORI: - tcg_gen_ori_tl(source1, source1, imm); - break; - case OPC_RISC_ANDI: - tcg_gen_andi_tl(source1, source1, imm); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SLLIW: - shift_len =3D 32; - /* FALLTHRU */ -#endif - case OPC_RISC_SLLI: - if (imm >=3D shift_len) { - goto do_illegal; - } - tcg_gen_shli_tl(source1, source1, imm); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SHIFT_RIGHT_IW: - shift_len =3D 32; - /* FALLTHRU */ -#endif - case OPC_RISC_SHIFT_RIGHT_I: - /* differentiate on IMM */ - shift_a =3D imm & 0x400; - imm &=3D 0x3ff; - if (imm >=3D shift_len) { - goto do_illegal; - } - if (imm !=3D 0) { - if (shift_a) { - /* SRAI[W] */ - tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm= ); - } else { - /* SRLI[W] */ - tcg_gen_extract_tl(source1, source1, imm, shift_len - imm); - } - /* No further sign-extension needed for W instructions. */ - opc &=3D ~0x8; - } - break; - default: - do_illegal: - gen_exception_illegal(ctx); - return; - } - - if (opc & 0x8) { /* sign-extend for W instructions */ - tcg_gen_ext32s_tl(source1, source1); - } - - gen_set_gpr(rd, source1); - tcg_temp_free(source1); -} - static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, target_ulong imm) { @@ -696,6 +616,33 @@ static int ex_rvc_register(int reg) bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" + +static bool gen_arith_imm(DisasContext *ctx, arg_i *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 =3D tcg_temp_new(); + source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->imm); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +#ifdef TARGET_RISCV64 +static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_add_tl(ret, arg1, arg2); + tcg_gen_ext32s_tl(ret, ret); +} +#endif + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 22 Jan 2019 10:30:18 +0100 Received: from mail.uni-paderborn.de by magmaria with queue id 3095054-3; Tue, 22 Jan 2019 09:30:17 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:28:59 +0100 Message-Id: <20190122092909.5341-26-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvi.inc.c | 21 +++++-------- target/riscv/translate.c | 40 +++++++++++++++---------- 3 files changed, 34 insertions(+), 30 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d6b4197841..6f3ab7aa52 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -36,11 +36,12 @@ # Argument sets: &b imm rs2 rs1 &i imm rs1 rd +&r rd rs1 rs2 &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 # Formats 32: -@r ....... ..... ..... ... ..... ....... %rs2 %r= s1 %rd +@r ....... ..... ..... ... ..... ....... &r %rs2 %r= s1 %rd @i ............ ..... ... ..... ....... &i imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index dc6e395863..f52182e9f4 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) =20 static bool trans_add(DisasContext *ctx, arg_add *a) { - gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_add_tl); } =20 static bool trans_sub(DisasContext *ctx, arg_sub *a) { - gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_sub_tl); } =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a) =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) { - gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_xor_tl); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) =20 static bool trans_or(DisasContext *ctx, arg_or *a) { - gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_or_tl); } =20 static bool trans_and(DisasContext *ctx, arg_and *a) { - gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_and_tl); } =20 #ifdef TARGET_RISCV64 @@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { - gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { - gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 55b10fdd64..f691cbcd80 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -192,12 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, gen_get_gpr(source2, rs2); =20 switch (opc) { - CASE_OP_32_64(OPC_RISC_ADD): - tcg_gen_add_tl(source1, source1, source2); - break; - CASE_OP_32_64(OPC_RISC_SUB): - tcg_gen_sub_tl(source1, source1, source2); - break; #if defined(TARGET_RISCV64) case OPC_RISC_SLLW: tcg_gen_andi_tl(source2, source2, 0x1F); @@ -214,9 +208,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, = int rd, int rs1, case OPC_RISC_SLTU: tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2); break; - case OPC_RISC_XOR: - tcg_gen_xor_tl(source1, source1, source2); - break; #if defined(TARGET_RISCV64) case OPC_RISC_SRLW: /* clear upper 32 */ @@ -242,12 +233,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); tcg_gen_sar_tl(source1, source1, source2); break; - case OPC_RISC_OR: - tcg_gen_or_tl(source1, source1, source2); - break; - case OPC_RISC_AND: - tcg_gen_and_tl(source1, source1, source2); - break; CASE_OP_32_64(OPC_RISC_MUL): tcg_gen_mul_tl(source1, source1, source2); break; @@ -641,8 +626,33 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_add_tl(ret, arg1, arg2); tcg_gen_ext32s_tl(ret, ret); } + +static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_sub_tl(ret, arg1, arg2); + tcg_gen_ext32s_tl(ret, ret); +} + #endif =20 +static bool trans_arith(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 =3D tcg_temp_new(); + source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 22 Jan 2019 10:30:19 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098401-2; Tue, 22 Jan 2019 09:30:18 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:00 +0100 Message-Id: <20190122092909.5341-27-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92416, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 26/35] target/riscv: Remove shift and slt insn manual decoding X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- v4 -> v5: - removed rs2 =3D=3D 0 special cases in sraw/srlw target/riscv/insn_trans/trans_rvi.inc.c | 93 +++++++++++++++++-------- target/riscv/translate.c | 59 +++++----------- 2 files changed, 81 insertions(+), 71 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index f52182e9f4..3badb70b1d 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a) return gen_arith_imm(ctx, a, &tcg_gen_add_tl); } =20 -static bool trans_slti(DisasContext *ctx, arg_slti *a) +static void gen_slt(TCGv ret, TCGv s1, TCGv s2) { - TCGv source1; - source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); + tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2); +} + +static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2); +} =20 - tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm); =20 - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - return true; +static bool trans_slti(DisasContext *ctx, arg_slti *a) +{ + return gen_arith_imm(ctx, a, &gen_slt); } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - TCGv source1; - source1 =3D tcg_temp_new(); - gen_get_gpr(source1, a->rs1); - - tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm); - - gen_set_gpr(a->rd, source1); - tcg_temp_free(source1); - return true; + return gen_arith_imm(ctx, a, &gen_sltu); } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) @@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a) =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) { - gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shl_tl); } =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) { - gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_slt); } =20 static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_sltu); } =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) @@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a) =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) { - gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shr_tl); } =20 static bool trans_sra(DisasContext *ctx, arg_sra *a) { - gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_sar_tl); } =20 static bool trans_or(DisasContext *ctx, arg_or *a) @@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { - gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shl_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { - gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* clear upper 32 */ + tcg_gen_ext32u_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_shr_tl(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { - gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + /* + * first, trick to get it to act like working on 32 bits (get rid of + * upper 32, sign extend to fill space) + */ + tcg_gen_ext32s_tl(source1, source1); + tcg_gen_andi_tl(source2, source2, 0x1F); + tcg_gen_sar_tl(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f691cbcd80..442c7d26a3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -192,47 +192,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,= int rd, int rs1, gen_get_gpr(source2, rs2); =20 switch (opc) { -#if defined(TARGET_RISCV64) - case OPC_RISC_SLLW: - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shl_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SLL: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shl_tl(source1, source1, source2); - break; - case OPC_RISC_SLT: - tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2); - break; - case OPC_RISC_SLTU: - tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRLW: - /* clear upper 32 */ - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_shr_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SRL: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shr_tl(source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRAW: - /* first, trick to get it to act like working on 32 bits (get rid = of - upper 32, sign extend to fill space) */ - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_andi_tl(source2, source2, 0x1F); - tcg_gen_sar_tl(source1, source1, source2); - break; -#endif - case OPC_RISC_SRA: - tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_sar_tl(source1, source1, source2); - break; CASE_OP_32_64(OPC_RISC_MUL): tcg_gen_mul_tl(source1, source1, source2); break; @@ -653,6 +612,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a, return true; } =20 +static bool gen_shift(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c" --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 27/35] target/riscv: Remove manual decoding of RV32/64M insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvm.inc.c | 55 +++-- target/riscv/translate.c | 283 +++++++++++------------- 2 files changed, 164 insertions(+), 174 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_tr= ans/trans_rvm.inc.c index ec3197ede8..949f59ddb2 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -21,80 +21,87 @@ =20 static bool trans_mul(DisasContext *ctx, arg_mul *a) { - gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &tcg_gen_mul_tl); } =20 static bool trans_mulh(DisasContext *ctx, arg_mulh *a) { - gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_muls2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { - gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_mulhsu); } =20 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) { - gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2); + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_mulu2_tl(source2, source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); return true; } =20 static bool trans_div(DisasContext *ctx, arg_div *a) { - gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_div); } =20 static bool trans_divu(DisasContext *ctx, arg_divu *a) { - gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_divu); } =20 static bool trans_rem(DisasContext *ctx, arg_rem *a) { - gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_rem); } =20 static bool trans_remu(DisasContext *ctx, arg_remu *a) { - gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_remu); } =20 #ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { - gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_mulw); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) { - gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2); - return true; + return gen_arith_div_w(ctx, a, &gen_div); } =20 static bool trans_divuw(DisasContext *ctx, arg_divuw *a) { - gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2); - return true; + return gen_arith_div_w(ctx, a, &gen_divu); } =20 static bool trans_remw(DisasContext *ctx, arg_remw *a) { - gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2); - return true; + return gen_arith_div_w(ctx, a, &gen_rem); } =20 static bool trans_remuw(DisasContext *ctx, arg_remuw *a) { - gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2); - return true; + return gen_arith_div_w(ctx, a, &gen_remu); } #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 442c7d26a3..6a722a0045 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -182,156 +182,112 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv ar= g2) tcg_temp_free(rh); } =20 -static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, - int rs2) -{ - TCGv source1, source2, cond1, cond2, zeroreg, resultopt1; - source1 =3D tcg_temp_new(); - source2 =3D tcg_temp_new(); - gen_get_gpr(source1, rs1); - gen_get_gpr(source2, rs2); - - switch (opc) { - CASE_OP_32_64(OPC_RISC_MUL): - tcg_gen_mul_tl(source1, source1, source2); - break; - case OPC_RISC_MULH: - tcg_gen_muls2_tl(source2, source1, source1, source2); - break; - case OPC_RISC_MULHSU: - gen_mulhsu(source1, source1, source2); - break; - case OPC_RISC_MULHU: - tcg_gen_mulu2_tl(source2, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_DIVW: - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_ext32s_tl(source2, source2); - /* fall through to DIV */ -#endif - case OPC_RISC_DIV: - /* Handle by altering args to tcg_gen_div to produce req'd results: - * For overflow: want source1 in source1 and 1 in source2 - * For div by zero: want -1 in source1 and 1 in source2 -> -1 resu= lt */ - cond1 =3D tcg_temp_new(); - cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0= L)); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - ((target_ulong)1) << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 =3D overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 =3D = div 0 */ - /* if div by zero, set source1 to -1, otherwise don't change */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, - resultopt1); - /* if overflow or div by zero, set source2 to 1, else don't change= */ - tcg_gen_or_tl(cond1, cond1, cond2); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_div_tl(source1, source1, source2); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_DIVUW: - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_ext32u_tl(source2, source2); - /* fall through to DIVU */ -#endif - case OPC_RISC_DIVU: - cond1 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movi_tl(resultopt1, (target_ulong)-1); - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, - resultopt1); - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_divu_tl(source1, source1, source2); - - tcg_temp_free(cond1); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_REMW: - tcg_gen_ext32s_tl(source1, source1); - tcg_gen_ext32s_tl(source2, source2); - /* fall through to REM */ -#endif - case OPC_RISC_REM: - cond1 =3D tcg_temp_new(); - cond2 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, 1L); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, - (target_ulong)1 << (TARGET_LONG_BITS - 1)); - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 =3D overflow */ - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 =3D = div 0 */ - /* if overflow or div by zero, set source2 to 1, else don't change= */ - tcg_gen_or_tl(cond2, cond1, cond2); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, - resultopt1); - tcg_gen_rem_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt= 1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(cond2); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_REMUW: - tcg_gen_ext32u_tl(source1, source1); - tcg_gen_ext32u_tl(source2, source2); - /* fall through to REMU */ -#endif - case OPC_RISC_REMU: - cond1 =3D tcg_temp_new(); - zeroreg =3D tcg_const_tl(0); - resultopt1 =3D tcg_temp_new(); - - tcg_gen_movi_tl(resultopt1, (target_ulong)1); - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, - resultopt1); - tcg_gen_remu_tl(resultopt1, source1, source2); - /* if div by zero, just return the original dividend */ - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, resultopt= 1, - source1); - - tcg_temp_free(cond1); - tcg_temp_free(zeroreg); - tcg_temp_free(resultopt1); - break; - default: - gen_exception_illegal(ctx); - return; - } - - if (opc & 0x8) { /* sign extend for W instructions */ - tcg_gen_ext32s_tl(source1, source1); - } - - gen_set_gpr(rd, source1); - tcg_temp_free(source1); - tcg_temp_free(source2); +static void gen_div(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, cond2, zeroreg, resultopt1; + /* + * Handle by altering args to tcg_gen_div to produce req'd results: + * For overflow: want source1 in source1 and 1 in source2 + * For div by zero: want -1 in source1 and 1 in source2 -> -1 result + */ + cond1 =3D tcg_temp_new(); + cond2 =3D tcg_temp_new(); + zeroreg =3D tcg_const_tl(0); + resultopt1 =3D tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, (target_ulong)-1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + ((target_ulong)1) << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 =3D overflow */ + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 =3D div = 0 */ + /* if div by zero, set source1 to -1, otherwise don't change */ + tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, + resultopt1); + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(cond1, cond1, cond2); + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_div_tl(ret, source1, source2); + + tcg_temp_free(cond1); + tcg_temp_free(cond2); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} + +static void gen_divu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, zeroreg, resultopt1; + cond1 =3D tcg_temp_new(); + + zeroreg =3D tcg_const_tl(0); + resultopt1 =3D tcg_temp_new(); + + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movi_tl(resultopt1, (target_ulong)-1); + tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, + resultopt1); + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_divu_tl(ret, source1, source2); + + tcg_temp_free(cond1); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} + +static void gen_rem(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, cond2, zeroreg, resultopt1; + + cond1 =3D tcg_temp_new(); + cond2 =3D tcg_temp_new(); + zeroreg =3D tcg_const_tl(0); + resultopt1 =3D tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, 1L); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, + (target_ulong)1 << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 =3D overflow */ + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 =3D div = 0 */ + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(cond2, cond1, cond2); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, + resultopt1); + tcg_gen_rem_tl(resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(cond1); + tcg_temp_free(cond2); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); +} + +static void gen_remu(TCGv ret, TCGv source1, TCGv source2) +{ + TCGv cond1, zeroreg, resultopt1; + cond1 =3D tcg_temp_new(); + zeroreg =3D tcg_const_tl(0); + resultopt1 =3D tcg_temp_new(); + + tcg_gen_movi_tl(resultopt1, (target_ulong)1); + tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_remu_tl(resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(cond1); + tcg_temp_free(zeroreg); + tcg_temp_free(resultopt1); } =20 static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, @@ -592,6 +548,33 @@ static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_ext32s_tl(ret, ret); } =20 +static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_mul_tl(ret, arg1, arg2); + tcg_gen_ext32s_tl(ret, ret); +} + +static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1, source2; + source1 =3D tcg_temp_new(); + source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + tcg_gen_ext32s_tl(source1, source1); + tcg_gen_ext32s_tl(source2, source2); + + (*func)(source1, source1, source2); + + tcg_gen_ext32s_tl(source1, source1); + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + #endif =20 static bool trans_arith(DisasContext *ctx, arg_r *a, --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154815008440510.381328535443686; Tue, 22 Jan 2019 01:41:24 -0800 (PST) Received: from localhost ([127.0.0.1]:41577 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsYd-0000aI-A8 for importer@patchew.org; Tue, 22 Jan 2019 04:41:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVL-00065q-SA for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOZ-00061Q-CO for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:31:00 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60944) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOZ-0005SM-28; Tue, 22 Jan 2019 04:30:59 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1glsNz-0006Ds-6V; Tue, 22 Jan 2019 10:30:23 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100916-5; Tue, 22 Jan 2019 09:30:21 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:02 +0100 Message-Id: <20190122092909.5341-29-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 28/35] target/riscv: Rename trans_arith to gen_arith X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++--------- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++------- target/riscv/translate.c | 4 ++-- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index 3badb70b1d..5a09ee556f 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a) =20 static bool trans_add(DisasContext *ctx, arg_add *a) { - return trans_arith(ctx, a, &tcg_gen_add_tl); + return gen_arith(ctx, a, &tcg_gen_add_tl); } =20 static bool trans_sub(DisasContext *ctx, arg_sub *a) { - return trans_arith(ctx, a, &tcg_gen_sub_tl); + return gen_arith(ctx, a, &tcg_gen_sub_tl); } =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a) =20 static bool trans_slt(DisasContext *ctx, arg_slt *a) { - return trans_arith(ctx, a, &gen_slt); + return gen_arith(ctx, a, &gen_slt); } =20 static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - return trans_arith(ctx, a, &gen_sltu); + return gen_arith(ctx, a, &gen_sltu); } =20 static bool trans_xor(DisasContext *ctx, arg_xor *a) { - return trans_arith(ctx, a, &tcg_gen_xor_tl); + return gen_arith(ctx, a, &tcg_gen_xor_tl); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a) =20 static bool trans_or(DisasContext *ctx, arg_or *a) { - return trans_arith(ctx, a, &tcg_gen_or_tl); + return gen_arith(ctx, a, &tcg_gen_or_tl); } =20 static bool trans_and(DisasContext *ctx, arg_and *a) { - return trans_arith(ctx, a, &tcg_gen_and_tl); + return gen_arith(ctx, a, &tcg_gen_and_tl); } =20 #ifdef TARGET_RISCV64 @@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw = *a) =20 static bool trans_addw(DisasContext *ctx, arg_addw *a) { - return trans_arith(ctx, a, &gen_addw); + return gen_arith(ctx, a, &gen_addw); } =20 static bool trans_subw(DisasContext *ctx, arg_subw *a) { - return trans_arith(ctx, a, &gen_subw); + return gen_arith(ctx, a, &gen_subw); } =20 static bool trans_sllw(DisasContext *ctx, arg_sllw *a) diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_tr= ans/trans_rvm.inc.c index 949f59ddb2..5844d6f5be 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.inc.c @@ -21,7 +21,7 @@ =20 static bool trans_mul(DisasContext *ctx, arg_mul *a) { - return trans_arith(ctx, a, &tcg_gen_mul_tl); + return gen_arith(ctx, a, &tcg_gen_mul_tl); } =20 static bool trans_mulh(DisasContext *ctx, arg_mulh *a) @@ -41,7 +41,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a) =20 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a) { - return trans_arith(ctx, a, &gen_mulhsu); + return gen_arith(ctx, a, &gen_mulhsu); } =20 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -61,28 +61,28 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) =20 static bool trans_div(DisasContext *ctx, arg_div *a) { - return trans_arith(ctx, a, &gen_div); + return gen_arith(ctx, a, &gen_div); } =20 static bool trans_divu(DisasContext *ctx, arg_divu *a) { - return trans_arith(ctx, a, &gen_divu); + return gen_arith(ctx, a, &gen_divu); } =20 static bool trans_rem(DisasContext *ctx, arg_rem *a) { - return trans_arith(ctx, a, &gen_rem); + return gen_arith(ctx, a, &gen_rem); } =20 static bool trans_remu(DisasContext *ctx, arg_remu *a) { - return trans_arith(ctx, a, &gen_remu); + return gen_arith(ctx, a, &gen_remu); } =20 #ifdef TARGET_RISCV64 static bool trans_mulw(DisasContext *ctx, arg_mulw *a) { - return trans_arith(ctx, a, &gen_mulw); + return gen_arith(ctx, a, &gen_mulw); } =20 static bool trans_divw(DisasContext *ctx, arg_divw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6a722a0045..d0b0fca12b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -577,8 +577,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, =20 #endif =20 -static bool trans_arith(DisasContext *ctx, arg_r *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; source1 =3D tcg_temp_new(); --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Tue, 22 Jan 2019 04:30:51 -0500 Received: from tweenies.uni-paderborn.de ([131.234.189.21] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 telepax) id 1glsO0-0001uT-3s; Tue, 22 Jan 2019 10:30:24 +0100 Received: from mail.uni-paderborn.de by tweenies with queue id 3069628-4; Tue, 22 Jan 2019 09:30:23 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:03 +0100 Message-Id: <20190122092909.5341-30-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 29/35] target/riscv: Remove gen_system() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/translate.c | 31 ------------------------------- 1 file changed, 31 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0b0fca12b..0e37beb68e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -427,32 +427,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } =20 -static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, - int rd, int rs1, int csr) -{ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - - switch (opc) { - case OPC_RISC_ECALL: - switch (csr) { - case 0x0: /* ECALL */ - /* always generates U-level ECALL, fixed in do_interrupt handl= er */ - generate_exception(ctx, RISCV_EXCP_U_ECALL); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp =3D DISAS_NORETURN; - break; - case 0x1: /* EBREAK */ - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp =3D DISAS_NORETURN; - break; - default: - gen_exception_illegal(ctx); - break; - } - break; - } -} =20 static void decode_RV32_64C0(DisasContext *ctx) { @@ -628,7 +602,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); =20 static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { - int rs1, rd; uint32_t op; =20 /* We do not do misaligned address check here: the address should neve= r be @@ -637,13 +610,9 @@ static void decode_RV32_64G(CPURISCVState *env, DisasC= ontext *ctx) * perform the misaligned instruction fetch */ =20 op =3D MASK_OP_MAJOR(ctx->opcode); - rs1 =3D GET_RS1(ctx->opcode); - rd =3D GET_RD(ctx->opcode); =20 switch (op) { case OPC_RISC_SYSTEM: - gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, - (ctx->opcode & 0xFFF00000) >> 20); break; default: gen_exception_illegal(ctx); --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150208147370.9334710792134; Tue, 22 Jan 2019 01:43:28 -0800 (PST) Received: from localhost ([127.0.0.1]:41611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsad-00028n-54 for importer@patchew.org; Tue, 22 Jan 2019 04:43:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVU-0006AI-Dm for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOV-0005z4-Be for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:56 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOV-0005Ti-5b; Tue, 22 Jan 2019 04:30:55 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 amazonia) id 1glsO1-0006EA-8q; Tue, 22 Jan 2019 10:30:25 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100917-5; Tue, 22 Jan 2019 09:30:24 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:04 +0100 Message-Id: <20190122092909.5341-31-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 30/35] target/riscv: Remove decode_RV32_64G() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Tested-by: Alistair Francis --- target/riscv/translate.c | 23 +---------------------- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0e37beb68e..b0251b3518 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -600,26 +600,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" =20 -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) -{ - uint32_t op; - - /* We do not do misaligned address check here: the address should neve= r be - * misaligned at this point. Instructions that set PC must do the chec= k, - * since epc must be the address of the instruction that caused us to - * perform the misaligned instruction fetch */ - - op =3D MASK_OP_MAJOR(ctx->opcode); - - switch (op) { - case OPC_RISC_SYSTEM: - break; - default: - gen_exception_illegal(ctx); - break; - } -} - static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ @@ -636,8 +616,7 @@ static void decode_opc(DisasContext *ctx) } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; if (!decode_insn32(ctx, ctx->opcode)) { - /* fallback to old decoder */ - decode_RV32_64G(ctx->env, ctx); + gen_exception_illegal(ctx); } } } --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150028406633.1977044820741; Tue, 22 Jan 2019 01:40:28 -0800 (PST) Received: from localhost ([127.0.0.1]:41543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsXc-000867-Bs for importer@patchew.org; Tue, 22 Jan 2019 04:40:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVN-00065q-PT for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:38:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOX-00060V-2Z for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:30:59 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:41962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOV-0005UN-5z; Tue, 22 Jan 2019 04:30:55 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 spheron) id 1glsO3-0004Kr-GQ; Tue, 22 Jan 2019 10:30:27 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098403-2; Tue, 22 Jan 2019 09:30:25 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:05 +0100 Message-Id: <20190122092909.5341-32-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92416, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 31/35] target/riscv: Convert @cs_2 insns to share translation functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" These all expand simply to R format instructions. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/Makefile.objs | 10 +++--- target/riscv/insn16-64.decode | 24 ++++++++++++++ target/riscv/insn16.decode | 15 +++++---- target/riscv/insn_trans/trans_rvc.inc.c | 44 ------------------------- target/riscv/translate.c | 20 ++++++++--- 5 files changed, 54 insertions(+), 59 deletions(-) create mode 100644 target/riscv/insn16-64.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 9c6c109327..990bd89016 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -5,16 +5,18 @@ DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py decode32-y =3D $(SRC_PATH)/target/riscv/insn32.decode decode32-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn32-64.decode =20 +decode16-y =3D $(SRC_PATH)/target/riscv/insn16.decode +decode16-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn16-64.decode + target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ "GEN", $(TARGET_DIR)$@) =20 -target/riscv/decode_insn16.inc.c: \ - $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<,= \ - "GEN", $(TARGET_DIR)$@) + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 \ + $(decode16-y), "GEN", $(TARGET_DIR)$@) =20 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode new file mode 100644 index 0000000000..5af2e2b072 --- /dev/null +++ b/target/riscv/insn16-64.decode @@ -0,0 +1,24 @@ +# +# RISC-V translation routines for the RVC Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# This is concatenated with insn16.decode for risc64 targets. +# All of the fields and formats are there. + +# *** RV64C Standard Extension (Quadrant 1) *** +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 0829e3bc59..c7a58d80e5 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -41,6 +41,9 @@ =20 =20 =20 +# Argument sets imported from insn32.decode: +&r rd rs1 rs2 !extern + # Argument sets: &cl rs1 rd &cl_dw uimm rs1 rd @@ -68,7 +71,7 @@ @cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 @cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 -@cs_2 ... ... ... .. ... .. &cr rd=3D%rs1_3 rs= 2=3D%rs2_3 +@cs_2 ... ... ... .. ... .. &r rd=3D%rs1_3 rs1=3D%rs1_3 rs2=3D%r= s2_3 @cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 @cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 @@ -107,12 +110,10 @@ c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_= lui # shares opc with C.LUI c_srli 100 . 00 ... ..... 01 @c_shift c_srai 100 . 01 ... ..... 01 @c_shift c_andi 100 . 10 ... ..... 01 @c_andi -c_sub 100 0 11 ... 00 ... 01 @cs_2 -c_xor 100 0 11 ... 01 ... 01 @cs_2 -c_or 100 0 11 ... 10 ... 01 @cs_2 -c_and 100 0 11 ... 11 ... 01 @cs_2 -c_subw 100 1 11 ... 00 ... 01 @cs_2 -c_addw 100 1 11 ... 01 ... 01 @cs_2 +sub 100 0 11 ... 00 ... 01 @cs_2 +xor 100 0 11 ... 01 ... 01 @cs_2 +or 100 0 11 ... 10 ... 01 @cs_2 +and 100 0 11 ... 11 ... 01 @cs_2 c_j 101 ........... 01 @cj c_beqz 110 ... ... ..... 01 @cb c_bnez 111 ... ... ..... 01 @cb diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index bcdf64d3b7..639c381edf 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -163,50 +163,6 @@ static bool trans_c_andi(DisasContext *ctx, arg_c_andi= *a) return trans_andi(ctx, &arg); } =20 -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) -{ - arg_sub arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_sub(ctx, &arg); -} - -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) -{ - arg_xor arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_xor(ctx, &arg); -} - -static bool trans_c_or(DisasContext *ctx, arg_c_or *a) -{ - arg_or arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_or(ctx, &arg); -} - -static bool trans_c_and(DisasContext *ctx, arg_c_and *a) -{ - arg_and arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_and(ctx, &arg); -} - -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) -{ -#ifdef TARGET_RISCV64 - arg_subw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_subw(ctx, &arg); -#else - return false; -#endif -} - -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) -{ -#ifdef TARGET_RISCV64 - arg_addw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_addw(ctx, &arg); -#else - return false; -#endif -} - static bool trans_c_j(DisasContext *ctx, arg_c_j *a) { arg_jal arg =3D { .rd =3D 0, .imm =3D a->imm }; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b0251b3518..5079c68b18 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -487,10 +487,25 @@ static int ex_rvc_register(int reg) return 8 + reg; } =20 +/* + * Include the auto-generated decoders. + * Note that the 16-bit decoder reuses some of the trans_* functions + * from the 32-bit decoder, which results in duplicate declarations + * of the relevant helpers. Suppress the warning. + */ bool decode_insn32(DisasContext *ctx, uint32_t insn); -/* Include the auto-generated decoder for 32 bit insn */ +bool decode_insn16(DisasContext *ctx, uint16_t insn); + #include "decode_insn32.inc.c" =20 +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" + +#include "decode_insn16.inc.c" + +#pragma GCC diagnostic pop + + static bool gen_arith_imm(DisasContext *ctx, arg_i *a, void(*func)(TCGv, TCGv, TCGv)) { @@ -595,9 +610,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 -bool decode_insn16(DisasContext *ctx, uint16_t insn); -/* auto-generated decoder*/ -#include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" =20 static void decode_opc(DisasContext *ctx) --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150196803988.1200341484828; Tue, 22 Jan 2019 01:43:16 -0800 (PST) Received: from localhost ([127.0.0.1]:41607 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsaR-00020e-ML for importer@patchew.org; Tue, 22 Jan 2019 04:43:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:58893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVJ-00065q-QU for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:37:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOY-00060t-1C for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:31:03 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:54012) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOX-0005XU-OU; Tue, 22 Jan 2019 04:30:57 -0500 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1glsO4-0004ru-Ke; Tue, 22 Jan 2019 10:30:28 +0100 Received: from mail.uni-paderborn.de by wormulon with queue id 3100918-5; Tue, 22 Jan 2019 09:30:27 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:06 +0100 Message-Id: <20190122092909.5341-33-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/insn16.decode | 20 ++++++++++---------- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvc.inc.c | 24 ------------------------ 3 files changed, 12 insertions(+), 35 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index c7a58d80e5..c215867ff9 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -43,14 +43,14 @@ =20 # Argument sets imported from insn32.decode: &r rd rs1 rs2 !extern +&i imm rs1 rd !extern +&s imm rs1 rs2 !extern =20 # Argument sets: &cl rs1 rd -&cl_dw uimm rs1 rd &ci imm rd &ciw nzuimm rd &cs rs1 rs2 -&cs_dw uimm rs1 rs2 &cb imm rs1 &cr rd rs2 &c_j imm @@ -67,13 +67,13 @@ @cr .... ..... ..... .. &cr rs2=3D%rs2_5 %rd @ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 -@cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 -@cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 rd=3D= %rs2_3 +@cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 rd=3D= %rs2_3 @cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 @cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 @cs_2 ... ... ... .. ... .. &r rd=3D%rs1_3 rs1=3D%rs1_3 rs2=3D%r= s2_3 -@cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 -@cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 rs2= =3D%rs2_3 +@cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 rs2= =3D%rs2_3 @cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 @cj ... ........... .. &c_j imm=3D%imm_cj =20 @@ -95,11 +95,11 @@ =20 # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw -c_fld 001 ... ... .. ... 00 @cl_d -c_lw 010 ... ... .. ... 00 @cl_w +fld 001 ... ... .. ... 00 @cl_d +lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually -c_fsd 101 ... ... .. ... 00 @cs_d -c_sw 110 ... ... .. ... 00 @cs_w +fsd 101 ... ... .. ... 00 @cs_d +sw 110 ... ... .. ... 00 @cs_w c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually =20 # *** RV64C Standard Extension (Quadrant 1) *** diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f3ab7aa52..b59a00cc42 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -37,6 +37,7 @@ &b imm rs2 rs1 &i imm rs1 rd &r rd rs1 rs2 +&s imm rs2 rs1 &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 @@ -44,7 +45,7 @@ @r ....... ..... ..... ... ..... ....... &r %rs2 %r= s1 %rd @i ............ ..... ... ..... ....... &i imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 -@s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 +@s ....... ..... ..... ... ..... ....... &s imm=3D%imm_s %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd @j .................... ..... ....... imm=3D%imm_j = %rd =20 diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index 639c381edf..d932bfd3e0 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_ad= di4spn *a) return trans_addi(ctx, &arg); } =20 -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) -{ - arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) -{ - arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -51,18 +39,6 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_= ld *a) #endif } =20 -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) -{ - arg_fsd arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) -{ - arg_sw arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) { #ifdef TARGET_RISCV32 --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Tue, 22 Jan 2019 04:30:58 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:60842) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1glsOV-0005Yk-4Q; Tue, 22 Jan 2019 04:30:55 -0500 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 nylar) id 1glsO5-0003Ju-P6; Tue, 22 Jan 2019 10:30:29 +0100 Received: from mail.uni-paderborn.de by pova with queue id 3098404-2; Tue, 22 Jan 2019 09:30:28 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:07 +0100 Message-Id: <20190122092909.5341-34-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92416, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" this finally removes the old decoder functions that we carried along with it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/Makefile.objs | 1 + target/riscv/insn16-32.decode | 24 ++++ target/riscv/insn16-64.decode | 4 + target/riscv/insn16.decode | 7 +- target/riscv/insn_trans/trans_rvc.inc.c | 22 ---- target/riscv/translate.c | 165 +----------------------- 6 files changed, 31 insertions(+), 192 deletions(-) create mode 100644 target/riscv/insn16-32.decode diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 990bd89016..a31a9ea061 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -6,6 +6,7 @@ decode32-y =3D $(SRC_PATH)/target/riscv/insn32.decode decode32-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn32-64.decode =20 decode16-y =3D $(SRC_PATH)/target/riscv/insn16.decode +decode16-$(TARGET_RISCV32) +=3D $(SRC_PATH)/target/riscv/insn16-32.decode decode16-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn16-64.decode =20 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode new file mode 100644 index 0000000000..e21a701056 --- /dev/null +++ b/target/riscv/insn16-32.decode @@ -0,0 +1,24 @@ +# +# RISC-V translation routines for the RVC Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# This is concatenated with insn16.decode for risc32 targets. +# All of the fields and formats are there. + +# *** RV32C Standard Extension (Quadrant 0) *** +flw 011 ... ... .. ... 00 @cl_w +fsw 111 ... ... .. ... 00 @cs_w diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode index 5af2e2b072..de97a45acf 100644 --- a/target/riscv/insn16-64.decode +++ b/target/riscv/insn16-64.decode @@ -19,6 +19,10 @@ # This is concatenated with insn16.decode for risc64 targets. # All of the fields and formats are there. =20 +# *** RV64C Standard Extension (Quadrant 0) *** +ld 011 ... ... .. ... 00 @cl_d +sd 111 ... ... .. ... 00 @cs_d + # *** RV64C Standard Extension (Quadrant 1) *** subw 100 1 11 ... 00 ... 01 @cs_2 addw 100 1 11 ... 01 ... 01 @cs_2 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index c215867ff9..b075336062 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -47,10 +47,9 @@ &s imm rs1 rs2 !extern =20 # Argument sets: -&cl rs1 rd &ci imm rd &ciw nzuimm rd -&cs rs1 rs2 +&cs_dw uimm rs1 rs2 &cb imm rs1 &cr rd rs2 &c_j imm @@ -69,8 +68,6 @@ @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 rd=3D= %rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 rd=3D= %rs2_3 -@cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 -@cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 @cs_2 ... ... ... .. ... .. &r rd=3D%rs1_3 rs1=3D%rs1_3 rs2=3D%r= s2_3 @cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 rs2= =3D%rs2_3 @cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 rs2= =3D%rs2_3 @@ -97,10 +94,8 @@ c_addi4spn 000 ........ ... 00 @ciw fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w -c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w -c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually =20 # *** RV64C Standard Extension (Quadrant 1) *** c_addi 000 . ..... ..... 01 @ci diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index d932bfd3e0..f521daf32e 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,28 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_ad= di4spn *a) return trans_addi(ctx, &arg); } =20 -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLW ( RV32FC-only ) */ - return false; -#else - /* C.LD ( RV64C/RV128C-only ) */ - return false; -#endif -} - -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSW ( RV32FC-only ) */ - return false; -#else - /* C.SD ( RV64C/RV128C-only ) */ - return false; -#endif -} - static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) { if (a->imm =3D=3D 0) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5079c68b18..9b8b53a9db 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -55,22 +55,6 @@ typedef struct DisasContext { CPURISCVState *env; } DisasContext; =20 -#ifdef TARGET_RISCV64 -/* convert riscv funct3 to qemu memop for load/store */ -static const int tcg_memop_lookup[8] =3D { - [0 ... 7] =3D -1, - [0] =3D MO_SB, - [1] =3D MO_TESW, - [2] =3D MO_TESL, - [4] =3D MO_UB, - [5] =3D MO_TEUW, -#ifdef TARGET_RISCV64 - [3] =3D MO_TEQ, - [6] =3D MO_TEUL, -#endif -}; -#endif - #ifdef TARGET_RISCV64 #define CASE_OP_32_64(X) case X: case glue(X, W) #else @@ -311,109 +295,6 @@ static void gen_jal(CPURISCVState *env, DisasContext = *ctx, int rd, ctx->base.is_jmp =3D DISAS_NORETURN; } =20 -#ifdef TARGET_RISCV64 -static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, - target_long imm) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - int memop =3D tcg_memop_lookup[(opc >> 12) & 0x7]; - - if (memop < 0) { - gen_exception_illegal(ctx); - return; - } - - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); - gen_set_gpr(rd, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, - target_long imm) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv dat =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - gen_get_gpr(dat, rs2); - int memop =3D tcg_memop_lookup[(opc >> 12) & 0x7]; - - if (memop < 0) { - gen_exception_illegal(ctx); - return; - } - - tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); - tcg_temp_free(t0); - tcg_temp_free(dat); -} -#endif - -#ifdef TARGET_RISCV32 -static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, - int rs1, target_long imm) -{ - TCGv t0; - - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { - gen_exception_illegal(ctx); - return; - } - - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - - switch (opc) { - case OPC_RISC_FLW: - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); - /* RISC-V requires NaN-boxing of narrower width floating point val= ues */ - tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); - break; - case OPC_RISC_FLD: - tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); - break; - default: - gen_exception_illegal(ctx); - break; - } - tcg_temp_free(t0); -} - -static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, - int rs2, target_long imm) -{ - TCGv t0; - - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { - gen_exception_illegal(ctx); - return; - } - - t0 =3D tcg_temp_new(); - gen_get_gpr(t0, rs1); - tcg_gen_addi_tl(t0, t0, imm); - - switch (opc) { - case OPC_RISC_FSW: - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); - break; - case OPC_RISC_FSD: - tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); - break; - default: - gen_exception_illegal(ctx); - break; - } - - tcg_temp_free(t0); -} -#endif - static void gen_set_rm(DisasContext *ctx, int rm) { TCGv_i32 t0; @@ -428,49 +309,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) } =20 =20 -static void decode_RV32_64C0(DisasContext *ctx) -{ - uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); - uint8_t rd_rs2 =3D GET_C_RS2S(ctx->opcode); - uint8_t rs1s =3D GET_C_RS1S(ctx->opcode); - - switch (funct3) { - case 3: -#if defined(TARGET_RISCV64) - /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ - gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); -#else - /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ - gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); -#endif - break; - case 7: -#if defined(TARGET_RISCV64) - /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ - gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); -#else - /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ - gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); -#endif - break; - } -} - -static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) -{ - uint8_t op =3D extract32(ctx->opcode, 0, 2); - - switch (op) { - case 0: - decode_RV32_64C0(ctx); - break; - } -} - #define EX_SH(amount) \ static int ex_shift_##amount(int imm) \ { \ @@ -621,8 +459,7 @@ static void decode_opc(DisasContext *ctx) } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 2; if (!decode_insn16(ctx, ctx->opcode)) { - /* fall back to old decoder */ - decode_RV32_64C(ctx->env, ctx); + gen_exception_illegal(ctx); } } } else { --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150016976382.36158066797066; Tue, 22 Jan 2019 01:40:16 -0800 (PST) Received: from localhost ([127.0.0.1]:41541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsXW-00081v-6z for importer@patchew.org; Tue, 22 Jan 2019 04:40:14 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59106) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glsVJ-0006AI-QF for qemu-devel@nongnu.org; Tue, 22 Jan 2019 04:37:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glsOb-00062b-Qn for qemu-devel@nongnu.org; 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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them reuse the code generator used for the non compressed insns. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/insn16-32.decode | 7 +++++ target/riscv/insn16-64.decode | 5 ++++ target/riscv/insn16.decode | 12 ++------ target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvc.inc.c | 40 ------------------------- 5 files changed, 16 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode index e21a701056..978b8d5834 100644 --- a/target/riscv/insn16-32.decode +++ b/target/riscv/insn16-32.decode @@ -22,3 +22,10 @@ # *** RV32C Standard Extension (Quadrant 0) *** flw 011 ... ... .. ... 00 @cl_w fsw 111 ... ... .. ... 00 @cs_w + +# *** RV32C Standard Extension (Quadrant 1) *** +jal 001 ...... ..... 01 &j imm=3D%imm_cj rd=3D1 + +# *** RV32C Standard Extension (Quadrant 2) *** +flw 011 . ..... ..... 10 &i imm=3D%uimm_6bit_lw %rd rs1=3D2 +fsw 111 ...... ..... 10 &s imm=3D%uimm_6bit_sw rs2=3D2 rs1=3D%rs2_5 diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode index de97a45acf..d43055837a 100644 --- a/target/riscv/insn16-64.decode +++ b/target/riscv/insn16-64.decode @@ -24,5 +24,10 @@ ld 011 ... ... .. ... 00 @cl_d sd 111 ... ... .. ... 00 @cs_d =20 # *** RV64C Standard Extension (Quadrant 1) *** +addiw 001 . ..... ..... 01 @ci subw 100 1 11 ... 00 ... 01 @cs_2 addw 100 1 11 ... 01 ... 01 @cs_2 + +# *** RV64C Standard Extension (Quadrant 2) *** +ld 011 . ..... ..... 10 &i imm=3D%uimm_6bit_ld %rd rs1=3D2 +sd 111 ...... ..... 10 &s imm=3D%uimm_6bit_sd rs2=3D%rs2_5 rs1=3D2 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index b075336062..98dd672c7f 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -45,6 +45,7 @@ &r rd rs1 rs2 !extern &i imm rs1 rd !extern &s imm rs1 rs2 !extern +&j imm rd !extern =20 # Argument sets: &ci imm rd @@ -59,12 +60,10 @@ &c_sd uimm rs2 =20 &c_addi16sp_lui imm_lui imm_addi16sp rd -&c_flwsp_ldsp uimm_flwsp uimm_ldsp rd -&c_fswsp_sdsp uimm_fswsp uimm_sdsp rs2 =20 # Formats 16: @cr .... ..... ..... .. &cr rs2=3D%rs2_5 %rd -@ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd +@ci ... . ..... ..... .. &i imm=3D%imm_ci %rd rs1=3D%rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 rd=3D= %rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 rd=3D= %rs2_3 @@ -80,10 +79,6 @@ @c_sw ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sw rs2=3D%rs= 2_5 =20 @c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16= sp %rd -@c_flwsp_ldsp ... . ..... ..... .. &c_flwsp_ldsp uimm_flwsp=3D%uimm_6bi= t_lw \ - uimm_ldsp=3D%uimm_6bit_ld %rd -@c_fswsp_sdsp ... . ..... ..... .. &c_fswsp_sdsp uimm_fswsp=3D%uimm_6bi= t_sw \ - uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit @c_shift2 ... . .. ... ..... .. &c_shift rd=3D%rd shamt=3D%nzuimm= _6bit @@ -99,7 +94,6 @@ sw 110 ... ... .. ... 00 @cs_w =20 # *** RV64C Standard Extension (Quadrant 1) *** c_addi 000 . ..... ..... 01 @ci -c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually c_li 010 . ..... ..... 01 @ci c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI c_srli 100 . 00 ... ..... 01 @c_shift @@ -117,9 +111,7 @@ c_bnez 111 ... ... ..... 01 @cb c_slli 000 . ..... ..... 10 @c_shift2 c_fldsp 001 . ..... ..... 10 @c_ld c_lwsp 010 . ..... ..... 10 @c_lw -c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 c_jr_mv 100 0 ..... ..... 10 @cr c_ebreak_jalr_add 100 1 ..... ..... 10 @cr c_fsdsp 101 ...... ..... 10 @c_sd c_swsp 110 . ..... ..... 10 @c_sw -c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b59a00cc42..0e098e05fe 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -38,6 +38,7 @@ &i imm rs1 rd &r rd rs1 rs2 &s imm rs2 rs1 +&j imm rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 @@ -47,7 +48,7 @@ @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 @s ....... ..... ..... ... ..... ....... &s imm=3D%imm_s %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd -@j .................... ..... ....... imm=3D%imm_j = %rd +@j .................... ..... ....... &j imm=3D%imm_j = %rd =20 @sh ...... ...... ..... ... ..... ....... &shift shamt=3D%sh10 = %rs1 %rd @csr ............ ..... ... ..... ....... %csr %r= s1 %rd diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index f521daf32e..db9119ec9b 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -38,19 +38,6 @@ static bool trans_c_addi(DisasContext *ctx, arg_c_addi *= a) return trans_addi(ctx, &arg); } =20 -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) -{ -#ifdef TARGET_RISCV32 - /* C.JAL */ - arg_jal arg =3D { .rd =3D 1, .imm =3D a->imm }; - return trans_jal(ctx, &arg); -#else - /* C.ADDIW */ - arg_addiw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; - return trans_addiw(ctx, &arg); -#endif -} - static bool trans_c_li(DisasContext *ctx, arg_c_li *a) { if (a->rd =3D=3D 0) { @@ -163,20 +150,6 @@ static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp= *a) return trans_lw(ctx, &arg); } =20 -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLWSP */ - arg_flw arg_flw =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_flws= p }; - return trans_flw(ctx, &arg_flw); -#else - /* C.LDSP */ - arg_ld arg_ld =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_ldsp }; - return trans_ld(ctx, &arg_ld); -#endif - return false; -} - static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) { if (a->rd !=3D 0 && a->rs2 =3D=3D 0) { @@ -222,16 +195,3 @@ static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp= *a) arg_sw arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; return trans_sw(ctx, &arg); } - -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSWSP */ - arg_fsw a_fsw =3D { .rs1 =3D a->rs2, .rs2 =3D 2, .imm =3D a->uimm_fsws= p }; - return trans_fsw(ctx, &a_fsw); -#else - /* C.SDSP */ - arg_sd a_sd =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm_sdsp }; - return trans_sd(ctx, &a_sd); -#endif -} --=20 2.20.1 From nobody Fri May 17 07:07:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548150380022786.9417741551982; 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Tue, 22 Jan 2019 09:30:31 GMT X-Envelope-From: From: Bastian Koppelmann To: sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Tue, 22 Jan 2019 10:29:09 +0100 Message-Id: <20190122092909.5341-36-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> References: <20190122092909.5341-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.6.2792898, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2019.1.22.92116, AntiVirus-Engine: 5.56.1, AntiVirus-Data: 2019.1.18.5561000 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v5 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" only one translate functions of rvc needs to handle special cases. For the other rvc insns we can remove the extra layer of indirection. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Tested-by: Alistair Francis --- target/riscv/insn16.decode | 37 +++++++++---------- target/riscv/insn_trans/trans_rvc.inc.c | 48 ------------------------- 2 files changed, 17 insertions(+), 68 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 98dd672c7f..d88a0c78ab 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -46,19 +46,15 @@ &i imm rs1 rd !extern &s imm rs1 rs2 !extern &j imm rd !extern +&b imm rs2 rs1 !extern =20 # Argument sets: &ci imm rd &ciw nzuimm rd &cs_dw uimm rs1 rs2 -&cb imm rs1 &cr rd rs2 -&c_j imm &c_shift shamt rd =20 -&c_ld uimm rd -&c_sd uimm rs2 - &c_addi16sp_lui imm_lui imm_addi16sp rd =20 # Formats 16: @@ -70,20 +66,21 @@ @cs_2 ... ... ... .. ... .. &r rd=3D%rs1_3 rs1=3D%rs1_3 rs2=3D%r= s2_3 @cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 rs2= =3D%rs2_3 @cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 rs2= =3D%rs2_3 -@cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 -@cj ... ........... .. &c_j imm=3D%imm_cj +@cb ... ... ... .. ... .. &b imm=3D%imm_cb rs1=3D%rs1_3 rs2=3D0 +@cj ... ........... .. &j imm=3D%imm_cj rd=3D0 =20 -@c_ld ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_ld %rd -@c_lw ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_lw %rd -@c_sd ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sd rs2=3D%rs= 2_5 -@c_sw ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sw rs2=3D%rs= 2_5 +@c_ld ... . ..... ..... .. &i imm=3D%uimm_6bit_ld %rd rs1=3D2 +@c_lw ... . ..... ..... .. &i imm=3D%uimm_6bit_lw %rd rs1=3D2 +@c_sd ... . ..... ..... .. &s imm=3D%uimm_6bit_sd rs1=3D2 rs2=3D%r= s2_5 +@c_sw ... . ..... ..... .. &s imm=3D%uimm_6bit_sw rs1=3D2 rs2=3D%r= s2_5 =20 @c_addi16sp_lui ... . ..... ..... .. &c_addi16sp_lui %imm_lui %imm_addi16= sp %rd =20 @c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit @c_shift2 ... . .. ... ..... .. &c_shift rd=3D%rd shamt=3D%nzuimm= _6bit =20 -@c_andi ... . .. ... ..... .. &ci imm=3D%imm_ci rd=3D%rs1_3 +@c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rd=3D%rs1_3 rs1=3D%= rs1_3 + =20 # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw @@ -98,20 +95,20 @@ c_li 010 . ..... ..... 01 @ci c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI c_srli 100 . 00 ... ..... 01 @c_shift c_srai 100 . 01 ... ..... 01 @c_shift -c_andi 100 . 10 ... ..... 01 @c_andi +andi 100 . 10 ... ..... 01 @c_andi sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 or 100 0 11 ... 10 ... 01 @cs_2 and 100 0 11 ... 11 ... 01 @cs_2 -c_j 101 ........... 01 @cj -c_beqz 110 ... ... ..... 01 @cb -c_bnez 111 ... ... ..... 01 @cb +jal 101 ........... 01 @cj # c_j +beq 110 ... ... ..... 01 @cb # c_beqz +bne 111 ... ... ..... 01 @cb # c_bnez =20 # *** RV64C Standard Extension (Quadrant 2) *** c_slli 000 . ..... ..... 10 @c_shift2 -c_fldsp 001 . ..... ..... 10 @c_ld -c_lwsp 010 . ..... ..... 10 @c_lw +fld 001 . ..... ..... 10 @c_ld # fldsp +lw 010 . ..... ..... 10 @c_lw # lwsp c_jr_mv 100 0 ..... ..... 10 @cr c_ebreak_jalr_add 100 1 ..... ..... 10 @cr -c_fsdsp 101 ...... ..... 10 @c_sd -c_swsp 110 . ..... ..... 10 @c_sw +fsd 101 ...... ..... 10 @c_sd # fsdsp +sw 110 . ..... ..... 10 @c_sw # swsp diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index db9119ec9b..631e72c8b5 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -98,30 +98,6 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_srai *= a) return trans_srai(ctx, &arg); } =20 -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) -{ - arg_andi arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; - return trans_andi(ctx, &arg); -} - -static bool trans_c_j(DisasContext *ctx, arg_c_j *a) -{ - arg_jal arg =3D { .rd =3D 0, .imm =3D a->imm }; - return trans_jal(ctx, &arg); -} - -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a) -{ - arg_beq arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; - return trans_beq(ctx, &arg); -} - -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a) -{ - arg_bne arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; - return trans_bne(ctx, &arg); -} - static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) { int shamt =3D a->shamt; @@ -138,18 +114,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli= *a) return trans_slli(ctx, &arg); } =20 -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) -{ - arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) -{ - arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) { if (a->rd !=3D 0 && a->rs2 =3D=3D 0) { @@ -183,15 +147,3 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx,= arg_c_ebreak_jalr_add *a) } return false; } - -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) -{ - arg_fsd arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) -{ - arg_sw arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_sw(ctx, &arg); -} --=20 2.20.1