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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NyOzJo6HdhqirSo4FTNN+HWWChIIYH9S1hj1nxz1Els=; b=emaPeNzZfiytvchph1Vs4rV0jasLnMCz6Otco+zPhu8DUgwpls2bYG/kT3lx72wYme O3sceL8DhdZAM5NH4XLjCOAzNE6POmWlzSNyINL7L8hYBzSt3bIFFoV16Tiiv+pfVKOx 76I+JzpWLzw0yZKrlK29K4t/N9E7OeyKAqr0g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NyOzJo6HdhqirSo4FTNN+HWWChIIYH9S1hj1nxz1Els=; b=gIk7UVYMxKv9JZaaCmNS5J7+cLygzxa5jChMOEM9jmXdHwLm2fAjwSmYvP3eDskqLR whxym9NlD/cvAITptvxHBNqJVpI1Fhl6PdjMbcJE9UWLonDF7g11oZiPpC0eE6H1xQjz +Bj34IwF7sbhdbseaL2EZuZFThDhwEWQes883kbfciiTvu/bW2dRfBninDqmIH4j7Yfv C6iNF0BcTr661PTQ2ufd/xfaDLXq0QPYwzERx67DC0wvTYAZS37Fxw0mCfKOSf/VhMU5 eQo8G2scNs1hMFy2Wf4wI1gkohqX+YGi2cXiO+AgQDhkmVzmHIkPJ8Uj18eV0hAh+pM8 Ah2w== X-Gm-Message-State: AJcUukfXA3MnIi7i5lpkaZ5T8d+AwHlB0yg6cHlEILsTN8dhwS1pH+ke b17JCIc9fre+jS1vaah3ZkWFITRGyAcwbA== X-Google-Smtp-Source: ALg8bN49KtCxV3r66NgbjoNAW/HZTvij1jmLbBdZ76o5a1eSjVF0b0l5ie+G6Lo9ooS6pyKJTGswbw== X-Received: by 2002:a5d:678b:: with SMTP id v11mr31458990wru.245.1548096689601; Mon, 21 Jan 2019 10:51:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:03 +0000 Message-Id: <20190121185118.18550-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 08/23] hw/misc/iotkit-secctl: Support 4 internal MPCs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-secctl.h | 6 +++--- hw/arm/armsse.c | 6 +++--- hw/misc/iotkit-secctl.c | 5 +++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct= l.h index 1a193b306f1..bcb0437be5b 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -40,8 +40,8 @@ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status - * Controlling the MPC in the IoTKit: - * + named GPIO input mpc_status + * Controlling the (up to) 4 MPCs in the IoTKit/SSE: + * + named GPIO inputs mpc_status[0..3] * Controlling each of the 16 expansion MPCs which a system using the IoTK= it * might provide: * + named GPIO inputs mpcexp_status[0..15] @@ -67,7 +67,7 @@ #define IOTS_NUM_APB_EXP_PPC 4 #define IOTS_NUM_AHB_EXP_PPC 4 #define IOTS_NUM_EXP_MPC 16 -#define IOTS_NUM_MPC 1 +#define IOTS_NUM_MPC 4 #define IOTS_NUM_EXP_MSC 16 =20 typedef struct IoTKitSecCtl IoTKitSecCtl; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 8554be14128..074c1d3a6cf 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -138,7 +138,7 @@ static void armsse_init(Object *obj) sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, &error_abort, NULL); =20 - for (i =3D 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { char *name =3D g_strdup_printf("mpc-irq-splitter-%d", i); SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; =20 @@ -363,7 +363,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) =20 /* We must OR together lines from the MPC splitters to go to the NVIC = */ object_property_set_int(OBJECT(&s->mpc_irq_orgate), - IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", = &err); + IOTS_NUM_EXP_MPC + 1, "num-lines", &err); if (err) { error_propagate(errp, err); return; @@ -636,7 +636,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } =20 /* Wire up the splitters for the MPC IRQs */ - for (i =3D 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; DeviceState *dev_splitter =3D DEVICE(splitter); =20 diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 2222b3e147d..537601cd53f 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -600,7 +600,7 @@ static void iotkit_secctl_mpc_status(void *opaque, int = n, int level) { IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque); =20 - s->mpcintstatus =3D deposit32(s->mpcintstatus, 0, 1, !!level); + s->mpcintstatus =3D deposit32(s->mpcintstatus, n, 1, !!level); } =20 static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level) @@ -686,7 +686,8 @@ static void iotkit_secctl_init(Object *obj) qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); =20 - qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1= ); + qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", + IOTS_NUM_MPC); qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status, "mpcexp_status", IOTS_NUM_EXP_MPC); =20 --=20 2.20.1