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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yb+iGSLny/NNKQr0eBfsaeiJgzhFFuz8UhpvCuLEuGQ=; b=A7I/5q9cXc9mckH8SWkYhVVGGpKGt1aG6AbtZF9CIN6RK69DzBblaj3ory+n/dJ3B+ wKYaW2jQpEWcdm4dIzxCA7gybsgO+QWFyUszgYWKFB2cAo41ASUlCfM7Fbg6Jdg56Gsm jwGei6/ir6KSAwMnXVJ/t3bYmn7CQI0xJ0NNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yb+iGSLny/NNKQr0eBfsaeiJgzhFFuz8UhpvCuLEuGQ=; b=HUzun1nj6R6cDil/r1sPyNGzg/bYXZvZnaBrRcq8jrnn6JpaCBhwY1lhUn9j/kOXIx gPXYXErBDAjCsgO/xEMxasfgmy7JeZt86qgvsJbEmSY/6yX4VqO+UV5AMqtu5FCPlzxg I1enFjWnSW+ySgOhl3EyjtsUsVBIWBR24YgkedWji92wGia789SO241NoQ6yK6VO05uu TPazxVRhqZjru3yVtw5s5frdNvzTtfl4SrDScD+gU+H+fR4kZoHDNMLXdm673PEXUwi9 oo+HL+/1xBakzOZY492bhohGvB1IgKKKJcfmIJpuoLR6D+LoOl77sjn1MdDbEwmKbnE0 PVww== X-Gm-Message-State: AJcUukfiuIy7sVanfZbbgwgq+rIUrOW9zgj9CWm0FqSRqf9j9jtCLMUi swlUh9AEjgs6+aXhbVT0ThiMQQ== X-Google-Smtp-Source: ALg8bN6yesf6W/5VfsxAPADUYmK/8rflni+KaKI1SwDDcNF35Y2zfK0E7VTwnXjz9bll+gd5mJbJQQ== X-Received: by 2002:a1c:e046:: with SMTP id x67mr558024wmg.122.1548096705604; Mon, 21 Jan 2019 10:51:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:17 +0000 Message-Id: <20190121185118.18550-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 22/23] hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In preparation for adding support for the AN521 MPS2 image, we need to handle wiring up the MPS2 device interrupt lines to both CPUs in the SSE-200, rather than just the one that the IoTKit has. Abstract out a "connect to the IoTKit interrupt line" function and make it connect to a splitter which feeds both sets of inputs for the SSE-200 case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 79 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 20 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3859f17d98b..95adcd478ab 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -53,8 +53,11 @@ #include "net/net.h" #include "hw/core/split-irq.h" =20 +#define MPS2TZ_NUMIRQ 92 + typedef enum MPS2TZFPGAType { FPGA_AN505, + FPGA_AN521, } MPS2TZFPGAType; =20 typedef struct { @@ -85,6 +88,7 @@ typedef struct { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; } MPS2TZMachineState; =20 #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -111,6 +115,23 @@ static void make_ram_alias(MemoryRegion *mr, const cha= r *name, memory_region_add_subregion(get_system_memory(), base, mr); } =20 +static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) +{ + /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + assert(irqno < MPS2TZ_NUMIRQ); + + switch (mmc->fpga_type) { + case FPGA_AN505: + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); + case FPGA_AN521: + return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); + default: + g_assert_not_reached(); + } +} + /* Most of the devices in the AN505 FPGA image sit behind * Peripheral Protection Controllers. These data structures * define the layout of which devices sit behind which PPCs. @@ -161,7 +182,6 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, int txirqno =3D i * 2 + 1; int combirqno =3D i + 10; SysBusDevice *s; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), @@ -170,14 +190,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); s =3D SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", txirqno)); - sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } =20 @@ -213,7 +230,6 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, const char *name, hwaddr size) { SysBusDevice *s; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); NICInfo *nd =3D &nd_table[0]; =20 /* In hardware this is a LAN9220; the LAN9118 is software compatible @@ -225,7 +241,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, qdev_init_nofail(mms->lan9118); =20 s =3D SYS_BUS_DEVICE(mms->lan9118); - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", = 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); return sysbus_mmio_get_region(s, 0); } =20 @@ -315,12 +331,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms,= void *opaque, =20 s =3D SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 58 + i * 3)= ); - sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 56 + i * 3)= ); - sysbus_connect_irq(s, 2, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 57 + i * 3)= ); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); =20 g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -339,21 +352,20 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms= , void *opaque, */ PL022State *spi =3D opaque; int i =3D spi - &mms->spi[0]; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); SysBusDevice *s; =20 sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]), TYPE_PL022); object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); s =3D SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 51 + i= )); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); return sysbus_mmio_get_region(s, 0); } =20 static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *iotkitdev; @@ -371,11 +383,38 @@ static void mps2tz_common_init(MachineState *machine) iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), "memory", &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", &error_fatal); =20 + /* + * The AN521 needs us to create splitters to feed the IRQ inputs + * for each CPU in the SSE-200 from each device in the board. + */ + if (mmc->fpga_type =3D=3D FPGA_AN521) { + for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { + char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); + SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; + + object_initialize_child(OBJECT(machine), name, + splitter, sizeof(*splitter), + TYPE_SPLIT_IRQ, &error_fatal, NULL); + g_free(name); + + object_property_set_int(OBJECT(splitter), 2, "num-lines", + &error_fatal); + object_property_set_bool(OBJECT(splitter), true, "realized", + &error_fatal); + qdev_connect_gpio_out(DEVICE(splitter), 0, + qdev_get_gpio_in_named(DEVICE(&mms->iotk= it), + "EXP_IRQ", i)); + qdev_connect_gpio_out(DEVICE(splitter), 1, + qdev_get_gpio_in_named(DEVICE(&mms->iotk= it), + "EXP_CPU1_IRQ", i= )); + } + } + /* The sec_resp_cfg output from the IoTKit must be split into multiple * lines, one for each of the PPCs we create here, plus one per MSC. */ @@ -426,7 +465,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, "realized", &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)= ); + get_sse_irq_in(mms, 15)); =20 /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: --=20 2.20.1