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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y0iJP1/0IWSi2a//xChFZD3ZT9ballXzK0ZjLQwVNl8=; b=L/V3fAmOrajnLxIzBOWs3x+pFR3SCRdZ1OX/H++FufMgmt8nooRFHp8b+BOJxnOAyk N7daPs0ZVixlYoj23Q/4gEeVdRWkQXUNdvGGG43WZtU0NtXTbPk8bd9O2z0a6QSvgVGO VmWSHiIGcDjEFRp+2ge/EXNA87V3598kxjMTo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y0iJP1/0IWSi2a//xChFZD3ZT9ballXzK0ZjLQwVNl8=; b=SH4kalsZn4YDAJETeFfLlGDQADbWq/aTewbugDw+cIpowULhAnilcX2/qJjHxpgACk TgQTiHBay820sS51vCLU7jCA867FF7bA3dUnWm+wEy/XU83oCcPMQ7I8/TPe2EXqAHq9 ld8pOqKz3l836U6oAnnPyOHxQ4C+Pkw0v6wiRRM9eSjjZQm2tD3aNHky8ASiQGYuLPQc KE9TlWeBEFQjfVeQth7XdLLU4u5+YduDfC+dVGTzZM/EhZv5/lBrnUdljOCF4VOgkouN as5bWw3ANXuoRehYBbl0VqP5wUkTWMhFbkiBm8SGzJdwsi7yS6VmGjy1W/8ua5nnqZU/ fHVg== X-Gm-Message-State: AJcUukfAjvsTk2byUG9grmAXNoFjELcJjOYy3nvvy3HfuX/gbBCB/dVU VnHYUIgHdtLDj0u/cr8hVlS7uw== X-Google-Smtp-Source: ALg8bN7mn8BBfV+t0ww8EfNNo+ogUUTdsnWiD2ensAtoc0SxdHlyxwLKoAWKGDoAMxZoH3NtRSJCIw== X-Received: by 2002:adf:9f10:: with SMTP id l16mr30473940wrf.206.1548096704432; Mon, 21 Jan 2019 10:51:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:16 +0000 Message-Id: <20190121185118.18550-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 21/23] hw/arm/armsse: Add SSE-200 model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 19 ++++++++++++++++--- hw/arm/armsse.c | 12 ++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 3914e8e4bf2..f800bafb14a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -1,5 +1,5 @@ /* - * ARM SSE (Subsystems for Embedded): IoTKit + * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 * * Copyright (c) 2018 Linaro Limited * Written by Peter Maydell @@ -12,9 +12,13 @@ /* * This is a model of the Arm "Subsystems for Embedded" family of * hardware, which include the IoT Kit and the SSE-050, SSE-100 and - * SSE-200. Currently we model only the Arm IoT Kit which is documented in + * SSE-200. Currently we model: + * - the Arm IoT Kit which is documented in * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html - * It contains: + * - the SSE-200 which is documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * + * The IoTKit contains: * a Cortex-M33 * the IDAU * some timers and watchdogs @@ -23,6 +27,14 @@ * a security controller * a bus fabric which arranges that some parts of the address * space are secure and non-secure aliases of each other + * The SSE-200 additionally contains: + * a second Cortex-M33 + * two Message Handling Units (MHUs) + * an optional CryptoCell (which we do not model) + * more SRAM banks with associated MPCs + * multiple Power Policy Units (PPUs) + * a control interface for an icache for each CPU + * per-CPU identity and control register blocks * * QEMU interface: * + QOM property "memory" is a MemoryRegion containing the devices provi= ded @@ -93,6 +105,7 @@ * them via the ARMSSE base class, so they have no IOTKIT() etc macros. */ #define TYPE_IOTKIT "iotkit" +#define TYPE_SSE200 "sse-200" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index eb691faf720..5d53071a5a0 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -50,6 +50,18 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D false, .has_cpuid =3D false, }, + { + .name =3D TYPE_SSE200, + .sram_banks =3D 4, + .num_cpus =3D 2, + .sys_version =3D 0x22041743, + .sys_config_format =3D SSE200Format, + .has_mhus =3D true, + .has_ppus =3D true, + .has_cachectrl =3D true, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + }, }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) --=20 2.20.1