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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bbMrEQttECEQjo2HwYbstwzK4LFM5IR2j7Wqx0jx8pQ=; b=e2LCMT9LQ1Mdjr+1MMgPhcU5vqCfD42pcIcOC2kWUhNHqY2Hc1atNU7gxGo9xrxpVm 0L2D8irYgnl4IBD04V40VfOQYRYlzIR5e6GK+UuaKXe7jWiSzJfkCIwAARWuc+K/R7co Zck7bUIm2d70xj0kbfJ6chpxPUq+9MVMgmAnc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bbMrEQttECEQjo2HwYbstwzK4LFM5IR2j7Wqx0jx8pQ=; b=Cg7OdnGA+sZ0VVJacceMeT0yJuOcrqgkouHUdI/F29pn4MW11lx7z/mdLzqnE5vUbJ BiQ4C6Q/OFY5xDTMzC7+dQ8vh32e0+1cxcPMS3KJaqHZxKgj9o6qj2QIUKBN5RDgB1AP 22gCBlezTXv5T1mBpr2sL5lOaN9YBvAcQHsUXfaW5fw+W1LFk/wlqH+e/Zj1TJKmTR7Y 9jdObt5OkwikBj87B4LERhguYEWoYN5beRQ+LnxOlF0kdIOyiDNC7/ARdx0dM1j9/+tK PxDaNV6L6cwWcWLEmyTHgk61RqOHgA+Fv0lebkGenwvnicJKqrYCch3EmXKO3klQYXVh 2gHQ== X-Gm-Message-State: AJcUuke0fzpk3/HYKYrJ1kLnCac9a1tgLIAb3nZaVpRa6aHhMgYKtaHw Y9NpkDblVMFqXK52nS5JyvsZC9MTRwhP4A== X-Google-Smtp-Source: ALg8bN4uM0f+FMSiaksFJBXbe+NEu1SdpRLUM/SLXZfFST86d4sMexyn4KJPVciGmLmOvdTkKR0Iog== X-Received: by 2002:a7b:c757:: with SMTP id w23mr504644wmk.59.1548096703334; Mon, 21 Jan 2019 10:51:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:15 +0000 Message-Id: <20190121185118.18550-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 20/23] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 961dbb3032a..3914e8e4bf2 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/armsse-cpuid.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -153,6 +154,8 @@ typedef struct ARMSSE { UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 + ARMSSECPUID cpuid[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9c111ac6a40..eb691faf720 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -34,6 +34,7 @@ struct ARMSSEInfo { bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; + bool has_cpuid; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -47,6 +48,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_ppus =3D false, .has_cachectrl =3D false, .has_cpusecctrl =3D false, + .has_cpuid =3D false, }, }; =20 @@ -314,6 +316,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpuid%d", i); + + sysbus_init_child_obj(obj, name, &s->cpuid[i], + sizeof(s->cpuid[i]), + TYPE_ARMSSE_CPUID); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -864,6 +876,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); + object_property_set_bool(OBJECT(&s->cpuid[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1