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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BudMfJPXXih/S5U7jqBZwz9zkq27ugNQSCi2J5JSPGU=; b=XGzQP9dEvABjlLxrY/+/pZ/MQQI8uNCahT7MkkBNCbeGAYlBVVnNTWqUxZqbOioDx2 DPrEyzLGeU+PumTbco9Pj9sbKuO+/xtnqD4ZI35xnJQw+Nw9htZ7VIfhPZ1M7mLh3Mig Jhy4GdPtL7l4afGLwQnDQtaA7XBGoN8f2bVo4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BudMfJPXXih/S5U7jqBZwz9zkq27ugNQSCi2J5JSPGU=; b=mUtk5blq5vEFecdvF3/yjr0sy0b9YsEQQcVZpsdrqyc1SMtDZ1NjJqR8E4sH9KlPms O5NHn3pNhJl8OFwH4C+7hFyOMQ8bSA0KHHt8eX8ySnFlWImWkO5wvumDnLwOyCDVdeIl 2h9hexdP0SHPgk9KUMei63U2brTEp86QQ16OU9xZE+A8HC/2VoOs3bKMzh1D+ByaU3vX rWJuBJytMEptvHZ6KHaXQxcW/Tj3oaUp6wRu8yaBl4oaiYpJnbQqXgVty7dWHT1VT3Bm SSOpTjUyewuLoZjc85sKB4xCe5I6iFbmHewg65cwty6jv0QdfH0FOlKddbeBl3ZnNMGO sajw== X-Gm-Message-State: AJcUukcoDhW2oW1eFZY5B4LtIt00bYweN52qVj1cipf9UCV5CvNuE7b/ o39Sk7+v9BWvQgltOEFLR4NoxthjBm7IQg== X-Google-Smtp-Source: ALg8bN6lHnG1wHLT2fssKPXA128lwayAB6B3XPWM3uG1o0UZd7gdtXUfRvw2lsKMv25QDq82KZlvYw== X-Received: by 2002:a1c:5984:: with SMTP id n126mr555831wmb.62.1548096681581; Mon, 21 Jan 2019 10:51:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:50:56 +0000 Message-Id: <20190121185118.18550-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 01/23] armv7m: Don't assume the NVIC's CPU is CPU 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/armv7m.c | 6 ++++-- hw/intc/armv7m_nvic.c | 3 +-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f4446528307..f9aa83d20ef 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **= errp) } } =20 - /* Tell the CPU where the NVIC is; it will fail realize if it doesn't - * have one. + /* + * Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. Similarly, tell the NVIC where its CPU is. */ s->cpu->env.nvic =3D &s->nvic; + s->nvic.cpu =3D s->cpu; =20 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0beefb05d44..790a3d95849 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) Error *err =3D NULL; int regionlen; =20 - s->cpu =3D ARM_CPU(qemu_get_cpu(0)); - + /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); return; --=20 2.20.1