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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5oXNf8YbRJ27W92QaQUg2Jg/rlBLxD7V8QWz6bSn8Tg=; b=NMEiUA6jC+0+m1CiYmjfyxKZWyJRx0xr6H4P9drgvZ5QPfqBhY/BKSqZk/IPbrU/Xf OGNPviQ/5fYaPqA18k0svK4vT1RQaKgBapMB2EvRQiEnTxO/pZJ0pETAcz0p12JMtNLg bx580M/WbdelgqUl1aoX8/tCqBjJSdjgqtGlE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oXNf8YbRJ27W92QaQUg2Jg/rlBLxD7V8QWz6bSn8Tg=; b=CujO+/fvGhjcfu7nKH6pr3cesvxnOojeZIRSHLBCiFFZjFFkPk11fVCL+QHDVU6oYZ hLi6kD+4F7ql7mjzW9hpEuIIEPjYV/2E5poqyS9WpoHMnUL3Dj+ta4vUehAv9q4IzKaw 1O7/2K9vVVp792YT5CbcTcsvmuMUYEAKYf41SxF197eyj1LzMizOa5+WiqRR4jBLZPhf L9rZG74skpyP0P2P3JBr95dcP6gc+Ya5FpNDmB8WYtL4MD1QEZKBll85Sd5eYsg51BGb lYlz02dZl9sUo6Ik0JHszoXepS6YeC1aVsIA6cz46eLxyCaqOQrz8rY+YQWde6eGs3FO NpSg== X-Gm-Message-State: AJcUukc6NFCMhVFtT1Kze5+qdpmDADw+lO2Nj2SBrsERjS/aoQk5HLxd LMZfeLuWHjXxaYEgPpVWeaRMRg== X-Google-Smtp-Source: ALg8bN74c/3XSF9S+ykrcrnY28J2F5cQo6oflXsSA29QWkMqYizS0wBi+4xODclwajSVej8N5quI9A== X-Received: by 2002:adf:9c01:: with SMTP id f1mr30514330wrc.286.1548096701027; Mon, 21 Jan 2019 10:51:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:13 +0000 Message-Id: <20190121185118.18550-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 18/23] hw/arm/armsse: Add unimplemented-device stub for CPU local control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9d830057d5c..961dbb3032a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -151,6 +151,7 @@ typedef struct ARMSSE { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; + UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 41e4a781e11..9c111ac6a40 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -33,6 +33,7 @@ struct ARMSSEInfo { bool has_mhus; bool has_ppus; bool has_cachectrl; + bool has_cpusecctrl; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -45,6 +46,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_mhus =3D false, .has_ppus =3D false, .has_cachectrl =3D false, + .has_cpusecctrl =3D false, }, }; =20 @@ -302,6 +304,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpusecctrl%d", i); + + sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], + sizeof(s->cpusecctrl[i]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -833,6 +845,25 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50010000, = mr); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPUSECCTRL%d", i); + MemoryRegion *mr; + + qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); + g_free(name); + qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000= ); + object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]= ), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1