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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=16YcVXkNI0qZQIE9OU/93mNUdU9hbKw0nKOMHfNAYQc=; b=RRyB9+r1E4aTDZK4X/LljGD24LU6DFmbEl+Dgrb40u5v9tttO5ToKm4rgdX2rqxkva MG4hVDu6AjK+kHLE+cm/K6IFt8oEkvGIwAGAzFvNk7hRCsCneFHVaitePfhvv+SIVwJ+ tLGN+7vZBz4ooX1E2WevPKd7kr9YEsQyHzccw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=16YcVXkNI0qZQIE9OU/93mNUdU9hbKw0nKOMHfNAYQc=; b=MDNY5KyAezdWkNMba+pGajw44se2MHDQfkdabIqcXx/p910vdOHoJhylAJ6tRQYq0G Ty8tqOfKtHfwDjOOFuScj8euWGWAaIBc79j2BY5fGs9cDlp2L0sGKaTGZElHzF54zIuh nCX72JtAqknxfGMOB8beiruK/FMy+PljM9ZQ1T6FOXODgU2sIdKkCgNOl0ilL8pP2WPQ qdPw+eoTg94IIpc40Tq+5341i49zwz76SUzuV3dyCa8UL2/zMCMAwMHejesH3gcL8+8s axd4mEVLzubuKG/HaOKBP3/OL0cop2xX8eYQ+JEbr1vkq01QrH+ifKDYZikTeRVT4PVq YtnA== X-Gm-Message-State: AJcUukehFyAEYvtRHnkQe70jXPgJkB4bVhvyZQ3WCsDqsafT/EjFMDWZ WdzQ08ROK1pkih3L8eF3D2YcHFIF8YbvYQ== X-Google-Smtp-Source: ALg8bN4huX0n6vA9wOioumb58JSq3w0TB5hTQJ21O0Fg71HWtcKBv76BttZZVyhSu9h37MM3K3QJZQ== X-Received: by 2002:a5d:568c:: with SMTP id f12mr27701887wrv.101.1548096700023; Mon, 21 Jan 2019 10:51:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:12 +0000 Message-Id: <20190121185118.18550-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 17/23] hw/arm/armsse: Add unimplemented-device stub for cache control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 39 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9855ec5f269..9d830057d5c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -150,6 +150,7 @@ typedef struct ARMSSE { =20 UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; + UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 280ba5c78be..41e4a781e11 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -32,6 +32,7 @@ struct ARMSSEInfo { SysConfigFormat sys_config_format; bool has_mhus; bool has_ppus; + bool has_cachectrl; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -43,6 +44,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, .has_ppus =3D false, + .has_cachectrl =3D false, }, }; =20 @@ -290,6 +292,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cachectrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cachectrl%d", i); + + sysbus_init_child_obj(obj, name, &s->cachectrl[i], + sizeof(s->cachectrl[i]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -795,7 +807,32 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, armsse_get_common_irq_in(s, 10)); =20 - /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ + /* + * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): + * private per-CPU region (all these devices are SSE-200 only): + * 0x50010000: L1 icache control registers + * 0x50011000: CPUSECCTRL (CPU local security control registers) + * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block + */ + if (info->has_cachectrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cachectrl%d", i); + MemoryRegion *mr; + + qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); + g_free(name); + qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); + object_property_set_bool(OBJECT(&s->cachectrl[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i])= , 0); + memory_region_add_subregion(&s->cpu_container[i], 0x50010000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1