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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6dJlwUKV/mqO+LXLnxltTP2TIDBTQAdk8nXHap2RUUY=; b=SAD5tiJYu6GshOFt06OOesXbZzTo7uSnbOUYUPP6hioR7NUflBeSy72YkIuyrwN7oX aLQuXcQhe+ZMXQfxHe50YOXIq3qbei+/aVge2SxWMv7fEOg+ZqoeT/h18L2PM4D6aSfa nI9sisNjgTfbfI3NdCCJl6IPaOOHRZbEp5pXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6dJlwUKV/mqO+LXLnxltTP2TIDBTQAdk8nXHap2RUUY=; b=KgFROWJEnRQ2dnd2gKuy4YGFcvExYTO5mGaECTr+BEoUERe4E7iAFLjTUsHKFNvfR/ nPgPCs6rejDyZFdiitCfCFBaZuivDjDx0cddjn2DOi8IP5BatRfHBKdVlnI3Kah00UXn 2yFiqEy5Msbpkckf4ZWIVlqmwCPBSrFhfgwdHGWWXdIyxMXdyPUCN7Sm4BP7wjMXrsFi KlWkZODIaIDX1BHmocylMLESYzn/axDbqIYTr7eYTy4m9nsRkU6nNXPn82MX5v7iXva0 CNOHEBqDG23TqP1eWDUUCYEVeLkHXSxqyYwII9NiOO2/beD2vf1wLONdV+bTyAWz+GXp iwYg== X-Gm-Message-State: AJcUukcJtFRl4lA2MtH9LfujDahA0JrwKKDD2QNpcB6a6aMs3K1VlMnd izRo3PiAbDnTK8FxEUmRsMlcbg== X-Google-Smtp-Source: ALg8bN69OhaQokesDM5SCBqVsqokbgk72zS9fwThEkrY6Fk4Rlf0+5CQP+AsJabJCXcsAqoh57ocjg== X-Received: by 2002:a1c:4807:: with SMTP id v7mr555289wma.53.1548096697933; Mon, 21 Jan 2019 10:51:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:10 +0000 Message-Id: <20190121185118.18550-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 15/23] hw/arm/armsse: Add unimplemented-device stubs for MHUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 999c2e4f7e5..dbfcb280605 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" @@ -137,6 +138,8 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 + UnimplementedDeviceState mhu[2]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 19cae77e770..1f3dc89c8e8 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -30,6 +30,7 @@ struct ARMSSEInfo { int num_cpus; uint32_t sys_version; SysConfigFormat sys_config_format; + bool has_mhus; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -39,6 +40,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .num_cpus =3D 1, .sys_version =3D 0x41743, .sys_config_format =3D IoTKitFormat, + .has_mhus =3D false, }, }; =20 @@ -257,6 +259,12 @@ static void armsse_init(Object *obj) sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); + if (info->has_mhus) { + sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), + TYPE_UNIMPLEMENTED_DEVICE); + sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), + TYPE_UNIMPLEMENTED_DEVICE); + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -616,6 +624,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * 0x40000000: timer0 * 0x40001000: timer1 * 0x40002000: dual timer + * 0x40003000: MHU0 (SSE-200 only) + * 0x40004000: MHU1 (SSE-200 only) * We must configure and realize each downstream device and connect * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. @@ -666,6 +676,31 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } =20 + if (info->has_mhus) { + for (i =3D 0; i < ARRAY_SIZE(s->mhu); i++) { + char *name =3D g_strdup_printf("MHU%d", i); + char *port =3D g_strdup_printf("port[%d]", i + 3); + + qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name); + qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000); + object_property_set_bool(OBJECT(&s->mhu[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0); + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), + port, &err); + if (err) { + error_propagate(errp, err); + return; + } + g_free(name); + g_free(port); + } + } + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -681,6 +716,12 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0x40001000, mr); mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 2); memory_region_add_subregion(&s->container, 0x40002000, mr); + if (info->has_mhus) { + mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 3); + memory_region_add_subregion(&s->container, 0x40003000, mr); + mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 4); + memory_region_add_subregion(&s->container, 0x40004000, mr); + } for (i =3D 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, qdev_get_gpio_in_named(dev_apb_ppc0, --=20 2.20.1