From nobody Fri Nov 7 14:31:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098385850184.52969603787358; Mon, 21 Jan 2019 11:19:45 -0800 (PST) Received: from localhost ([127.0.0.1]:58496 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf6m-0000nI-Q3 for importer@patchew.org; Mon, 21 Jan 2019 14:19:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevS-0008OY-R7 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002sm-3Y for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:45 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefe-0002iK-Nz for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:42 -0500 Received: by mail-wm1-x343.google.com with SMTP id p6so11831828wmc.1 for ; Mon, 21 Jan 2019 10:51:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e/n/E9zIC87pmNrtpyul6OlAohOOfM09CA6XexX2VVY=; b=fJcrt2ee0cMoAYCl8VUBXDczHAbuDqtq7DELrUDquPqh7qPmJ/FmOgv6miS2LibFPa etUHy1h3HjFArQw7XTQwd0BFmHyfj9p8JPN61KDaq1FdK3aQ/QvoFU1FMsmuvB8kf6xm ASaLu9/85WEhGFmlgaAJTIevTxY1ySu+LmWtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e/n/E9zIC87pmNrtpyul6OlAohOOfM09CA6XexX2VVY=; b=nyJOS1vlnRUQL5A9KLb16gZsqBsBfHuw18a8+y3eLeIDU/Kunpkj24IIgiWLnLl0bq qMn8maKzhy9+kbGjZ+w6p5OYk35vcSF6ILkYsjPucrROVaJAFsR7Fe9J3zDeqlcUc5D3 YdXA9JPHQ8VHg0r5Ajl/saJ79yRIBZZbyzXUpHngCU95ksqd5ubZ981uDaAmkm/0VgJB 81TlPQpZcGJcNu8mo+UZlD+A2VBN8XrldtpmFb6//pyPiJiji+UX+AkvRmMO8V8XRI3o CnTOk9fK9I3huaTowXEmjLZRRbdboOidzXfGXLrs+KvDcTjXw3JFwhvDF96sH1MDX2N7 ukNw== X-Gm-Message-State: AJcUukfC0EqtkcYwif1uHij5r4qfvZJsPhMAZZ5aAqdaGi8+0y4ghW5n bnfkZVysPZidpSAUFclZ7jon5g== X-Google-Smtp-Source: ALg8bN7az6jkgFRO/wP9chzZj7eYZlRhd20Ob/GgkSE1WlLYU/JJkv2KpZPCQO5MZ5o6NZGkO7ejJw== X-Received: by 2002:a1c:ca15:: with SMTP id a21mr532240wmg.132.1548096695764; Mon, 21 Jan 2019 10:51:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:08 +0000 Message-Id: <20190121185118.18550-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 13/23] hw/arm/armsse: Put each CPU in its own cluster object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 2 ++ hw/arm/armsse.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 89f19a971f4..999c2e4f7e5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -80,6 +80,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" +#include "hw/cpu/cluster.h" =20 #define TYPE_ARMSSE "arm-sse" #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) @@ -110,6 +111,7 @@ typedef struct ARMSSE { =20 /*< public >*/ ARMv7MState armv7m[SSE_MAX_CPUS]; + CPUClusterState cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2472dfef3a1..2eb4ea3bfe0 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -147,9 +147,22 @@ static void armsse_init(Object *obj) memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("armv7m%d", i); - sysbus_init_child_obj(obj, name, &s->armv7m[i], sizeof(s->armv7m), - TYPE_ARMV7M); + /* + * We put each CPU in its own cluster as they are logically + * distinct and may be configured differently. + */ + char *name; + + name =3D g_strdup_printf("cluster%d", i); + object_initialize_child(obj, name, &s->cluster[i], + sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); + g_free(name); + + name =3D g_strdup_printf("armv7m%d", i); + sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, + &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7= M); qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m33")); g_free(name); @@ -406,6 +419,18 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) error_propagate(errp, err); return; } + /* + * The cluster must be realized after the armv7m container, as + * the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before + * the cluster is realized. + */ + object_property_set_bool(OBJECT(&s->cluster[i]), + true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } =20 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); --=20 2.20.1