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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hxN9w6vB/LiDEV5gzGDXQH/dDiAcrkx41p69PfQpSas=; b=czH42x5GG7hu82urZ1qyzXtX0PdCCEGBdww4vSZWEk9jkvtCRhQaIcvOupgjxp8P9o H8TDD10vorRCkBfzamXuZjCt0SbF3jT9NifOw9nnqbbxXJJeaAKHioQbjDVlhaqokLs4 lntdSHJc1OwoFJzZfgv57zVRJPva8RG0DQTMk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hxN9w6vB/LiDEV5gzGDXQH/dDiAcrkx41p69PfQpSas=; b=iIsrnvWyHEaZpCbQkVO7lUZkyUrHiyRLW6JGaGOMObj9Src4LIBE1BqjKGormQVgml wpTWxR1M0+tPIchk99HaVOAxLvckU+QJYESfKjtINPcdxn42+uBoAXsOEhwFmyme9O9k jooTpyPhQIKwjuhchKqHadLdblvYZ4W1BAzFB9OljS3gzNQ0iSa/sCXwa5q32lus4eO2 r5NFJyOylixsZEubrd16ZT+0jgp9qcJ6XyUR6cxXUJXZBShgJRPxppns4uMnzo3uuiDv xGXpWwyLXtiJdWACj7vkMymFhZMZfJirZexTDD2KOl+oVcLq9wM4AX9S5QAAsCHsZWRN 3Iug== X-Gm-Message-State: AJcUukd5Pmn+dslRBNZdvZQXgxGnrCyJEylY1Tx+8p9qpLiBKvs8E/vi 9kurhA6XchYmX2pOUaU1w7Yhrw== X-Google-Smtp-Source: ALg8bN4VYlkN4p7M6UFf+/LAA/xBTHibRlpkM1eL9pbPZw+s+GfC8iN97d+qsaH1j7EnsEvwvQlWmA== X-Received: by 2002:a1c:bd86:: with SMTP id n128mr588135wmf.22.1548096694400; Mon, 21 Jan 2019 10:51:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:07 +0000 Message-Id: <20190121185118.18550-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 12/23] hw/arm/armsse: Give each CPU its own view of memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 10 ++++++++++ hw/arm/armsse.c | 22 ++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index faf5dfed252..89f19a971f4 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -135,7 +135,17 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 + /* + * 'container' holds all devices seen by all CPUs. + * 'cpu_container[i]' is the view that CPU i has: this has the + * per-CPU devices of that CPU, plus as the background 'container' + * (or an alias of it, since we can only use it directly once). + * container_alias[i] is the alias of 'container' used by CPU i+1; + * CPU 0 can use 'container' directly. + */ MemoryRegion container; + MemoryRegion container_alias[SSE_MAX_CPUS - 1]; + MemoryRegion cpu_container[SSE_MAX_CPUS]; MemoryRegion alias1; MemoryRegion alias2; MemoryRegion alias3; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5cb2b78b1fc..2472dfef3a1 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -153,6 +153,15 @@ static void armsse_init(Object *obj) qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m33")); g_free(name); + name =3D g_strdup_printf("arm-sse-cpu-container%d", i); + memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); + g_free(name); + if (i > 0) { + name =3D g_strdup_printf("arm-sse-container-alias%d", i); + memory_region_init_alias(&s->container_alias[i - 1], obj, + name, &s->container, 0, UINT64_MAX); + g_free(name); + } } =20 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), @@ -332,7 +341,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff */ =20 - memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -2); =20 for (i =3D 0; i < info->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&s->armv7m[i]); @@ -373,7 +382,16 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } } - object_property_set_link(cpuobj, OBJECT(&s->container), "memory", = &err); + + if (i > 0) { + memory_region_add_subregion_overlap(&s->cpu_container[i], 0, + &s->container_alias[i - 1]= , -1); + } else { + memory_region_add_subregion_overlap(&s->cpu_container[i], 0, + &s->container, -1); + } + object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), + "memory", &err); if (err) { error_propagate(errp, err); return; --=20 2.20.1