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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZtglysStG0tXIkc7Lj+My+7b7XqiO1d9EdiWVYmU19M=; b=ZMdYJmqzA5/BcWiQm8dp6Y66h5RsB/6WGQZ6Uk6pgVk1JEReUlPo7fupO4z0o2YNxA Ie7svBsqsr5CU2IvQ2/w8aV80Eymgqel6wyFcc2nyhwbklU79jDpfUXeuu6nrn+hRd21 BOyNKJIjrV8gfpfmEJgJeGL4OuQPaPmti0yCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZtglysStG0tXIkc7Lj+My+7b7XqiO1d9EdiWVYmU19M=; b=Gc8wjQXdk7rjcVq0X4H7gu71hPoNvcYX3L+rTHxfgfXJoDqKlI/IU/EYUBcSx7k7UK ASalf+mSwUXy9t6K6L6AURXq3k5TMCJD9Hl0TC0LAgHeqAa/m0tun8A4pGI1KIfo+XOy tkGwW05MGz1r5fvQMQ7hrKny5+Z+V2wOqpItrBtu17/5Q7d+KAF3HU64Lq8ExCCO1lyJ eHKjm5q7dDTYNVzHfeYbp4lZGMsN7CLqcCKO3xZBVr3t9QvMWbIC7q9erdUQf8U3dPCa dLRfuv90FkW995ZVp1YDANMjSN2qUSz3BT7NVPDE2zbZ9mX00S5QQpjGY9qMPnMAmyva SghA== X-Gm-Message-State: AJcUukf8Dwn1mxw9vdoHWDb8fepZ5k/ddhZ+Y8/mPiW6ZB6fj/QAZVKA zCAJWvUZQnSmyQSjYv3tR9Ilkg== X-Google-Smtp-Source: ALg8bN6eONj0omW2Km1lqm7d3AhBgeoePlM6hLj85GNaoo8xG2UX1CLOX4be8/Ji9Tq9Y4bYw5yPOA== X-Received: by 2002:a7b:c44d:: with SMTP id l13mr578253wmi.144.1548096691956; Mon, 21 Jan 2019 10:51:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:05 +0000 Message-Id: <20190121185118.18550-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 10/23] hw/arm/armsse: Make SRAM bank size configurable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 99714aa63cd..e4a05013316 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -146,6 +146,7 @@ typedef struct ARMSSE { MemoryRegion *board_memory; uint32_t exp_numirq; uint32_t mainclk_frq; + uint32_t sram_addr_width; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index b639b54e0db..a2ae5d3c4b9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -221,6 +221,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) DeviceState *dev_apb_ppc1; DeviceState *dev_secctl; DeviceState *dev_splitter; + uint32_t addr_width_max; =20 if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -232,6 +233,15 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } =20 + /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ + assert(is_power_of_2(info->sram_banks)); + addr_width_max =3D 24 - ctz32(info->sram_banks); + if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { + error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", + addr_width_max); + return; + } + /* Handling of which devices should be available only to secure * code is usually done differently for M profile than for A profile. * Instead of putting some devices only into the secure address space, @@ -352,8 +362,10 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) for (i =3D 0; i < info->sram_banks; i++) { char *ramname =3D g_strdup_printf("armsse.sram%d", i); SysBusDevice *sbd_mpc; + uint32_t sram_bank_size =3D 1 << s->sram_addr_width; =20 - memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &er= r); + memory_region_init_ram(&s->sram[i], NULL, ramname, + sram_bank_size, &err); g_free(ramname); if (err) { error_propagate(errp, err); @@ -372,7 +384,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } /* Map the upstream end of the MPC into the right place... */ sbd_mpc =3D SYS_BUS_DEVICE(&s->mpc[i]); - memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000, + memory_region_add_subregion(&s->container, + 0x20000000 + i * sram_bank_size, sysbus_mmio_get_region(sbd_mpc, 1)); /* ...and its register interface */ memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, @@ -748,6 +761,7 @@ static Property armsse_properties[] =3D { MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1