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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BudMfJPXXih/S5U7jqBZwz9zkq27ugNQSCi2J5JSPGU=; b=XGzQP9dEvABjlLxrY/+/pZ/MQQI8uNCahT7MkkBNCbeGAYlBVVnNTWqUxZqbOioDx2 DPrEyzLGeU+PumTbco9Pj9sbKuO+/xtnqD4ZI35xnJQw+Nw9htZ7VIfhPZ1M7mLh3Mig Jhy4GdPtL7l4afGLwQnDQtaA7XBGoN8f2bVo4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BudMfJPXXih/S5U7jqBZwz9zkq27ugNQSCi2J5JSPGU=; b=mUtk5blq5vEFecdvF3/yjr0sy0b9YsEQQcVZpsdrqyc1SMtDZ1NjJqR8E4sH9KlPms O5NHn3pNhJl8OFwH4C+7hFyOMQ8bSA0KHHt8eX8ySnFlWImWkO5wvumDnLwOyCDVdeIl 2h9hexdP0SHPgk9KUMei63U2brTEp86QQ16OU9xZE+A8HC/2VoOs3bKMzh1D+ByaU3vX rWJuBJytMEptvHZ6KHaXQxcW/Tj3oaUp6wRu8yaBl4oaiYpJnbQqXgVty7dWHT1VT3Bm SSOpTjUyewuLoZjc85sKB4xCe5I6iFbmHewg65cwty6jv0QdfH0FOlKddbeBl3ZnNMGO sajw== X-Gm-Message-State: AJcUukcoDhW2oW1eFZY5B4LtIt00bYweN52qVj1cipf9UCV5CvNuE7b/ o39Sk7+v9BWvQgltOEFLR4NoxthjBm7IQg== X-Google-Smtp-Source: ALg8bN6lHnG1wHLT2fssKPXA128lwayAB6B3XPWM3uG1o0UZd7gdtXUfRvw2lsKMv25QDq82KZlvYw== X-Received: by 2002:a1c:5984:: with SMTP id n126mr555831wmb.62.1548096681581; Mon, 21 Jan 2019 10:51:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:50:56 +0000 Message-Id: <20190121185118.18550-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 01/23] armv7m: Don't assume the NVIC's CPU is CPU 0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/armv7m.c | 6 ++++-- hw/intc/armv7m_nvic.c | 3 +-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f4446528307..f9aa83d20ef 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,10 +178,12 @@ static void armv7m_realize(DeviceState *dev, Error **= errp) } } =20 - /* Tell the CPU where the NVIC is; it will fail realize if it doesn't - * have one. + /* + * Tell the CPU where the NVIC is; it will fail realize if it doesn't + * have one. Similarly, tell the NVIC where its CPU is. */ s->cpu->env.nvic =3D &s->nvic; + s->nvic.cpu =3D s->cpu; =20 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); if (err !=3D NULL) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0beefb05d44..790a3d95849 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2274,8 +2274,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) Error *err =3D NULL; int regionlen; =20 - s->cpu =3D ARM_CPU(qemu_get_cpu(0)); - + /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); return; --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548096852489224.29368495461006; Mon, 21 Jan 2019 10:54:12 -0800 (PST) Received: from localhost ([127.0.0.1]:58094 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glei3-0002eC-El for importer@patchew.org; Mon, 21 Jan 2019 13:54:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glefN-0000oe-Em for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefM-0002X5-Nh for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:25 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46041) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefL-0002Uu-U8 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:24 -0500 Received: by mail-wr1-x441.google.com with SMTP id t6so24556097wrr.12 for ; Mon, 21 Jan 2019 10:51:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Riqos2VP4k1FpZGAuE3wK4J/sKpJkrJvi5DAGfdCgXc=; b=EvbakUOsiQn1dEFRXSf/ntddoYujwEmLJBVnqkFQFDYG04lBDchLWPq76KUWx6nRd3 b0J+2Oq7JRrChIcSdsT4WVYi889yEFogbROpRP8CW1goEQ/GZkwPXqqX2pNeg0MEsG/j slGuUfA+u/GcZbfHIfygPLW1s4Oz9hcClk2NQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Riqos2VP4k1FpZGAuE3wK4J/sKpJkrJvi5DAGfdCgXc=; b=hUWYkgoXi/gqp+r/+J1Kh4D7lIon+oEk3/nGKOQh55lYTzr6ar4qs8rnklNmPqvjw4 DeL94eGPUtmjq+U3CLQbKgsCe92Ip6h+o1tvWDsrk5H0IsZz2+JT7zpGRcY/8Cj/oXMa 0NFocaTraf35pcSp78hQDzwxR/Y7JV9PlpjEh6NwBbG123LtWU2e2H7m8bzOe8Q7Tb7U MViBr6hOwZrdmveFCDkCsGxkXN5rKdcf7Oqxpw2JEbNlfFedqNrz2PCLwabebA3FGC+5 sGMwHFFdJcpauD4VFKz2NosdrS9uv8RRz7RjecG5JJ+/09eLGETGb0y1wWx+P37HT6dq kdOg== X-Gm-Message-State: AJcUukeg1JcUocuKjm5StbYIhVLwfZqIRT3UWs8u220gHuRj1+0P+2Zg dZrCcjPrrZdi50iGdtXcKUUvTA== X-Google-Smtp-Source: ALg8bN6XNOdoDuJrYJCPwHdvi1b9dBWSYfEtimjlBPBKhP0ZqZFQYm72CM77rZnd/b0asqgx++EYag== X-Received: by 2002:a5d:42ce:: with SMTP id t14mr29775792wrr.51.1548096682643; Mon, 21 Jan 2019 10:51:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:50:57 +0000 Message-Id: <20190121185118.18550-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 02/23] armv7m: Make cpu object a child of the armv7m container X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rather than just creating the CPUs with object_new, make them child objects of the armv7m container. This will allow the cluster code to find the CPUs if an armv7m object is made a child of a cluster object. object_new_with_props() will do the parenting for us. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/armv7m.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index f9aa83d20ef..0f2c8e066cf 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -158,7 +158,12 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 - s->cpu =3D ARM_CPU(object_new(s->cpu_type)); + s->cpu =3D ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu", + &err, NULL)); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } =20 object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memor= y", &error_abort); --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548096986979281.9240299823989; Mon, 21 Jan 2019 10:56:26 -0800 (PST) Received: from localhost ([127.0.0.1]:58146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glejz-0004Wm-0F for importer@patchew.org; Mon, 21 Jan 2019 13:56:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35767) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glefQ-0000qv-0N for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefN-0002Yn-4G for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:27 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:39573) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefM-0002Vi-QW for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:25 -0500 Received: by mail-wr1-x442.google.com with SMTP id t27so24610627wra.6 for ; Mon, 21 Jan 2019 10:51:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WmmMPknEg5hUgKMPxj3CIX2ru0eV6+lHEZhIc4wzqM8=; b=kH4B50dshKqdlBEi6X0rMUGnH6egzwECFs6BSbOgtvrdRxemJY4HfY13l7SC5DYKHB 7OER1cxXNm7G6ztPQKqunG7Hnzaum2GCAifUl3gx/wr9h0pVFo3Z/e+uYtRevlhvoVhU vn+oclbjsas45TKGbePHHNtXJbMLFnYIQNe6w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WmmMPknEg5hUgKMPxj3CIX2ru0eV6+lHEZhIc4wzqM8=; b=iz95HZV3DAu4p47gS4wnYonRt1n+ceTACuPDIaKyAIX6FleHQd4p0GUPjjoDDO5n8m QLTRMElOdicTiN+OtDuBhcdTwsIsPaVSHUdFNf6wOENn85ikc+vKBk4zG6kptI6hUv1z nSIjCy1wEl4zuQixAgNmkB3OKxm153Xz75hw3HVZ4vD+wfHQTB8OvodjjMIPqFXMIYKz sPQCkMhwQrHHABxjvAK/kYyN19uKGopuFGgihvZMsVXoU29lUy/gCN2emq+E1jKdjeEb aPz3Z8FgeQsjte0laLCzIOoxCGD649BSoP/8iMB/OADUFP9kp5YnNUknC+06xhXkqT3/ 8/xQ== X-Gm-Message-State: AJcUukcKBfBNqouIWgnTDug3uPlnqrkP29T0QoVYngArBhz6IS+VX/Vs HGQMGuG/BMhiBTpi3oPZLArQr55XHj6/RA== X-Google-Smtp-Source: ALg8bN40GC0rRvzHIHkzbMX64/LuIT+NuKFgFmD8W/jqvnmInODPCvaQJF732AZaeVE/iazwYrb35g== X-Received: by 2002:adf:9f10:: with SMTP id l16mr30472796wrf.206.1548096683696; Mon, 21 Jan 2019 10:51:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:50:58 +0000 Message-Id: <20190121185118.18550-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 03/23] armv7m: Pass through start-powered-off CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armv7m.h | 1 + hw/arm/armv7m.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 2ba24953b63..e96a98f8093 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -65,6 +65,7 @@ typedef struct ARMv7MState { Object *idau; uint32_t init_svtor; bool enable_bitband; + bool start_powered_off; } ARMv7MState; =20 #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 0f2c8e066cf..adae11e76ed 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -182,6 +182,14 @@ static void armv7m_realize(DeviceState *dev, Error **e= rrp) return; } } + if (object_property_find(OBJECT(s->cpu), "start-powered-off", NULL)) { + object_property_set_bool(OBJECT(s->cpu), s->start_powered_off, + "start-powered-off", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + } =20 /* * Tell the CPU where the NVIC is; it will fail realize if it doesn't @@ -250,6 +258,8 @@ static Property armv7m_properties[] =3D { DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Objec= t *), DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), + DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, + false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548097174323535.976897000107; Mon, 21 Jan 2019 10:59:34 -0800 (PST) Received: from localhost ([127.0.0.1]:58183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glenB-0006bo-Bd for importer@patchew.org; Mon, 21 Jan 2019 13:59:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glefT-0000up-5l for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefR-0002cc-9E for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:31 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:35860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefP-0002ZL-CP for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:28 -0500 Received: by mail-wm1-x344.google.com with SMTP id p6so11831332wmc.1 for ; Mon, 21 Jan 2019 10:51:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GGm0EepQW4CpO+lX7AkPi0zjfoy2SviKPe3G9gGyJx4=; b=YfHdsCjizcCsLAbf3gRWn3IhWz6cr7bEgsgJZ5i8TntyhRbsku0wYrGqEssQ8pQZil eddIxA2AataA0XctefU7foeLALVWbyfB8o5DndIUuS7gzlgntPF/dff5UT0zY2om+D0x C3ka0sUv0MD2ewW1oSde3ipn16pc9TrSmVlbo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GGm0EepQW4CpO+lX7AkPi0zjfoy2SviKPe3G9gGyJx4=; b=K2RUbDF7B6Ls+TZQKZ6Fukq7UfywHC5gUbLE3XMSPxRtk2tSGyiOi10lWSAMQDgLX3 Nj1l5h+mEIGv0LoXfUrt12aFbjQXfxFscyz09+67nAC6yeCfHJRvuAcPq10NtK9CY6ze jB0J8OpSSy9pBDpzu+EWwSMn07isBM2yyBMjECF1xiJTCpgSORiVmnySafUsFABkJW1W T3V5gAfjBPKsmc9DZ2P5WHQm68mDBI6rwp3FuRCF/DWCkns51bM0h8KodajL7zcthIV1 rTiSTc/MoRnUjaAyNffN7uKkVWUBDsdNvddjiXRw6N5bD4CxAGDp6Ux5AQSRi6umnpgz wuVQ== X-Gm-Message-State: AJcUukfBGrbd/Ue0/7chnBH2qmOiatxQpuS+MQzAPLgmwOK5shH2Mn+B 5jCWpUWUid0/ia/7UZAF/iDQ1A== X-Google-Smtp-Source: ALg8bN711016e7xAdPfDdfrPAOv2gG4Z+q3H00wyb/F7iG6GLn/0KOaNk3vfJBnZjjTo++LQBdq59A== X-Received: by 2002:a1c:13d1:: with SMTP id 200mr577151wmt.4.1548096684911; Mon, 21 Jan 2019 10:51:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:50:59 +0000 Message-Id: <20190121185118.18550-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 04/23] hw/arm/iotkit: Rename IoTKit to ARMSSE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/arm/iotkit.h | 22 ++++++++++----- hw/arm/iotkit.c | 59 +++++++++++++++++++++-------------------- hw/arm/mps2-tz.c | 2 +- 3 files changed, 47 insertions(+), 36 deletions(-) diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h index 3a8ee639085..9701738ec75 100644 --- a/include/hw/arm/iotkit.h +++ b/include/hw/arm/iotkit.h @@ -1,5 +1,5 @@ /* - * ARM IoT Kit + * ARM SSE (Subsystems for Embedded): IoTKit * * Copyright (c) 2018 Linaro Limited * Written by Peter Maydell @@ -9,7 +9,10 @@ * (at your option) any later version. */ =20 -/* This is a model of the Arm IoT Kit which is documented in +/* + * This is a model of the Arm "Subsystems for Embedded" family of + * hardware, which include the IoT Kit and the SSE-050, SSE-100 and + * SSE-200. Currently we model only the Arm IoT Kit which is documented in * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html * It contains: * a Cortex-M33 @@ -71,8 +74,15 @@ #include "hw/or-irq.h" #include "hw/core/split-irq.h" =20 -#define TYPE_IOTKIT "iotkit" -#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) +#define TYPE_ARMSSE "iotkit" +#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) + +/* + * For the moment TYPE_IOTKIT is a synonym for TYPE_ARMSSE (and the + * latter's underlying name is left as "iotkit"); in a later + * commit it will become a subclass of TYPE_ARMSSE. + */ +#define TYPE_IOTKIT TYPE_ARMSSE =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs @@ -80,7 +90,7 @@ #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) =20 -typedef struct IoTKit { +typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; =20 @@ -131,6 +141,6 @@ typedef struct IoTKit { MemoryRegion *board_memory; uint32_t exp_numirq; uint32_t mainclk_frq; -} IoTKit; +} ARMSSE; =20 #endif diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c index 8742200fb42..9360053184e 100644 --- a/hw/arm/iotkit.c +++ b/hw/arm/iotkit.c @@ -1,5 +1,5 @@ /* - * Arm IoT Kit + * Arm SSE (Subsystems for Embedded): IoTKit * * Copyright (c) 2018 Linaro Limited * Written by Peter Maydell @@ -24,7 +24,7 @@ /* Create an alias region of @size bytes starting at @base * which mirrors the memory starting at @orig. */ -static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name, +static void make_alias(ARMSSE *s, MemoryRegion *mr, const char *name, hwaddr base, hwaddr size, hwaddr orig) { memory_region_init_alias(mr, NULL, name, &s->container, orig, size); @@ -41,18 +41,18 @@ static void irq_status_forwarder(void *opaque, int n, i= nt level) =20 static void nsccfg_handler(void *opaque, int n, int level) { - IoTKit *s =3D IOTKIT(opaque); + ARMSSE *s =3D ARMSSE(opaque); =20 s->nsccfg =3D level; } =20 -static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum) +static void iotkit_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) { /* Each of the 4 AHB and 4 APB PPCs that might be present in a - * system using the IoTKit has a collection of control lines which + * system using the ARMSSE has a collection of control lines which * are provided by the security controller and which we want to - * expose as control lines on the IoTKit device itself, so the - * code using the IoTKit can wire them up to the PPCs. + * expose as control lines on the ARMSSE device itself, so the + * code using the ARMSSE can wire them up to the PPCs. */ SplitIRQ *splitter =3D &s->ppc_irq_splitter[ppcnum]; DeviceState *iotkitdev =3D DEVICE(s); @@ -91,7 +91,7 @@ static void iotkit_forward_ppc(IoTKit *s, const char *ppc= name, int ppcnum) g_free(name); } =20 -static void iotkit_forward_sec_resp_cfg(IoTKit *s) +static void iotkit_forward_sec_resp_cfg(ARMSSE *s) { /* Forward the 3rd output from the splitter device as a * named GPIO output of the iotkit object. @@ -107,7 +107,7 @@ static void iotkit_forward_sec_resp_cfg(IoTKit *s) =20 static void iotkit_init(Object *obj) { - IoTKit *s =3D IOTKIT(obj); + ARMSSE *s =3D ARMSSE(obj); int i; =20 memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); @@ -175,20 +175,20 @@ static void iotkit_init(Object *obj) =20 static void iotkit_exp_irq(void *opaque, int n, int level) { - IoTKit *s =3D IOTKIT(opaque); + ARMSSE *s =3D ARMSSE(opaque); =20 qemu_set_irq(s->exp_irqs[n], level); } =20 static void iotkit_mpcexp_status(void *opaque, int n, int level) { - IoTKit *s =3D IOTKIT(opaque); + ARMSSE *s =3D ARMSSE(opaque); qemu_set_irq(s->mpcexp_status_in[n], level); } =20 static void iotkit_realize(DeviceState *dev, Error **errp) { - IoTKit *s =3D IOTKIT(dev); + ARMSSE *s =3D ARMSSE(dev); int i; MemoryRegion *mr; Error *err =3D NULL; @@ -215,9 +215,9 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) * devices exist in both address spaces but with hard-wired security * permissions that will cause the CPU to fault for non-secure accesse= s. * - * The IoTKit has an IDAU (Implementation Defined Access Unit), + * The ARMSSE has an IDAU (Implementation Defined Access Unit), * which specifies hard-wired security permissions for different - * areas of the physical address space. For the IoTKit IDAU, the + * areas of the physical address space. For the ARMSSE IDAU, the * top 4 bits of the physical address are the IDAU region ID, and * if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS * region, otherwise it is an S region. @@ -239,7 +239,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) * 0x20000000..0x2007ffff 32KB FPGA block RAM * 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff * 0x40000000..0x4000ffff base peripheral region 1 - * 0x40010000..0x4001ffff CPU peripherals (none for IoTKit) + * 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE) * 0x40020000..0x4002ffff system control element peripherals * 0x40080000..0x400fffff base peripheral region 2 * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff @@ -306,8 +306,8 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in); =20 /* The sec_resp_cfg output from the security controller must be split = into - * multiple lines, one for each of the PPCs within the IoTKit and one - * that will be an output from the IoTKit to the system. + * multiple lines, one for each of the PPCs within the ARMSSE and one + * that will be an output from the ARMSSE to the system. */ object_property_set_int(OBJECT(&s->sec_resp_splitter), 3, "num-lines", &err); @@ -475,7 +475,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) =20 /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ =20 - /* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region = */ + /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: * 0x4002f000: S32K timer */ @@ -558,7 +558,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000); =20 - /* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */ + /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */ =20 qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk= _frq); object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &er= r); @@ -678,7 +678,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) * Expose our container region to the board model; this corresponds * to the AHB Slave Expansion ports which allow bus master devices * (eg DMA controllers) in the board model to make transactions into - * devices in the IoTKit. + * devices in the ARMSSE. */ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container); =20 @@ -688,11 +688,12 @@ static void iotkit_realize(DeviceState *dev, Error **= errp) static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, int *iregion, bool *exempt, bool *ns, bool *= nsc) { - /* For IoTKit systems the IDAU responses are simple logical functions + /* + * For ARMSSE systems the IDAU responses are simple logical functions * of the address bits. The NSC attribute is guest-adjustable via the * NSCCFG register in the security controller. */ - IoTKit *s =3D IOTKIT(ii); + ARMSSE *s =3D ARMSSE(ii); int region =3D extract32(address, 28, 4); =20 *ns =3D !(region & 1); @@ -707,22 +708,22 @@ static const VMStateDescription iotkit_vmstate =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(nsccfg, IoTKit), + VMSTATE_UINT32(nsccfg, ARMSSE), VMSTATE_END_OF_LIST() } }; =20 static Property iotkit_properties[] =3D { - DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION, + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), DEFINE_PROP_END_OF_LIST() }; =20 static void iotkit_reset(DeviceState *dev) { - IoTKit *s =3D IOTKIT(dev); + ARMSSE *s =3D ARMSSE(dev); =20 s->nsccfg =3D 0; } @@ -740,9 +741,9 @@ static void iotkit_class_init(ObjectClass *klass, void = *data) } =20 static const TypeInfo iotkit_info =3D { - .name =3D TYPE_IOTKIT, + .name =3D TYPE_ARMSSE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(IoTKit), + .instance_size =3D sizeof(ARMSSE), .instance_init =3D iotkit_init, .class_init =3D iotkit_class_init, .interfaces =3D (InterfaceInfo[]) { diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 82b1d020a58..5824335b4fb 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -66,7 +66,7 @@ typedef struct { typedef struct { MachineState parent; =20 - IoTKit iotkit; + ARMSSE iotkit; MemoryRegion psram; MemoryRegion ssram[3]; MemoryRegion ssram1_m; --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098589924518.8995338632794; Mon, 21 Jan 2019 11:23:09 -0800 (PST) Received: from localhost ([127.0.0.1]:58563 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfA4-0003Gn-SQ for importer@patchew.org; Mon, 21 Jan 2019 14:23:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevW-000854-0H for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefT-0002dd-4k for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:32 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38971) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefR-0002bJ-72 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:29 -0500 Received: by mail-wm1-x342.google.com with SMTP id y8so11809649wmi.4 for ; Mon, 21 Jan 2019 10:51:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8/8nrDNxFDGGiKzCXqhPzki/Hbmqf6CuZf0plZpfE7M=; b=XvIAnboji2u7aobGX3RE5JSxCNVqGBP1JBOfYm4yjDB2ljtp5oDzEEj5FM9j/R0MAj K101rhiL0ot6tc63jnBc58PF8Ms+fwyTWhJ5eglyo36AGQ7GOliWyjIrz3pupx9xq+xA 4MPfHSveN1ZfpshNq1bLtyTo33sIhOMtEOTkk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8/8nrDNxFDGGiKzCXqhPzki/Hbmqf6CuZf0plZpfE7M=; b=BzgyW0aLScs74R0734NvW4T3kbYYAtl9kd52LBCw9XkmhEjufSFht6Xht4pNyh6dn2 gujfW+pEOXeB3jjxk9Ytur3G9DoiJZZp6O84eK/nIeHmQCnYPFzPvqpf05SySKWOmOpJ oNjn9S6xsbpWQqeYFkYAOIW97yg+yoPbREshc3IwOeJg8DvTJTOdxwhGIA116tYx8pRC 6DdaNQQR0/UYqONDPney7GyCCtWrB1PBxW2Uon0sgqoboabnHVv5BCNDiRzw0piOU+64 rovxFAvGNNG+KdPZ6yfugej7E/YkL1+Zdp/qfPnAAeAHb3w7joDm/NwWuRC84ijehgLI LcAg== X-Gm-Message-State: AJcUukchvqdbOwZH7w9v4X8Qei+UORHpU2wd33subRnSzry6Ky/cIot3 QKdF2m5Gg4Jj1cTxirAlutnASqj9FdqbfA== X-Google-Smtp-Source: ALg8bN5kpxoBDnrxq6W4QBbtu6bdfs7MHw+7Aw0d+QGJcxhu6iQAxf6VApidNoWtLVVn1tIdREl5ww== X-Received: by 2002:a1c:e913:: with SMTP id q19mr550689wmc.55.1548096686163; Mon, 21 Jan 2019 10:51:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:00 +0000 Message-Id: <20190121185118.18550-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 05/23] hw/arm/iotkit: Refactor into abstract base class and subclass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/arm/iotkit.h | 22 +++++++++++++++++----- hw/arm/iotkit.c | 34 +++++++++++++++++++++++++++++----- 2 files changed, 46 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/iotkit.h index 9701738ec75..521d1f73757 100644 --- a/include/hw/arm/iotkit.h +++ b/include/hw/arm/iotkit.h @@ -74,15 +74,15 @@ #include "hw/or-irq.h" #include "hw/core/split-irq.h" =20 -#define TYPE_ARMSSE "iotkit" +#define TYPE_ARMSSE "arm-sse" #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) =20 /* - * For the moment TYPE_IOTKIT is a synonym for TYPE_ARMSSE (and the - * latter's underlying name is left as "iotkit"); in a later - * commit it will become a subclass of TYPE_ARMSSE. + * These type names are for specific IoTKit subsystems; other than + * instantiating them, code using these devices should always handle + * them via the ARMSSE base class, so they have no IOTKIT() etc macros. */ -#define TYPE_IOTKIT TYPE_ARMSSE +#define TYPE_IOTKIT "iotkit" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs @@ -143,4 +143,16 @@ typedef struct ARMSSE { uint32_t mainclk_frq; } ARMSSE; =20 +typedef struct ARMSSEInfo ARMSSEInfo; + +typedef struct ARMSSEClass { + DeviceClass parent_class; + const ARMSSEInfo *info; +} ARMSSEClass; + +#define ARMSSE_CLASS(klass) \ + OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE) +#define ARMSSE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE) + #endif diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c index 9360053184e..d5b172933c3 100644 --- a/hw/arm/iotkit.c +++ b/hw/arm/iotkit.c @@ -18,6 +18,16 @@ #include "hw/arm/iotkit.h" #include "hw/arm/arm.h" =20 +struct ARMSSEInfo { + const char *name; +}; + +static const ARMSSEInfo armsse_variants[] =3D { + { + .name =3D TYPE_IOTKIT, + }, +}; + /* Clock frequency in HZ of the 32KHz "slow clock" */ #define S32KCLK (32 * 1000) =20 @@ -732,29 +742,43 @@ static void iotkit_class_init(ObjectClass *klass, voi= d *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(klass); + ARMSSEClass *asc =3D ARMSSE_CLASS(klass); =20 dc->realize =3D iotkit_realize; dc->vmsd =3D &iotkit_vmstate; dc->props =3D iotkit_properties; dc->reset =3D iotkit_reset; iic->check =3D iotkit_idau_check; + asc->info =3D data; } =20 -static const TypeInfo iotkit_info =3D { +static const TypeInfo armsse_info =3D { .name =3D TYPE_ARMSSE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(ARMSSE), .instance_init =3D iotkit_init, - .class_init =3D iotkit_class_init, + .abstract =3D true, .interfaces =3D (InterfaceInfo[]) { { TYPE_IDAU_INTERFACE }, { } } }; =20 -static void iotkit_register_types(void) +static void armsse_register_types(void) { - type_register_static(&iotkit_info); + int i; + + type_register_static(&armsse_info); + + for (i =3D 0; i < ARRAY_SIZE(armsse_variants); i++) { + TypeInfo ti =3D { + .name =3D armsse_variants[i].name, + .parent =3D TYPE_ARMSSE, + .class_init =3D iotkit_class_init, + .class_data =3D (void *)&armsse_variants[i], + }; + type_register(&ti); + } } =20 -type_init(iotkit_register_types); +type_init(armsse_register_types); --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548097946765856.5122538727613; Mon, 21 Jan 2019 11:12:26 -0800 (PST) Received: from localhost ([127.0.0.1]:58365 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glezh-0003Np-KD for importer@patchew.org; Mon, 21 Jan 2019 14:12:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gleui-0007jF-9f for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:07:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefT-0002dr-6j for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:32 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefR-0002bk-B9 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:31 -0500 Received: by mail-wr1-x444.google.com with SMTP id t6so24556309wrr.12 for ; Mon, 21 Jan 2019 10:51:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GwOkcaqB4nWlxWAy1SiSdUxzJLjM4/IN2mfdSNwClek=; b=NYRKVfhK0bl0+Rx6WK64jDuRfNTgKFq3Ifv/AFF9m3+CxYnmDg795Y6zahCpFxUgWI LZOq98MmawMUasCmvAvsmwwFeNsQ6kk6+8FqxGEx2mvvWFMgQzc+o5VJ51OGIkRc5lwn r6TY9shzKF/7d0q1VTHofuS24pMdG+iguf06w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GwOkcaqB4nWlxWAy1SiSdUxzJLjM4/IN2mfdSNwClek=; b=ABM8zn+tTwtxltcjpJrN/L6wAq6CP1gFXnwDG3DB4Js6rH9mRpP/yXjFiEnrRialse dlLz7XpLdAgnn7W+hb5OTj/nZKpTLycFB7AKi/s7sRaNpoU79gN4NJ3+59/1Foywuepv O1i/1U7swDyHE7FsB+nXsQIVDvCGbL1feETo7F0vnIvs9DUcDZ6BTwQ8cFXe/hBqjOrV /x9+eU+bFpCJbL8Iuxv+8iWiX9iWRWSgiQAKbez9bp+ZhLo0Gzv+78ZeoBTRO15rutap 5s57DqVv0PGG4O9025mpipaONT/5OuTYtFW3ikOVCSdDrQChq9F+vOM/b8P6NMVuFztj hHvQ== X-Gm-Message-State: AJcUukfII5oXc4TbUjy0KfPBEIX+fg88puNIQEd6zyLgZWG2ftKXRY+e yreOofnUaq+paxTguGU+jshUyQ== X-Google-Smtp-Source: ALg8bN6KOkKgflz9bGoxw4lJICGdOvQgAD9N9ZHfjAwub29cI487LsDpHB/T5orf8eK8JkQSUOBCkQ== X-Received: by 2002:adf:f848:: with SMTP id d8mr31169495wrq.178.1548096687479; Mon, 21 Jan 2019 10:51:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:01 +0000 Message-Id: <20190121185118.18550-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 06/23] hw/arm/iotkit: Rename 'iotkit' local variables and functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to 'armsse', for consistency. The remaining occurences are: * related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO, etc, which this refactor is not touching * references that apply specifically to the IoTKit (like the lack of a private CPU region) * the vmstate, which keeps its old "iotkit" name for migration compatibility reasons Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/iotkit.c | 68 ++++++++++++++++++++++++------------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c index d5b172933c3..7ff14fd5aef 100644 --- a/hw/arm/iotkit.c +++ b/hw/arm/iotkit.c @@ -56,7 +56,7 @@ static void nsccfg_handler(void *opaque, int n, int level) s->nsccfg =3D level; } =20 -static void iotkit_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) +static void armsse_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum) { /* Each of the 4 AHB and 4 APB PPCs that might be present in a * system using the ARMSSE has a collection of control lines which @@ -65,22 +65,22 @@ static void iotkit_forward_ppc(ARMSSE *s, const char *p= pcname, int ppcnum) * code using the ARMSSE can wire them up to the PPCs. */ SplitIRQ *splitter =3D &s->ppc_irq_splitter[ppcnum]; - DeviceState *iotkitdev =3D DEVICE(s); + DeviceState *armssedev =3D DEVICE(s); DeviceState *dev_secctl =3D DEVICE(&s->secctl); DeviceState *dev_splitter =3D DEVICE(splitter); char *name; =20 name =3D g_strdup_printf("%s_nonsec", ppcname); - qdev_pass_gpios(dev_secctl, iotkitdev, name); + qdev_pass_gpios(dev_secctl, armssedev, name); g_free(name); name =3D g_strdup_printf("%s_ap", ppcname); - qdev_pass_gpios(dev_secctl, iotkitdev, name); + qdev_pass_gpios(dev_secctl, armssedev, name); g_free(name); name =3D g_strdup_printf("%s_irq_enable", ppcname); - qdev_pass_gpios(dev_secctl, iotkitdev, name); + qdev_pass_gpios(dev_secctl, armssedev, name); g_free(name); name =3D g_strdup_printf("%s_irq_clear", ppcname); - qdev_pass_gpios(dev_secctl, iotkitdev, name); + qdev_pass_gpios(dev_secctl, armssedev, name); g_free(name); =20 /* irq_status is a little more tricky, because we need to @@ -96,15 +96,15 @@ static void iotkit_forward_ppc(ARMSSE *s, const char *p= pcname, int ppcnum) qdev_connect_gpio_out(dev_splitter, 1, qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), ppc= num)); s->irq_status_in[ppcnum] =3D qdev_get_gpio_in(dev_splitter, 0); - qdev_init_gpio_in_named_with_opaque(iotkitdev, irq_status_forwarder, + qdev_init_gpio_in_named_with_opaque(armssedev, irq_status_forwarder, s->irq_status_in[ppcnum], name, 1); g_free(name); } =20 -static void iotkit_forward_sec_resp_cfg(ARMSSE *s) +static void armsse_forward_sec_resp_cfg(ARMSSE *s) { /* Forward the 3rd output from the splitter device as a - * named GPIO output of the iotkit object. + * named GPIO output of the armsse object. */ DeviceState *dev =3D DEVICE(s); DeviceState *dev_splitter =3D DEVICE(&s->sec_resp_splitter); @@ -115,12 +115,12 @@ static void iotkit_forward_sec_resp_cfg(ARMSSE *s) qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in); } =20 -static void iotkit_init(Object *obj) +static void armsse_init(Object *obj) { ARMSSE *s =3D ARMSSE(obj); int i; =20 - memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M); @@ -160,9 +160,9 @@ static void iotkit_init(Object *obj) sizeof(s->nswatchdog), TYPE_CMSDK_APB_WATCHDOG); sysbus_init_child_obj(obj, "swatchdog", &s->swatchdog, sizeof(s->swatchdog), TYPE_CMSDK_APB_WATCHDOG); - sysbus_init_child_obj(obj, "iotkit-sysctl", &s->sysctl, + sysbus_init_child_obj(obj, "armsse-sysctl", &s->sysctl, sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); - sysbus_init_child_obj(obj, "iotkit-sysinfo", &s->sysinfo, + sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, @@ -183,20 +183,20 @@ static void iotkit_init(Object *obj) } } =20 -static void iotkit_exp_irq(void *opaque, int n, int level) +static void armsse_exp_irq(void *opaque, int n, int level) { ARMSSE *s =3D ARMSSE(opaque); =20 qemu_set_irq(s->exp_irqs[n], level); } =20 -static void iotkit_mpcexp_status(void *opaque, int n, int level) +static void armsse_mpcexp_status(void *opaque, int n, int level) { ARMSSE *s =3D ARMSSE(opaque); qemu_set_irq(s->mpcexp_status_in[n], level); } =20 -static void iotkit_realize(DeviceState *dev, Error **errp) +static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARMSSE(dev); int i; @@ -287,7 +287,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) for (i =3D 0; i < s->exp_numirq; i++) { s->exp_irqs[i] =3D qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); } - qdev_init_gpio_in_named(dev, iotkit_exp_irq, "EXP_IRQ", s->exp_numirq); + qdev_init_gpio_in_named(dev, armsse_exp_irq, "EXP_IRQ", s->exp_numirq); =20 /* Set up the big aliases first */ make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x0000000= 0); @@ -336,7 +336,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) qdev_get_gpio_in(dev_splitter, 0)); =20 /* This RAM lives behind the Memory Protection Controller */ - memory_region_init_ram(&s->sram0, NULL, "iotkit.sram0", 0x00008000, &e= rr); + memory_region_init_ram(&s->sram0, NULL, "armsse.sram0", 0x00008000, &e= rr); if (err) { error_propagate(errp, err); return; @@ -608,14 +608,14 @@ static void iotkit_realize(DeviceState *dev, Error **= errp) for (i =3D 0; i < IOTS_NUM_AHB_EXP_PPC; i++) { char *ppcname =3D g_strdup_printf("ahb_ppcexp%d", i); =20 - iotkit_forward_ppc(s, ppcname, i); + armsse_forward_ppc(s, ppcname, i); g_free(ppcname); } =20 for (i =3D 0; i < IOTS_NUM_APB_EXP_PPC; i++) { char *ppcname =3D g_strdup_printf("apb_ppcexp%d", i); =20 - iotkit_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); + armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC); g_free(ppcname); } =20 @@ -672,10 +672,10 @@ static void iotkit_realize(DeviceState *dev, Error **= errp) /* Create GPIO inputs which will pass the line state for our * mpcexp_irq inputs to the correct splitter devices. */ - qdev_init_gpio_in_named(dev, iotkit_mpcexp_status, "mpcexp_status", + qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status", IOTS_NUM_EXP_MPC); =20 - iotkit_forward_sec_resp_cfg(s); + armsse_forward_sec_resp_cfg(s); =20 /* Forward the MSC related signals */ qdev_pass_gpios(dev_secctl, dev, "mscexp_status"); @@ -695,7 +695,7 @@ static void iotkit_realize(DeviceState *dev, Error **er= rp) system_clock_scale =3D NANOSECONDS_PER_SECOND / s->mainclk_frq; } =20 -static void iotkit_idau_check(IDAUInterface *ii, uint32_t address, +static void armsse_idau_check(IDAUInterface *ii, uint32_t address, int *iregion, bool *exempt, bool *ns, bool *= nsc) { /* @@ -713,7 +713,7 @@ static void iotkit_idau_check(IDAUInterface *ii, uint32= _t address, *iregion =3D region; } =20 -static const VMStateDescription iotkit_vmstate =3D { +static const VMStateDescription armsse_vmstate =3D { .name =3D "iotkit", .version_id =3D 1, .minimum_version_id =3D 1, @@ -723,7 +723,7 @@ static const VMStateDescription iotkit_vmstate =3D { } }; =20 -static Property iotkit_properties[] =3D { +static Property armsse_properties[] =3D { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), @@ -731,24 +731,24 @@ static Property iotkit_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -static void iotkit_reset(DeviceState *dev) +static void armsse_reset(DeviceState *dev) { ARMSSE *s =3D ARMSSE(dev); =20 s->nsccfg =3D 0; } =20 -static void iotkit_class_init(ObjectClass *klass, void *data) +static void armsse_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(klass); ARMSSEClass *asc =3D ARMSSE_CLASS(klass); =20 - dc->realize =3D iotkit_realize; - dc->vmsd =3D &iotkit_vmstate; - dc->props =3D iotkit_properties; - dc->reset =3D iotkit_reset; - iic->check =3D iotkit_idau_check; + dc->realize =3D armsse_realize; + dc->vmsd =3D &armsse_vmstate; + dc->props =3D armsse_properties; + dc->reset =3D armsse_reset; + iic->check =3D armsse_idau_check; asc->info =3D data; } =20 @@ -756,7 +756,7 @@ static const TypeInfo armsse_info =3D { .name =3D TYPE_ARMSSE, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(ARMSSE), - .instance_init =3D iotkit_init, + .instance_init =3D armsse_init, .abstract =3D true, .interfaces =3D (InterfaceInfo[]) { { TYPE_IDAU_INTERFACE }, @@ -774,7 +774,7 @@ static void armsse_register_types(void) TypeInfo ti =3D { .name =3D armsse_variants[i].name, .parent =3D TYPE_ARMSSE, - .class_init =3D iotkit_class_init, + .class_init =3D armsse_class_init, .class_data =3D (void *)&armsse_variants[i], }; type_register(&ti); --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098017078260.0314068072905; Mon, 21 Jan 2019 11:13:37 -0800 (PST) Received: from localhost ([127.0.0.1]:58375 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf0e-0004Bd-RR for importer@patchew.org; Mon, 21 Jan 2019 14:13:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevU-0007jF-Mk for qemu-devel@nongnu.org; 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X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 07/23] hw/arm/iotkit: Rename files to hw/arm/armsse.[ch] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/Makefile.objs | 2 +- include/hw/arm/{iotkit.h =3D> armsse.h} | 4 ++-- hw/arm/{iotkit.c =3D> armsse.c} | 2 +- hw/arm/mps2-tz.c | 2 +- MAINTAINERS | 4 ++-- default-configs/arm-softmmu.mak | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) rename include/hw/arm/{iotkit.h =3D> armsse.h} (99%) rename hw/arm/{iotkit.c =3D> armsse.c} (99%) diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 50c7b4a927d..22b7f0ed0ba 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -34,7 +34,7 @@ obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) +=3D mps2.o obj-$(CONFIG_MPS2) +=3D mps2-tz.o obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o -obj-$(CONFIG_IOTKIT) +=3D iotkit.o +obj-$(CONFIG_ARMSSE) +=3D armsse.o obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) +=3D smmu-common.o smmuv3.o obj-$(CONFIG_FSL_IMX6UL) +=3D fsl-imx6ul.o mcimx6ul-evk.o diff --git a/include/hw/arm/iotkit.h b/include/hw/arm/armsse.h similarity index 99% rename from include/hw/arm/iotkit.h rename to include/hw/arm/armsse.h index 521d1f73757..ff512054988 100644 --- a/include/hw/arm/iotkit.h +++ b/include/hw/arm/armsse.h @@ -58,8 +58,8 @@ * + named GPIO outputs mscexp_ns[0..15] */ =20 -#ifndef IOTKIT_H -#define IOTKIT_H +#ifndef ARMSSE_H +#define ARMSSE_H =20 #include "hw/sysbus.h" #include "hw/arm/armv7m.h" diff --git a/hw/arm/iotkit.c b/hw/arm/armsse.c similarity index 99% rename from hw/arm/iotkit.c rename to hw/arm/armsse.c index 7ff14fd5aef..8554be14128 100644 --- a/hw/arm/iotkit.c +++ b/hw/arm/armsse.c @@ -15,7 +15,7 @@ #include "trace.h" #include "hw/sysbus.h" #include "hw/registerfields.h" -#include "hw/arm/iotkit.h" +#include "hw/arm/armsse.h" #include "hw/arm/arm.h" =20 struct ARMSSEInfo { diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 5824335b4fb..3859f17d98b 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -46,7 +46,7 @@ #include "hw/misc/mps2-fpgaio.h" #include "hw/misc/tz-mpc.h" #include "hw/misc/tz-msc.h" -#include "hw/arm/iotkit.h" +#include "hw/arm/armsse.h" #include "hw/dma/pl080.h" #include "hw/ssi/pl022.h" #include "hw/devices.h" diff --git a/MAINTAINERS b/MAINTAINERS index af339b86db7..52222117d77 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -625,8 +625,8 @@ F: hw/arm/mps2.c F: hw/arm/mps2-tz.c F: hw/misc/mps2-*.c F: include/hw/misc/mps2-*.h -F: hw/arm/iotkit.c -F: include/hw/arm/iotkit.h +F: hw/arm/armsse.c +F: include/hw/arm/armsse.h F: hw/misc/iotkit-secctl.c F: include/hw/misc/iotkit-secctl.h F: hw/misc/iotkit-sysctl.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 2420491aacd..3f200157879 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -114,7 +114,7 @@ CONFIG_MPS2_SCC=3Dy CONFIG_TZ_MPC=3Dy CONFIG_TZ_MSC=3Dy CONFIG_TZ_PPC=3Dy -CONFIG_IOTKIT=3Dy +CONFIG_ARMSSE=3Dy CONFIG_IOTKIT_SECCTL=3Dy CONFIG_IOTKIT_SYSCTL=3Dy CONFIG_IOTKIT_SYSINFO=3Dy --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098576701526.6532228127896; Mon, 21 Jan 2019 11:22:56 -0800 (PST) Received: from localhost ([127.0.0.1]:58561 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf9r-00039L-JB for importer@patchew.org; Mon, 21 Jan 2019 14:22:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevU-0008OH-10 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefe-0002sL-M6 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:44 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:42972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefe-0002d3-Eo for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:42 -0500 Received: by mail-wr1-x442.google.com with SMTP id q18so24571077wrx.9 for ; Mon, 21 Jan 2019 10:51:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NyOzJo6HdhqirSo4FTNN+HWWChIIYH9S1hj1nxz1Els=; b=emaPeNzZfiytvchph1Vs4rV0jasLnMCz6Otco+zPhu8DUgwpls2bYG/kT3lx72wYme O3sceL8DhdZAM5NH4XLjCOAzNE6POmWlzSNyINL7L8hYBzSt3bIFFoV16Tiiv+pfVKOx 76I+JzpWLzw0yZKrlK29K4t/N9E7OeyKAqr0g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NyOzJo6HdhqirSo4FTNN+HWWChIIYH9S1hj1nxz1Els=; b=gIk7UVYMxKv9JZaaCmNS5J7+cLygzxa5jChMOEM9jmXdHwLm2fAjwSmYvP3eDskqLR whxym9NlD/cvAITptvxHBNqJVpI1Fhl6PdjMbcJE9UWLonDF7g11oZiPpC0eE6H1xQjz +Bj34IwF7sbhdbseaL2EZuZFThDhwEWQes883kbfciiTvu/bW2dRfBninDqmIH4j7Yfv C6iNF0BcTr661PTQ2ufd/xfaDLXq0QPYwzERx67DC0wvTYAZS37Fxw0mCfKOSf/VhMU5 eQo8G2scNs1hMFy2Wf4wI1gkohqX+YGi2cXiO+AgQDhkmVzmHIkPJ8Uj18eV0hAh+pM8 Ah2w== X-Gm-Message-State: AJcUukfXA3MnIi7i5lpkaZ5T8d+AwHlB0yg6cHlEILsTN8dhwS1pH+ke b17JCIc9fre+jS1vaah3ZkWFITRGyAcwbA== X-Google-Smtp-Source: ALg8bN49KtCxV3r66NgbjoNAW/HZTvij1jmLbBdZ76o5a1eSjVF0b0l5ie+G6Lo9ooS6pyKJTGswbw== X-Received: by 2002:a5d:678b:: with SMTP id v11mr31458990wru.245.1548096689601; Mon, 21 Jan 2019 10:51:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:03 +0000 Message-Id: <20190121185118.18550-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 08/23] hw/misc/iotkit-secctl: Support 4 internal MPCs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-secctl.h | 6 +++--- hw/arm/armsse.c | 6 +++--- hw/misc/iotkit-secctl.c | 5 +++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct= l.h index 1a193b306f1..bcb0437be5b 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -40,8 +40,8 @@ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status - * Controlling the MPC in the IoTKit: - * + named GPIO input mpc_status + * Controlling the (up to) 4 MPCs in the IoTKit/SSE: + * + named GPIO inputs mpc_status[0..3] * Controlling each of the 16 expansion MPCs which a system using the IoTK= it * might provide: * + named GPIO inputs mpcexp_status[0..15] @@ -67,7 +67,7 @@ #define IOTS_NUM_APB_EXP_PPC 4 #define IOTS_NUM_AHB_EXP_PPC 4 #define IOTS_NUM_EXP_MPC 16 -#define IOTS_NUM_MPC 1 +#define IOTS_NUM_MPC 4 #define IOTS_NUM_EXP_MSC 16 =20 typedef struct IoTKitSecCtl IoTKitSecCtl; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 8554be14128..074c1d3a6cf 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -138,7 +138,7 @@ static void armsse_init(Object *obj) sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, &error_abort, NULL); =20 - for (i =3D 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { char *name =3D g_strdup_printf("mpc-irq-splitter-%d", i); SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; =20 @@ -363,7 +363,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) =20 /* We must OR together lines from the MPC splitters to go to the NVIC = */ object_property_set_int(OBJECT(&s->mpc_irq_orgate), - IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", = &err); + IOTS_NUM_EXP_MPC + 1, "num-lines", &err); if (err) { error_propagate(errp, err); return; @@ -636,7 +636,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } =20 /* Wire up the splitters for the MPC IRQs */ - for (i =3D 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; DeviceState *dev_splitter =3D DEVICE(splitter); =20 diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 2222b3e147d..537601cd53f 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -600,7 +600,7 @@ static void iotkit_secctl_mpc_status(void *opaque, int = n, int level) { IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque); =20 - s->mpcintstatus =3D deposit32(s->mpcintstatus, 0, 1, !!level); + s->mpcintstatus =3D deposit32(s->mpcintstatus, n, 1, !!level); } =20 static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level) @@ -686,7 +686,8 @@ static void iotkit_secctl_init(Object *obj) qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); =20 - qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1= ); + qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", + IOTS_NUM_MPC); qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status, "mpcexp_status", IOTS_NUM_EXP_MPC); =20 --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098919566747.4760699246522; Mon, 21 Jan 2019 11:28:39 -0800 (PST) Received: from localhost ([127.0.0.1]:58649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfFO-0007dt-FE for importer@patchew.org; Mon, 21 Jan 2019 14:28:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevU-0008Da-D5 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefa-0002qQ-MP for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:40 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39575) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefY-0002e8-V7 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:37 -0500 Received: by mail-wr1-x444.google.com with SMTP id t27so24610974wra.6 for ; Mon, 21 Jan 2019 10:51:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rmaI+kkyf9uJRswykyw1+Rfz8wtF0OuwFSjC/Eb5qSY=; b=NgT4LneBBMvw0kDkLDvSpQiBIPRjr8l2M2Cq2zUTQi7FHfUoqM0f5LEX4QOQK0mCtz VI4zl206m5KIxK5jbs3zo5fTaf3aR0b5rXW52vw9sm/zQtwD3+uriaJzIAFsfNsa7fWu WpqX14k+wA6xc6APHOINQ+YZeMESM5cjSqfjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rmaI+kkyf9uJRswykyw1+Rfz8wtF0OuwFSjC/Eb5qSY=; b=LhK/PDUePrr24MTkxnhstOE9TfGea3dhTMfSc5xmOA9YNsveFNJyNN3Nn6JpW7D+xg 7sZhHvxez6Z1Q1p2rGA5UmfrFqcC867wa9CWFZaiexQaBCDhi0a/rqHpolJ63515h2ri duGqenexm45rG1ekFFItp4xHMIgCHcMIxDevVponQmMmkMOEVCK1KLOWR7Z68IwpCn1I xQNLS84LPeZhN33o11NpAPMn+5o7RFA/WEL4JPeA5OWNShNvjaV1Pfyfa5VmumMYq3uU t3nGt/vT1Kbr7VmfMHIq1u7IfA+oWw/EvbyRlDQEmWjK8i603N82cCaXL3hmw/AMLJ7W MI6g== X-Gm-Message-State: AJcUukcJxgZRTbv2VN/Q4udqu+WMkb1GdSb/UaSfdfp5/8voxpEL/szX P5WJ/wNA6LUVTqeNoyxEtHWnNCrlbpi1Aw== X-Google-Smtp-Source: ALg8bN6UcskssWrZ30dPS0LT9CAknEuHbcAur8fuiXFyNUwUYQcXGgt0xr86OU9HS4jqmGxRBpVOBg== X-Received: by 2002:adf:ea11:: with SMTP id q17mr28257724wrm.328.1548096690792; Mon, 21 Jan 2019 10:51:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:04 +0000 Message-Id: <20190121185118.18550-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 09/23] hw/arm/armsse: Make number of SRAM banks parameterised X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 9 +++-- hw/arm/armsse.c | 78 ++++++++++++++++++++++++++--------------- 2 files changed, 56 insertions(+), 31 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index ff512054988..99714aa63cd 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -90,6 +90,11 @@ #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) =20 +#define MAX_SRAM_BANKS 4 +#if MAX_SRAM_BANKS > IOTS_NUM_MPC +#error Too many SRAM banks +#endif + typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -99,7 +104,7 @@ typedef struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; - TZMPC mpc; + TZMPC mpc[IOTS_NUM_MPC]; CMSDKAPBTIMER timer0; CMSDKAPBTIMER timer1; CMSDKAPBTIMER s32ktimer; @@ -123,7 +128,7 @@ typedef struct ARMSSE { MemoryRegion alias1; MemoryRegion alias2; MemoryRegion alias3; - MemoryRegion sram0; + MemoryRegion sram[MAX_SRAM_BANKS]; =20 qemu_irq *exp_irqs; qemu_irq ppc0_irq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 074c1d3a6cf..b639b54e0db 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -20,11 +20,13 @@ =20 struct ARMSSEInfo { const char *name; + int sram_banks; }; =20 static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, + .sram_banks =3D 1, }, }; =20 @@ -118,8 +120,12 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s) static void armsse_init(Object *obj) { ARMSSE *s =3D ARMSSE(obj); + ARMSSEClass *asc =3D ARMSSE_GET_CLASS(obj); + const ARMSSEInfo *info =3D asc->info; int i; =20 + assert(info->sram_banks <=3D MAX_SRAM_BANKS); + memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), @@ -133,12 +139,17 @@ static void armsse_init(Object *obj) TYPE_TZ_PPC); sysbus_init_child_obj(obj, "apb-ppc1", &s->apb_ppc1, sizeof(s->apb_ppc= 1), TYPE_TZ_PPC); - sysbus_init_child_obj(obj, "mpc", &s->mpc, sizeof(s->mpc), TYPE_TZ_MPC= ); + for (i =3D 0; i < info->sram_banks; i++) { + char *name =3D g_strdup_printf("mpc%d", i); + sysbus_init_child_obj(obj, name, &s->mpc[i], + sizeof(s->mpc[i]), TYPE_TZ_MPC); + g_free(name); + } object_initialize_child(obj, "mpc-irq-orgate", &s->mpc_irq_orgate, sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, &error_abort, NULL); =20 - for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { char *name =3D g_strdup_printf("mpc-irq-splitter-%d", i); SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; =20 @@ -199,6 +210,8 @@ static void armsse_mpcexp_status(void *opaque, int n, i= nt level) static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARMSSE(dev); + ARMSSEClass *asc =3D ARMSSE_GET_CLASS(dev); + const ARMSSEInfo *info =3D asc->info; int i; MemoryRegion *mr; Error *err =3D NULL; @@ -335,35 +348,41 @@ static void armsse_realize(DeviceState *dev, Error **= errp) qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); =20 - /* This RAM lives behind the Memory Protection Controller */ - memory_region_init_ram(&s->sram0, NULL, "armsse.sram0", 0x00008000, &e= rr); - if (err) { - error_propagate(errp, err); - return; + /* Each SRAM bank lives behind its own Memory Protection Controller */ + for (i =3D 0; i < info->sram_banks; i++) { + char *ramname =3D g_strdup_printf("armsse.sram%d", i); + SysBusDevice *sbd_mpc; + + memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &er= r); + g_free(ramname); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_link(OBJECT(&s->mpc[i]), OBJECT(&s->sram[i]), + "downstream", &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->mpc[i]), true, "realized", &er= r); + if (err) { + error_propagate(errp, err); + return; + } + /* Map the upstream end of the MPC into the right place... */ + sbd_mpc =3D SYS_BUS_DEVICE(&s->mpc[i]); + memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000, + sysbus_mmio_get_region(sbd_mpc, 1)); + /* ...and its register interface */ + memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, + sysbus_mmio_get_region(sbd_mpc, 0)); } - object_property_set_link(OBJECT(&s->mpc), OBJECT(&s->sram0), - "downstream", &err); - if (err) { - error_propagate(errp, err); - return; - } - object_property_set_bool(OBJECT(&s->mpc), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } - /* Map the upstream end of the MPC into the right place... */ - memory_region_add_subregion(&s->container, 0x20000000, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= mpc), - 1)); - /* ...and its register interface */ - memory_region_add_subregion(&s->container, 0x50083000, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->= mpc), - 0)); =20 /* We must OR together lines from the MPC splitters to go to the NVIC = */ object_property_set_int(OBJECT(&s->mpc_irq_orgate), - IOTS_NUM_EXP_MPC + 1, "num-lines", &err); + IOTS_NUM_EXP_MPC + info->sram_banks, + "num-lines", &err); if (err) { error_propagate(errp, err); return; @@ -636,7 +655,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } =20 /* Wire up the splitters for the MPC IRQs */ - for (i =3D 0; i < IOTS_NUM_EXP_MPC + 1; i++) { + for (i =3D 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) { SplitIRQ *splitter =3D &s->mpc_irq_splitter[i]; DeviceState *dev_splitter =3D DEVICE(splitter); =20 @@ -659,7 +678,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) "mpcexp_status", = i)); } else { /* Splitter input is from our own MPC */ - qdev_connect_gpio_out_named(DEVICE(&s->mpc), "irq", 0, + qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MP= C]), + "irq", 0, qdev_get_gpio_in(dev_splitter, 0)); qdev_connect_gpio_out(dev_splitter, 0, qdev_get_gpio_in_named(dev_secctl, --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZtglysStG0tXIkc7Lj+My+7b7XqiO1d9EdiWVYmU19M=; b=ZMdYJmqzA5/BcWiQm8dp6Y66h5RsB/6WGQZ6Uk6pgVk1JEReUlPo7fupO4z0o2YNxA Ie7svBsqsr5CU2IvQ2/w8aV80Eymgqel6wyFcc2nyhwbklU79jDpfUXeuu6nrn+hRd21 BOyNKJIjrV8gfpfmEJgJeGL4OuQPaPmti0yCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZtglysStG0tXIkc7Lj+My+7b7XqiO1d9EdiWVYmU19M=; b=Gc8wjQXdk7rjcVq0X4H7gu71hPoNvcYX3L+rTHxfgfXJoDqKlI/IU/EYUBcSx7k7UK ASalf+mSwUXy9t6K6L6AURXq3k5TMCJD9Hl0TC0LAgHeqAa/m0tun8A4pGI1KIfo+XOy tkGwW05MGz1r5fvQMQ7hrKny5+Z+V2wOqpItrBtu17/5Q7d+KAF3HU64Lq8ExCCO1lyJ eHKjm5q7dDTYNVzHfeYbp4lZGMsN7CLqcCKO3xZBVr3t9QvMWbIC7q9erdUQf8U3dPCa dLRfuv90FkW995ZVp1YDANMjSN2qUSz3BT7NVPDE2zbZ9mX00S5QQpjGY9qMPnMAmyva SghA== X-Gm-Message-State: AJcUukf8Dwn1mxw9vdoHWDb8fepZ5k/ddhZ+Y8/mPiW6ZB6fj/QAZVKA zCAJWvUZQnSmyQSjYv3tR9Ilkg== X-Google-Smtp-Source: ALg8bN6eONj0omW2Km1lqm7d3AhBgeoePlM6hLj85GNaoo8xG2UX1CLOX4be8/Ji9Tq9Y4bYw5yPOA== X-Received: by 2002:a7b:c44d:: with SMTP id l13mr578253wmi.144.1548096691956; Mon, 21 Jan 2019 10:51:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:05 +0000 Message-Id: <20190121185118.18550-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 10/23] hw/arm/armsse: Make SRAM bank size configurable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 99714aa63cd..e4a05013316 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -146,6 +146,7 @@ typedef struct ARMSSE { MemoryRegion *board_memory; uint32_t exp_numirq; uint32_t mainclk_frq; + uint32_t sram_addr_width; } ARMSSE; =20 typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index b639b54e0db..a2ae5d3c4b9 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -221,6 +221,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) DeviceState *dev_apb_ppc1; DeviceState *dev_secctl; DeviceState *dev_splitter; + uint32_t addr_width_max; =20 if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -232,6 +233,15 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } =20 + /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */ + assert(is_power_of_2(info->sram_banks)); + addr_width_max =3D 24 - ctz32(info->sram_banks); + if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) { + error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d", + addr_width_max); + return; + } + /* Handling of which devices should be available only to secure * code is usually done differently for M profile than for A profile. * Instead of putting some devices only into the secure address space, @@ -352,8 +362,10 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) for (i =3D 0; i < info->sram_banks; i++) { char *ramname =3D g_strdup_printf("armsse.sram%d", i); SysBusDevice *sbd_mpc; + uint32_t sram_bank_size =3D 1 << s->sram_addr_width; =20 - memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &er= r); + memory_region_init_ram(&s->sram[i], NULL, ramname, + sram_bank_size, &err); g_free(ramname); if (err) { error_propagate(errp, err); @@ -372,7 +384,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) } /* Map the upstream end of the MPC into the right place... */ sbd_mpc =3D SYS_BUS_DEVICE(&s->mpc[i]); - memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000, + memory_region_add_subregion(&s->container, + 0x20000000 + i * sram_bank_size, sysbus_mmio_get_region(sbd_mpc, 1)); /* ...and its register interface */ memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, @@ -748,6 +761,7 @@ static Property armsse_properties[] =3D { MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098302570322.06551456841123; Mon, 21 Jan 2019 11:18:22 -0800 (PST) Received: from localhost ([127.0.0.1]:58484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf5R-0008CZ-6I for importer@patchew.org; Mon, 21 Jan 2019 14:18:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevN-0008Da-W8 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002uj-Qt for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:49 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38678) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gleff-0002fY-Dx for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wr1-x42c.google.com with SMTP id v13so24619441wrw.5 for ; Mon, 21 Jan 2019 10:51:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ERgJG9PhtMoyjC++bigjOAZTdVMBDVouJXesxc5aBKU=; b=Nbmar4Ta2YoevbRAXWViDayhj3522vcuqTNxt5Ir0Og/25a15O8haSV24npiZfiDJQ zygnLbMgJgOIp7m4pyoVVno7G88GFzgk+mIhpT/1m0TdRrbAiNlKGcZC/hklxZr7wjpH p/Hy8trwsC9eymAItvjO5j49jykp8l67dYvdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ERgJG9PhtMoyjC++bigjOAZTdVMBDVouJXesxc5aBKU=; b=UTbh5obNFpCFFWEai5WeHiSq90bfI32B18I0/Cu8lYmEaDvcwDo2/kdDKwomiUW5FF Iz0rgKZszuzWthj1BF6yVqxPBqQWO5CZGwrJaeA7OaM+ZY0nO5hcT9vSqZZ1GI3erF3L HqMoh6jsoyJAhrju0AxftMO7hiYCMEaBvnNzfLtnMm7d+v4scTvFWvOrV8GMN0CbwTwB sIpL01lsacbERJOMQGBFwbK+yW8i9PJWA37ntEMK01dzdUPzp5f4aiMR9o1CGvq2ga3a 3fS4C/nMFX7EaPIrTllC1MINgGGWUEoE1fxkqcldoZWcu8gFQ5w9bX6wHnw4yXquKFtS hhJw== X-Gm-Message-State: AJcUukeuDUktGz+TWm9xVEJQQ8vYd3WwvQnGZPbMmcLX1rS1MSzFzSde wuWRxbBUGcLd34IRbjD68E1HxVBdPv0zjQ== X-Google-Smtp-Source: ALg8bN5X5LXwQAmTOOhHIcdUYpKwWALKF+y5R9cFQ/bQ7rd/OHcuI1E9sm9lNGj/AjmWzEPoAUcbSQ== X-Received: by 2002:adf:9f10:: with SMTP id l16mr30473325wrf.206.1548096693322; Mon, 21 Jan 2019 10:51:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:06 +0000 Message-Id: <20190121185118.18550-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PATCH 11/23] hw/arm/armsse: Support dual-CPU configuration X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 21 +++- hw/arm/armsse.c | 206 ++++++++++++++++++++++++++++++++-------- 2 files changed, 180 insertions(+), 47 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index e4a05013316..faf5dfed252 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -28,9 +28,16 @@ * + QOM property "memory" is a MemoryRegion containing the devices provi= ded * by the board model. * + QOM property "MAINCLK" is the frequency of the main system clock - * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts - * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which - * are wired to the NVIC lines 32 .. n+32 + * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. + * (In hardware, the SSE-200 permits the number of expansion interrupts + * for the two CPUs to be configured separately, but we restrict it to + * being the same for both, to avoid having to have separate Property + * lists for different variants. This restriction can be relaxed later + * if necessary.) + * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CP= U 0, + * which are wired to its NVIC lines 32 .. n+32 + * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts f= or + * CPU 1, which are wired to its NVIC lines 32 .. n+32 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows * bus master devices in the board model to make transactions into * all the devices and memory areas in the IoTKit @@ -95,12 +102,14 @@ #error Too many SRAM banks #endif =20 +#define SSE_MAX_CPUS 2 + typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ - ARMv7MState armv7m; + ARMv7MState armv7m[SSE_MAX_CPUS]; IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; @@ -115,6 +124,8 @@ typedef struct ARMSSE { qemu_or_irq mpc_irq_orgate; qemu_or_irq nmi_orgate; =20 + SplitIRQ cpu_irq_splitter[32]; + CMSDKAPBDualTimer dualtimer; =20 CMSDKAPBWatchdog s32kwatchdog; @@ -130,7 +141,7 @@ typedef struct ARMSSE { MemoryRegion alias3; MemoryRegion sram[MAX_SRAM_BANKS]; =20 - qemu_irq *exp_irqs; + qemu_irq *exp_irqs[SSE_MAX_CPUS]; qemu_irq ppc0_irq; qemu_irq ppc1_irq; qemu_irq sec_resp_cfg; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index a2ae5d3c4b9..5cb2b78b1fc 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -21,18 +21,35 @@ struct ARMSSEInfo { const char *name; int sram_banks; + int num_cpus; }; =20 static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, .sram_banks =3D 1, + .num_cpus =3D 1, }, }; =20 /* Clock frequency in HZ of the 32KHz "slow clock" */ #define S32KCLK (32 * 1000) =20 +/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ +static bool irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: per-CPU icache interrupt */ + /* 14: reserved */ + [15 ... 20] =3D true, + /* 21: reserved */ + [22 ... 26] =3D true, + /* 27: reserved */ + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + /* Create an alias region of @size bytes starting at @base * which mirrors the memory starting at @orig. */ @@ -125,13 +142,18 @@ static void armsse_init(Object *obj) int i; =20 assert(info->sram_banks <=3D MAX_SRAM_BANKS); + assert(info->num_cpus <=3D SSE_MAX_CPUS); =20 memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 - sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m), - TYPE_ARMV7M); - qdev_prop_set_string(DEVICE(&s->armv7m), "cpu-type", - ARM_CPU_TYPE_NAME("cortex-m33")); + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("armv7m%d", i); + sysbus_init_child_obj(obj, name, &s->armv7m[i], sizeof(s->armv7m), + TYPE_ARMV7M); + qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-m33")); + g_free(name); + } =20 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), TYPE_IOTKIT_SECCTL); @@ -192,13 +214,25 @@ static void armsse_init(Object *obj) TYPE_SPLIT_IRQ, &error_abort, NULL); g_free(name); } + if (info->num_cpus > 1) { + for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { + if (irq_is_common[i]) { + char *name =3D g_strdup_printf("cpu-irq-splitter%d", i); + SplitIRQ *splitter =3D &s->cpu_irq_splitter[i]; + + object_initialize_child(obj, name, splitter, sizeof(*split= ter), + TYPE_SPLIT_IRQ, &error_abort, NULL= ); + g_free(name); + } + } + } } =20 static void armsse_exp_irq(void *opaque, int n, int level) { - ARMSSE *s =3D ARMSSE(opaque); + qemu_irq *irqarray =3D opaque; =20 - qemu_set_irq(s->exp_irqs[n], level); + qemu_set_irq(irqarray[n], level); } =20 static void armsse_mpcexp_status(void *opaque, int n, int level) @@ -207,6 +241,26 @@ static void armsse_mpcexp_status(void *opaque, int n, = int level) qemu_set_irq(s->mpcexp_status_in[n], level); } =20 +static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int irqno) +{ + /* + * Return a qemu_irq which can be used to signal IRQ n to + * all CPUs in the SSE. + */ + ARMSSEClass *asc =3D ARMSSE_GET_CLASS(s); + const ARMSSEInfo *info =3D asc->info; + + assert(irq_is_common[irqno]); + + if (info->num_cpus =3D=3D 1) { + /* Only one CPU -- just connect directly to it */ + return qdev_get_gpio_in(DEVICE(&s->armv7m[0]), irqno); + } else { + /* Connect to the splitter which feeds all CPUs */ + return qdev_get_gpio_in(DEVICE(&s->cpu_irq_splitter[irqno]), 0); + } +} + static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARMSSE(dev); @@ -280,37 +334,105 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 - qdev_prop_set_uint32(DEVICE(&s->armv7m), "num-irq", s->exp_numirq + 32= ); - /* In real hardware the initial Secure VTOR is set from the INITSVTOR0 - * register in the IoT Kit System Control Register block, and the - * initial value of that is in turn specifiable by the FPGA that - * instantiates the IoT Kit. In QEMU we don't implement this wrinkle, - * and simply set the CPU's init-svtor to the IoT Kit default value. - */ - qdev_prop_set_uint32(DEVICE(&s->armv7m), "init-svtor", 0x10000000); - object_property_set_link(OBJECT(&s->armv7m), OBJECT(&s->container), - "memory", &err); - if (err) { - error_propagate(errp, err); - return; - } - object_property_set_link(OBJECT(&s->armv7m), OBJECT(s), "idau", &err); - if (err) { - error_propagate(errp, err); - return; - } - object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); - if (err) { - error_propagate(errp, err); - return; + for (i =3D 0; i < info->num_cpus; i++) { + DeviceState *cpudev =3D DEVICE(&s->armv7m[i]); + Object *cpuobj =3D OBJECT(&s->armv7m[i]); + int j; + char *gpioname; + + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); + /* + * In real hardware the initial Secure VTOR is set from the INITSV= TOR0 + * register in the IoT Kit System Control Register block, and the + * initial value of that is in turn specifiable by the FPGA that + * instantiates the IoT Kit. In QEMU we don't implement this wrink= le, + * and simply set the CPU's init-svtor to the IoT Kit default valu= e. + * In SSE-200 the situation is similar, except that the default va= lue + * is a reset-time signal input. Typically a board using the SSE-2= 00 + * will have a system control processor whose boot firmware initia= lizes + * the INITSVTOR* registers before powering up the CPUs in any cas= e, + * so the hardware's default value doesn't matter. QEMU doesn't em= ulate + * the control processor, so instead we behave in the way that the + * firmware does. All boards currently known about have firmware t= hat + * sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, lik= e the + * IoTKit default. We can make this more configurable if necessary. + */ + qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); + /* + * Start all CPUs except CPU0 powered down. In real hardware it is + * a configurable property of the SSE-200 which CPUs start powered= up + * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since a= ll + * the boards we care about start CPU0 and leave CPU1 powered off, + * we hard-code that for now. We can add QOM properties for this + * later if necessary. + */ + if (i > 0) { + object_property_set_bool(cpuobj, true, "start-powered-off", &e= rr); + if (err) { + error_propagate(errp, err); + return; + } + } + object_property_set_link(cpuobj, OBJECT(&s->container), "memory", = &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_link(cpuobj, OBJECT(s), "idau", &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(cpuobj, true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ + s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); + for (j =3D 0; j < s->exp_numirq; j++) { + s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, i + 32); + } + if (i =3D=3D 0) { + gpioname =3D g_strdup("EXP_IRQ"); + } else { + gpioname =3D g_strdup_printf("EXP_CPU%d_IRQ", i); + } + qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq, + s->exp_irqs[i], + gpioname, s->exp_numirq); + g_free(gpioname); } =20 - /* Connect our EXP_IRQ GPIOs to the NVIC's lines 32 and up. */ - s->exp_irqs =3D g_new(qemu_irq, s->exp_numirq); - for (i =3D 0; i < s->exp_numirq; i++) { - s->exp_irqs[i] =3D qdev_get_gpio_in(DEVICE(&s->armv7m), i + 32); + /* Wire up the splitters that connect common IRQs to all CPUs */ + if (info->num_cpus > 1) { + for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { + if (irq_is_common[i]) { + Object *splitter =3D OBJECT(&s->cpu_irq_splitter[i]); + DeviceState *devs =3D DEVICE(splitter); + int cpunum; + + object_property_set_int(splitter, info->num_cpus, + "num-lines", &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(splitter, true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + for (cpunum =3D 0; cpunum < info->num_cpus; cpunum++) { + DeviceState *cpudev =3D DEVICE(&s->armv7m[cpunum]); + + qdev_connect_gpio_out(devs, cpunum, + qdev_get_gpio_in(cpudev, i)); + } + } + } } - qdev_init_gpio_in_named(dev, armsse_exp_irq, "EXP_IRQ", s->exp_numirq); =20 /* Set up the big aliases first */ make_alias(s, &s->alias1, "alias 1", 0x10000000, 0x10000000, 0x0000000= 0); @@ -407,7 +529,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 9)); + armsse_get_common_irq_in(s, 9)); =20 /* Devices behind APB PPC0: * 0x40000000: timer0 @@ -424,7 +546,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 3)); + armsse_get_common_irq_in(s, 3)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[0]", = &err); if (err) { @@ -439,7 +561,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 4)); + armsse_get_common_irq_in(s, 4)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", = &err); if (err) { @@ -455,7 +577,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->dualtimer), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 5)); + armsse_get_common_irq_in(s, 5)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dualtimer), 0); object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[2]", = &err); if (err) { @@ -513,7 +635,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 10)); + armsse_get_common_irq_in(s, 10)); =20 /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ =20 @@ -528,7 +650,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->s32ktimer), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 2)); + armsse_get_common_irq_in(s, 2)); mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->s32ktimer), 0); object_property_set_link(OBJECT(&s->apb_ppc1), OBJECT(mr), "port[0]", = &err); if (err) { @@ -609,7 +731,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) return; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->nswatchdog), 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 1)); + armsse_get_common_irq_in(s, 1)); sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000); =20 qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_= frq); @@ -715,7 +837,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) qdev_pass_gpios(dev_secctl, dev, "mscexp_clear"); qdev_pass_gpios(dev_secctl, dev, "mscexp_ns"); qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0, - qdev_get_gpio_in(DEVICE(&s->armv7m), 11)); + armsse_get_common_irq_in(s, 11)); =20 /* * Expose our container region to the board model; this corresponds --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hxN9w6vB/LiDEV5gzGDXQH/dDiAcrkx41p69PfQpSas=; b=czH42x5GG7hu82urZ1qyzXtX0PdCCEGBdww4vSZWEk9jkvtCRhQaIcvOupgjxp8P9o H8TDD10vorRCkBfzamXuZjCt0SbF3jT9NifOw9nnqbbxXJJeaAKHioQbjDVlhaqokLs4 lntdSHJc1OwoFJzZfgv57zVRJPva8RG0DQTMk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hxN9w6vB/LiDEV5gzGDXQH/dDiAcrkx41p69PfQpSas=; b=iIsrnvWyHEaZpCbQkVO7lUZkyUrHiyRLW6JGaGOMObj9Src4LIBE1BqjKGormQVgml wpTWxR1M0+tPIchk99HaVOAxLvckU+QJYESfKjtINPcdxn42+uBoAXsOEhwFmyme9O9k jooTpyPhQIKwjuhchKqHadLdblvYZ4W1BAzFB9OljS3gzNQ0iSa/sCXwa5q32lus4eO2 r5NFJyOylixsZEubrd16ZT+0jgp9qcJ6XyUR6cxXUJXZBShgJRPxppns4uMnzo3uuiDv xGXpWwyLXtiJdWACj7vkMymFhZMZfJirZexTDD2KOl+oVcLq9wM4AX9S5QAAsCHsZWRN 3Iug== X-Gm-Message-State: AJcUukd5Pmn+dslRBNZdvZQXgxGnrCyJEylY1Tx+8p9qpLiBKvs8E/vi 9kurhA6XchYmX2pOUaU1w7Yhrw== X-Google-Smtp-Source: ALg8bN4VYlkN4p7M6UFf+/LAA/xBTHibRlpkM1eL9pbPZw+s+GfC8iN97d+qsaH1j7EnsEvwvQlWmA== X-Received: by 2002:a1c:bd86:: with SMTP id n128mr588135wmf.22.1548096694400; Mon, 21 Jan 2019 10:51:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:07 +0000 Message-Id: <20190121185118.18550-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 12/23] hw/arm/armsse: Give each CPU its own view of memory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 10 ++++++++++ hw/arm/armsse.c | 22 ++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index faf5dfed252..89f19a971f4 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -135,7 +135,17 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 + /* + * 'container' holds all devices seen by all CPUs. + * 'cpu_container[i]' is the view that CPU i has: this has the + * per-CPU devices of that CPU, plus as the background 'container' + * (or an alias of it, since we can only use it directly once). + * container_alias[i] is the alias of 'container' used by CPU i+1; + * CPU 0 can use 'container' directly. + */ MemoryRegion container; + MemoryRegion container_alias[SSE_MAX_CPUS - 1]; + MemoryRegion cpu_container[SSE_MAX_CPUS]; MemoryRegion alias1; MemoryRegion alias2; MemoryRegion alias3; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5cb2b78b1fc..2472dfef3a1 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -153,6 +153,15 @@ static void armsse_init(Object *obj) qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m33")); g_free(name); + name =3D g_strdup_printf("arm-sse-cpu-container%d", i); + memory_region_init(&s->cpu_container[i], obj, name, UINT64_MAX); + g_free(name); + if (i > 0) { + name =3D g_strdup_printf("arm-sse-container-alias%d", i); + memory_region_init_alias(&s->container_alias[i - 1], obj, + name, &s->container, 0, UINT64_MAX); + g_free(name); + } } =20 sysbus_init_child_obj(obj, "secctl", &s->secctl, sizeof(s->secctl), @@ -332,7 +341,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff */ =20 - memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -2); =20 for (i =3D 0; i < info->num_cpus; i++) { DeviceState *cpudev =3D DEVICE(&s->armv7m[i]); @@ -373,7 +382,16 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } } - object_property_set_link(cpuobj, OBJECT(&s->container), "memory", = &err); + + if (i > 0) { + memory_region_add_subregion_overlap(&s->cpu_container[i], 0, + &s->container_alias[i - 1]= , -1); + } else { + memory_region_add_subregion_overlap(&s->cpu_container[i], 0, + &s->container, -1); + } + object_property_set_link(cpuobj, OBJECT(&s->cpu_container[i]), + "memory", &err); if (err) { error_propagate(errp, err); return; --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098385850184.52969603787358; Mon, 21 Jan 2019 11:19:45 -0800 (PST) Received: from localhost ([127.0.0.1]:58496 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf6m-0000nI-Q3 for importer@patchew.org; Mon, 21 Jan 2019 14:19:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevS-0008OY-R7 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002sm-3Y for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:45 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:35860) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefe-0002iK-Nz for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:42 -0500 Received: by mail-wm1-x343.google.com with SMTP id p6so11831828wmc.1 for ; Mon, 21 Jan 2019 10:51:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e/n/E9zIC87pmNrtpyul6OlAohOOfM09CA6XexX2VVY=; b=fJcrt2ee0cMoAYCl8VUBXDczHAbuDqtq7DELrUDquPqh7qPmJ/FmOgv6miS2LibFPa etUHy1h3HjFArQw7XTQwd0BFmHyfj9p8JPN61KDaq1FdK3aQ/QvoFU1FMsmuvB8kf6xm ASaLu9/85WEhGFmlgaAJTIevTxY1ySu+LmWtY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e/n/E9zIC87pmNrtpyul6OlAohOOfM09CA6XexX2VVY=; b=nyJOS1vlnRUQL5A9KLb16gZsqBsBfHuw18a8+y3eLeIDU/Kunpkj24IIgiWLnLl0bq qMn8maKzhy9+kbGjZ+w6p5OYk35vcSF6ILkYsjPucrROVaJAFsR7Fe9J3zDeqlcUc5D3 YdXA9JPHQ8VHg0r5Ajl/saJ79yRIBZZbyzXUpHngCU95ksqd5ubZ981uDaAmkm/0VgJB 81TlPQpZcGJcNu8mo+UZlD+A2VBN8XrldtpmFb6//pyPiJiji+UX+AkvRmMO8V8XRI3o CnTOk9fK9I3huaTowXEmjLZRRbdboOidzXfGXLrs+KvDcTjXw3JFwhvDF96sH1MDX2N7 ukNw== X-Gm-Message-State: AJcUukfC0EqtkcYwif1uHij5r4qfvZJsPhMAZZ5aAqdaGi8+0y4ghW5n bnfkZVysPZidpSAUFclZ7jon5g== X-Google-Smtp-Source: ALg8bN7az6jkgFRO/wP9chzZj7eYZlRhd20Ob/GgkSE1WlLYU/JJkv2KpZPCQO5MZ5o6NZGkO7ejJw== X-Received: by 2002:a1c:ca15:: with SMTP id a21mr532240wmg.132.1548096695764; Mon, 21 Jan 2019 10:51:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:08 +0000 Message-Id: <20190121185118.18550-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 13/23] hw/arm/armsse: Put each CPU in its own cluster object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 2 ++ hw/arm/armsse.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 89f19a971f4..999c2e4f7e5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -80,6 +80,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" +#include "hw/cpu/cluster.h" =20 #define TYPE_ARMSSE "arm-sse" #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) @@ -110,6 +111,7 @@ typedef struct ARMSSE { =20 /*< public >*/ ARMv7MState armv7m[SSE_MAX_CPUS]; + CPUClusterState cluster[SSE_MAX_CPUS]; IoTKitSecCtl secctl; TZPPC apb_ppc0; TZPPC apb_ppc1; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2472dfef3a1..2eb4ea3bfe0 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -147,9 +147,22 @@ static void armsse_init(Object *obj) memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX); =20 for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("armv7m%d", i); - sysbus_init_child_obj(obj, name, &s->armv7m[i], sizeof(s->armv7m), - TYPE_ARMV7M); + /* + * We put each CPU in its own cluster as they are logically + * distinct and may be configured differently. + */ + char *name; + + name =3D g_strdup_printf("cluster%d", i); + object_initialize_child(obj, name, &s->cluster[i], + sizeof(s->cluster[i]), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); + g_free(name); + + name =3D g_strdup_printf("armv7m%d", i); + sysbus_init_child_obj(OBJECT(&s->cluster[i]), name, + &s->armv7m[i], sizeof(s->armv7m), TYPE_ARMV7= M); qdev_prop_set_string(DEVICE(&s->armv7m[i]), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m33")); g_free(name); @@ -406,6 +419,18 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) error_propagate(errp, err); return; } + /* + * The cluster must be realized after the armv7m container, as + * the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before + * the cluster is realized. + */ + object_property_set_bool(OBJECT(&s->cluster[i]), + true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } =20 /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098858737571.9535003663661; Mon, 21 Jan 2019 11:27:38 -0800 (PST) Received: from localhost ([127.0.0.1]:58641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfEP-0006iT-I5 for importer@patchew.org; Mon, 21 Jan 2019 14:27:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevQ-0008Da-Bs for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002tn-Gb for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:47 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gleff-0002pQ-4D for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wm1-x342.google.com with SMTP id r24so6819069wmh.0 for ; Mon, 21 Jan 2019 10:51:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VmHuIRIe0slMKOXr+14HFfLZdXo4lblxIN5l7d3ILAc=; b=SesOGL775fsc9/86PZIQVXi1iJ6ymEgeMQdsTAHfJr1xh8SHO19KzSSu3eNIUYmhts 01un4Q/lXFCf9G2YD66HKEQJKS8AqvREwmM/9i4cnnrnHsyQZ4UobZgM4vztejm7fjtM /a6c8+/FvgP1E1hpF9FmIdF+JD8Rkl3Xx+jcE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VmHuIRIe0slMKOXr+14HFfLZdXo4lblxIN5l7d3ILAc=; b=kt6W3DegyG6WU+tQXOR64HAJeF1vdf9Y0O1Usaf4UI4LOHtWgjCxQ/FMkBiemr6R5+ scw9LAnBOlbo7KmntKhnoRwzVzTR0GeZjpNr1vP8iBecSWJy9wyqqlLQyI+xi48d3HJs 5cWk4ei5hZdrO93FUKH8b9Hh+/6XAWFbz5PJxkz1PmF7n2v3ONOnSn4v7AOmFaB2HrfS juuA75J2RzTuRYWcMyslU3BqlrvXxfGibUSk0nGY8D9mDPGS6cX3yjGakjxk9NGAAAlT Y62NKgQgf0UsDd27OS7Almw2oVxY6LiDw04uNzruQf0vb/2NWujoldjWfUPBkWQ2HN+Q WEUw== X-Gm-Message-State: AJcUukddVrpZepAwlnc9OazfhnyP61ibQYYOTcxgbzBwIcxn5Av7XASk p61xJnu6FYDoF3KNBfUojVFqxw== X-Google-Smtp-Source: ALg8bN4SD6VtGPSe4qgq4pF/Twajt18eftHA/2OLSmOKYgGv6s48F39+LHzsyvNXAQooSX8z3h/Sag== X-Received: by 2002:a1c:cf0d:: with SMTP id f13mr559540wmg.70.1548096696872; Mon, 21 Jan 2019 10:51:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:09 +0000 Message-Id: <20190121185118.18550-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 14/23] iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/misc/iotkit-sysinfo.h | 6 ++++ hw/arm/armsse.c | 51 ++++++++++++++++++++++++++++++++ hw/misc/iotkit-sysinfo.c | 15 ++++++++-- 3 files changed, 70 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysi= nfo.h index 7b2e1a5e48b..d84eb203b90 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -14,6 +14,8 @@ * Arm IoTKit and documented in * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html * QEMU interface: + * + QOM property "SYS_VERSION": value to use for SYS_VERSION register + * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register * + sysbus MMIO region 0: the system information register bank */ =20 @@ -32,6 +34,10 @@ typedef struct IoTKitSysInfo { =20 /*< public >*/ MemoryRegion iomem; + + /* Properties */ + uint32_t sys_version; + uint32_t sys_config; } IoTKitSysInfo; =20 #endif diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2eb4ea3bfe0..19cae77e770 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -18,10 +18,18 @@ #include "hw/arm/armsse.h" #include "hw/arm/arm.h" =20 +/* Format of the System Information block SYS_CONFIG register */ +typedef enum SysConfigFormat { + IoTKitFormat, + SSE200Format, +} SysConfigFormat; + struct ARMSSEInfo { const char *name; int sram_banks; int num_cpus; + uint32_t sys_version; + SysConfigFormat sys_config_format; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -29,9 +37,39 @@ static const ARMSSEInfo armsse_variants[] =3D { .name =3D TYPE_IOTKIT, .sram_banks =3D 1, .num_cpus =3D 1, + .sys_version =3D 0x41743, + .sys_config_format =3D IoTKitFormat, }, }; =20 +static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) +{ + /* Return the SYS_CONFIG value for this SSE */ + uint32_t sys_config; + + switch (info->sys_config_format) { + case IoTKitFormat: + sys_config =3D 0; + sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); + sys_config =3D deposit32(sys_config, 4, 4, s->sram_addr_width - 12= ); + break; + case SSE200Format: + sys_config =3D 0; + sys_config =3D deposit32(sys_config, 0, 4, info->sram_banks); + sys_config =3D deposit32(sys_config, 4, 5, s->sram_addr_width); + sys_config =3D deposit32(sys_config, 24, 4, 2); + if (info->num_cpus > 1) { + sys_config =3D deposit32(sys_config, 10, 1, 1); + sys_config =3D deposit32(sys_config, 20, 4, info->sram_banks -= 1); + sys_config =3D deposit32(sys_config, 28, 4, 2); + } + break; + default: + g_assert_not_reached(); + } + return sys_config; +} + /* Clock frequency in HZ of the 32KHz "slow clock" */ #define S32KCLK (32 * 1000) =20 @@ -726,6 +764,19 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) qdev_get_gpio_in_named(dev_apb_ppc1, "cfg_sec_resp", 0)); =20 + object_property_set_int(OBJECT(&s->sysinfo), info->sys_version, + "SYS_VERSION", &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_int(OBJECT(&s->sysinfo), + armsse_sys_config_value(s, info), + "SYS_CONFIG", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->sysinfo), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 78955bc45f5..026ba942613 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -51,15 +51,16 @@ static const int sysinfo_id[] =3D { static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset, unsigned size) { + IoTKitSysInfo *s =3D IOTKIT_SYSINFO(opaque); uint64_t r; =20 switch (offset) { case A_SYS_VERSION: - r =3D 0x41743; + r =3D s->sys_version; break; =20 case A_SYS_CONFIG: - r =3D 0x31; + r =3D s->sys_config; break; case A_PID4 ... A_CID3: r =3D sysinfo_id[(offset - A_PID4) / 4]; @@ -94,6 +95,12 @@ static const MemoryRegionOps iotkit_sysinfo_ops =3D { .valid.max_access_size =3D 4, }; =20 +static Property iotkit_sysinfo_props[] =3D { + DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0), + DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void iotkit_sysinfo_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); @@ -106,10 +113,14 @@ static void iotkit_sysinfo_init(Object *obj) =20 static void iotkit_sysinfo_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); + /* * This device has no guest-modifiable state and so it * does not need a reset function or VMState. */ + + dc->props =3D iotkit_sysinfo_props; } =20 static const TypeInfo iotkit_sysinfo_info =3D { --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548097815530799.6713425036068; Mon, 21 Jan 2019 11:10:15 -0800 (PST) Received: from localhost ([127.0.0.1]:58296 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glexZ-0001XM-4P for importer@patchew.org; Mon, 21 Jan 2019 14:10:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevS-0007jF-K3 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002tG-9q for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:45 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:37154) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefe-0002q6-Tc for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wm1-x341.google.com with SMTP id g67so11810974wmd.2 for ; Mon, 21 Jan 2019 10:51:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6dJlwUKV/mqO+LXLnxltTP2TIDBTQAdk8nXHap2RUUY=; b=SAD5tiJYu6GshOFt06OOesXbZzTo7uSnbOUYUPP6hioR7NUflBeSy72YkIuyrwN7oX aLQuXcQhe+ZMXQfxHe50YOXIq3qbei+/aVge2SxWMv7fEOg+ZqoeT/h18L2PM4D6aSfa nI9sisNjgTfbfI3NdCCJl6IPaOOHRZbEp5pXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6dJlwUKV/mqO+LXLnxltTP2TIDBTQAdk8nXHap2RUUY=; b=KgFROWJEnRQ2dnd2gKuy4YGFcvExYTO5mGaECTr+BEoUERe4E7iAFLjTUsHKFNvfR/ nPgPCs6rejDyZFdiitCfCFBaZuivDjDx0cddjn2DOi8IP5BatRfHBKdVlnI3Kah00UXn 2yFiqEy5Msbpkckf4ZWIVlqmwCPBSrFhfgwdHGWWXdIyxMXdyPUCN7Sm4BP7wjMXrsFi KlWkZODIaIDX1BHmocylMLESYzn/axDbqIYTr7eYTy4m9nsRkU6nNXPn82MX5v7iXva0 CNOHEBqDG23TqP1eWDUUCYEVeLkHXSxqyYwII9NiOO2/beD2vf1wLONdV+bTyAWz+GXp iwYg== X-Gm-Message-State: AJcUukcJtFRl4lA2MtH9LfujDahA0JrwKKDD2QNpcB6a6aMs3K1VlMnd izRo3PiAbDnTK8FxEUmRsMlcbg== X-Google-Smtp-Source: ALg8bN69OhaQokesDM5SCBqVsqokbgk72zS9fwThEkrY6Fk4Rlf0+5CQP+AsJabJCXcsAqoh57ocjg== X-Received: by 2002:a1c:4807:: with SMTP id v7mr555289wma.53.1548096697933; Mon, 21 Jan 2019 10:51:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:10 +0000 Message-Id: <20190121185118.18550-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 15/23] hw/arm/armsse: Add unimplemented-device stubs for MHUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has two Message Handling Units (MHUs), which sit behind the APB PPC0. Wire up some unimplemented-device stubs for these, since we don't yet implement a real model of this device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 999c2e4f7e5..dbfcb280605 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" #include "hw/cpu/cluster.h" @@ -137,6 +138,8 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 + UnimplementedDeviceState mhu[2]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 19cae77e770..1f3dc89c8e8 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -30,6 +30,7 @@ struct ARMSSEInfo { int num_cpus; uint32_t sys_version; SysConfigFormat sys_config_format; + bool has_mhus; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -39,6 +40,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .num_cpus =3D 1, .sys_version =3D 0x41743, .sys_config_format =3D IoTKitFormat, + .has_mhus =3D false, }, }; =20 @@ -257,6 +259,12 @@ static void armsse_init(Object *obj) sizeof(s->sysctl), TYPE_IOTKIT_SYSCTL); sysbus_init_child_obj(obj, "armsse-sysinfo", &s->sysinfo, sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO); + if (info->has_mhus) { + sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]), + TYPE_UNIMPLEMENTED_DEVICE); + sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), + TYPE_UNIMPLEMENTED_DEVICE); + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -616,6 +624,8 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) * 0x40000000: timer0 * 0x40001000: timer1 * 0x40002000: dual timer + * 0x40003000: MHU0 (SSE-200 only) + * 0x40004000: MHU1 (SSE-200 only) * We must configure and realize each downstream device and connect * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. @@ -666,6 +676,31 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } =20 + if (info->has_mhus) { + for (i =3D 0; i < ARRAY_SIZE(s->mhu); i++) { + char *name =3D g_strdup_printf("MHU%d", i); + char *port =3D g_strdup_printf("port[%d]", i + 3); + + qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name); + qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000); + object_property_set_bool(OBJECT(&s->mhu[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0); + object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), + port, &err); + if (err) { + error_propagate(errp, err); + return; + } + g_free(name); + g_free(port); + } + } + object_property_set_bool(OBJECT(&s->apb_ppc0), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -681,6 +716,12 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->container, 0x40001000, mr); mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 2); memory_region_add_subregion(&s->container, 0x40002000, mr); + if (info->has_mhus) { + mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 3); + memory_region_add_subregion(&s->container, 0x40003000, mr); + mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 4); + memory_region_add_subregion(&s->container, 0x40004000, mr); + } for (i =3D 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) { qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i, qdev_get_gpio_in_named(dev_apb_ppc0, --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LzRvPMbQkQGhAdwFKIwhiAq/gXzdlKz74UrTsx5pEqs=; b=HTFIpc6plfz5Oe4OMdVqt3PxMZFqJEa+VBhskWdK6sf8arXNcOMps+Q2BlZwycXeBf E9lnYWNq7kxZO4dLaFcxCQRB6rSV2JVVGHFzwh4N5lTSiy/x7kh53azg+JKckGvl3nCj CNzGrg5OHRU7RTpouszJJTG1tcRz6D45isqDo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LzRvPMbQkQGhAdwFKIwhiAq/gXzdlKz74UrTsx5pEqs=; b=e9KWs+sHPLAll4V252i7QMWFgZRMasoPuFhhswOA10oi2K9gQkFZv1Y+t4ncbz0VUg +/aHJkoM/Qbmu68So5UQ6dnyYgS5LQaPjfOD/jpbaL18l4KiXyu0lp4u3Luc4bg89FOB dlWy/YTbQoW6p3iH+Bz2ZTY0N2flYkZNioyXd3vQOCY1BGYWntqEKorLmM4tJGzPiXkU WSeAGtbrn0NpwmYcdu7Nf3krLXMV2XxtQCbmIBNYA1ghUREyLTxI/g0m/YL2xbAml1R4 h71+itmrLttNZteaZBc15QMAM5LxMB0TlrWQhvHlAy+nJUSGGShRoOzomy+OR0C+jthP xoQw== X-Gm-Message-State: AJcUukcKVVug+wqSSbJbBXHCMhUAubxAuoO121tEdKdVVwKllt8maKuP G+MarV3Yy0SB8Fkfc0HBAAgmpA== X-Google-Smtp-Source: ALg8bN45w2p1E0/xf2Y5Eyksdnp2txrpoYFYaJsaqJco8ucxFZZc/SaZX9YLqFIbsSGYJH5Kn0HJGg== X-Received: by 2002:a5d:678b:: with SMTP id v11mr31459517wru.245.1548096698977; Mon, 21 Jan 2019 10:51:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:11 +0000 Message-Id: <20190121185118.18550-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH 16/23] hw/arm/armsse: Add unimplemented-device stubs for PPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add unimplemented-device stubs for the various Power Policy Unit devices that the SSE-200 has. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 11 ++++++++ hw/arm/armsse.c | 58 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index dbfcb280605..9855ec5f269 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -106,6 +106,16 @@ =20 #define SSE_MAX_CPUS 2 =20 +/* These define what each PPU in the ppu[] index is for */ +#define CPU0CORE_PPU 0 +#define CPU1CORE_PPU 1 +#define DBG_PPU 2 +#define RAM0_PPU 3 +#define RAM1_PPU 4 +#define RAM2_PPU 5 +#define RAM3_PPU 6 +#define NUM_PPUS 7 + typedef struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -139,6 +149,7 @@ typedef struct ARMSSE { IoTKitSysCtl sysinfo; =20 UnimplementedDeviceState mhu[2]; + UnimplementedDeviceState ppu[NUM_PPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1f3dc89c8e8..280ba5c78be 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -31,6 +31,7 @@ struct ARMSSEInfo { uint32_t sys_version; SysConfigFormat sys_config_format; bool has_mhus; + bool has_ppus; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -41,6 +42,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sys_version =3D 0x41743, .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, + .has_ppus =3D false, }, }; =20 @@ -265,6 +267,29 @@ static void armsse_init(Object *obj) sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]), TYPE_UNIMPLEMENTED_DEVICE); } + if (info->has_ppus) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); + int ppuidx =3D CPU0CORE_PPU + i; + + sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], + sizeof(s->ppu[ppuidx]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + sysbus_init_child_obj(obj, "DBG_PPU", &s->ppu[DBG_PPU], + sizeof(s->ppu[DBG_PPU]), + TYPE_UNIMPLEMENTED_DEVICE); + for (i =3D 0; i < info->sram_banks; i++) { + char *name =3D g_strdup_printf("RAM%d_PPU", i); + int ppuidx =3D RAM0_PPU + i; + + sysbus_init_child_obj(obj, name, &s->ppu[ppuidx], + sizeof(s->ppu[ppuidx]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -329,6 +354,17 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, in= t irqno) } } =20 +static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) +{ + /* Map a PPU unimplemented device stub */ + DeviceState *dev =3D DEVICE(&s->ppu[ppuidx]); + + qdev_prop_set_string(dev, "name", name); + qdev_prop_set_uint64(dev, "size", 0x1000); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); +} + static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARMSSE(dev); @@ -833,6 +869,28 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); =20 + if (info->has_ppus) { + /* CPUnCORE_PPU for each CPU */ + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); + + map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); + /* + * We don't support CPU debug so don't create the + * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. + */ + g_free(name); + } + map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); + + for (i =3D 0; i < info->sram_banks; i++) { + char *name =3D g_strdup_printf("RAM%d_PPU", i); + + map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); + g_free(name); + } + } + /* This OR gate wires together outputs from the secure watchdogs to NM= I */ object_property_set_int(OBJECT(&s->nmi_orgate), 2, "num-lines", &err); if (err) { --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098361933627.1404197550975; Mon, 21 Jan 2019 11:19:21 -0800 (PST) Received: from localhost ([127.0.0.1]:58492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf6O-0000TH-T2 for importer@patchew.org; Mon, 21 Jan 2019 14:19:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevR-0008Da-WD for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002ti-GT for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:47 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:40271) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gleff-0002r1-1w for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wr1-x441.google.com with SMTP id p4so24610847wrt.7 for ; Mon, 21 Jan 2019 10:51:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=16YcVXkNI0qZQIE9OU/93mNUdU9hbKw0nKOMHfNAYQc=; b=RRyB9+r1E4aTDZK4X/LljGD24LU6DFmbEl+Dgrb40u5v9tttO5ToKm4rgdX2rqxkva MG4hVDu6AjK+kHLE+cm/K6IFt8oEkvGIwAGAzFvNk7hRCsCneFHVaitePfhvv+SIVwJ+ tLGN+7vZBz4ooX1E2WevPKd7kr9YEsQyHzccw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=16YcVXkNI0qZQIE9OU/93mNUdU9hbKw0nKOMHfNAYQc=; b=MDNY5KyAezdWkNMba+pGajw44se2MHDQfkdabIqcXx/p910vdOHoJhylAJ6tRQYq0G Ty8tqOfKtHfwDjOOFuScj8euWGWAaIBc79j2BY5fGs9cDlp2L0sGKaTGZElHzF54zIuh nCX72JtAqknxfGMOB8beiruK/FMy+PljM9ZQ1T6FOXODgU2sIdKkCgNOl0ilL8pP2WPQ qdPw+eoTg94IIpc40Tq+5341i49zwz76SUzuV3dyCa8UL2/zMCMAwMHejesH3gcL8+8s axd4mEVLzubuKG/HaOKBP3/OL0cop2xX8eYQ+JEbr1vkq01QrH+ifKDYZikTeRVT4PVq YtnA== X-Gm-Message-State: AJcUukehFyAEYvtRHnkQe70jXPgJkB4bVhvyZQ3WCsDqsafT/EjFMDWZ WdzQ08ROK1pkih3L8eF3D2YcHFIF8YbvYQ== X-Google-Smtp-Source: ALg8bN4huX0n6vA9wOioumb58JSq3w0TB5hTQJ21O0Fg71HWtcKBv76BttZZVyhSu9h37MM3K3QJZQ== X-Received: by 2002:a5d:568c:: with SMTP id f12mr27701887wrv.101.1548096700023; Mon, 21 Jan 2019 10:51:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:12 +0000 Message-Id: <20190121185118.18550-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH 17/23] hw/arm/armsse: Add unimplemented-device stub for cache control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 gives each CPU a register bank to use to control its L1 instruction cache. Put in an unimplemented-device stub for this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 39 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9855ec5f269..9d830057d5c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -150,6 +150,7 @@ typedef struct ARMSSE { =20 UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; + UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 280ba5c78be..41e4a781e11 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -32,6 +32,7 @@ struct ARMSSEInfo { SysConfigFormat sys_config_format; bool has_mhus; bool has_ppus; + bool has_cachectrl; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -43,6 +44,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .sys_config_format =3D IoTKitFormat, .has_mhus =3D false, .has_ppus =3D false, + .has_cachectrl =3D false, }, }; =20 @@ -290,6 +292,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cachectrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cachectrl%d", i); + + sysbus_init_child_obj(obj, name, &s->cachectrl[i], + sizeof(s->cachectrl[i]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -795,7 +807,32 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0, armsse_get_common_irq_in(s, 10)); =20 - /* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */ + /* + * 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias): + * private per-CPU region (all these devices are SSE-200 only): + * 0x50010000: L1 icache control registers + * 0x50011000: CPUSECCTRL (CPU local security control registers) + * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block + */ + if (info->has_cachectrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cachectrl%d", i); + MemoryRegion *mr; + + qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name); + g_free(name); + qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000); + object_property_set_bool(OBJECT(&s->cachectrl[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i])= , 0); + memory_region_add_subregion(&s->cpu_container[i], 0x50010000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548099264705472.0593529369248; Mon, 21 Jan 2019 11:34:24 -0800 (PST) Received: from localhost ([127.0.0.1]:58729 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfKs-0003he-K3 for importer@patchew.org; Mon, 21 Jan 2019 14:34:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevS-000888-D0 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002uI-Mt for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:47 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34468) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gleff-0002rQ-Bb for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wr1-x444.google.com with SMTP id j2so24705781wrw.1 for ; Mon, 21 Jan 2019 10:51:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5oXNf8YbRJ27W92QaQUg2Jg/rlBLxD7V8QWz6bSn8Tg=; b=NMEiUA6jC+0+m1CiYmjfyxKZWyJRx0xr6H4P9drgvZ5QPfqBhY/BKSqZk/IPbrU/Xf OGNPviQ/5fYaPqA18k0svK4vT1RQaKgBapMB2EvRQiEnTxO/pZJ0pETAcz0p12JMtNLg bx580M/WbdelgqUl1aoX8/tCqBjJSdjgqtGlE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oXNf8YbRJ27W92QaQUg2Jg/rlBLxD7V8QWz6bSn8Tg=; b=CujO+/fvGhjcfu7nKH6pr3cesvxnOojeZIRSHLBCiFFZjFFkPk11fVCL+QHDVU6oYZ hLi6kD+4F7ql7mjzW9hpEuIIEPjYV/2E5poqyS9WpoHMnUL3Dj+ta4vUehAv9q4IzKaw 1O7/2K9vVVp792YT5CbcTcsvmuMUYEAKYf41SxF197eyj1LzMizOa5+WiqRR4jBLZPhf L9rZG74skpyP0P2P3JBr95dcP6gc+Ya5FpNDmB8WYtL4MD1QEZKBll85Sd5eYsg51BGb lYlz02dZl9sUo6Ik0JHszoXepS6YeC1aVsIA6cz46eLxyCaqOQrz8rY+YQWde6eGs3FO NpSg== X-Gm-Message-State: AJcUukc6NFCMhVFtT1Kze5+qdpmDADw+lO2Nj2SBrsERjS/aoQk5HLxd LMZfeLuWHjXxaYEgPpVWeaRMRg== X-Google-Smtp-Source: ALg8bN74c/3XSF9S+ykrcrnY28J2F5cQo6oflXsSA29QWkMqYizS0wBi+4xODclwajSVej8N5quI9A== X-Received: by 2002:adf:9c01:: with SMTP id f1mr30514330wrc.286.1548096701027; Mon, 21 Jan 2019 10:51:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:13 +0000 Message-Id: <20190121185118.18550-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH 18/23] hw/arm/armsse: Add unimplemented-device stub for CPU local control registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has a "CPU local security control" register bank; add an unimplemented-device stub for it. (The register bank has only one interesting register, which allows the guest to lock down changes to various CPU registers so they cannot be modified further. We don't support that in our Cortex-M33 model anyway.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 9d830057d5c..961dbb3032a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -151,6 +151,7 @@ typedef struct ARMSSE { UnimplementedDeviceState mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; + UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 /* * 'container' holds all devices seen by all CPUs. diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 41e4a781e11..9c111ac6a40 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -33,6 +33,7 @@ struct ARMSSEInfo { bool has_mhus; bool has_ppus; bool has_cachectrl; + bool has_cpusecctrl; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -45,6 +46,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_mhus =3D false, .has_ppus =3D false, .has_cachectrl =3D false, + .has_cpusecctrl =3D false, }, }; =20 @@ -302,6 +304,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpusecctrl%d", i); + + sysbus_init_child_obj(obj, name, &s->cpusecctrl[i], + sizeof(s->cpusecctrl[i]), + TYPE_UNIMPLEMENTED_DEVICE); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -833,6 +845,25 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50010000, = mr); } } + if (info->has_cpusecctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("CPUSECCTRL%d", i); + MemoryRegion *mr; + + qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name); + g_free(name); + qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000= ); + object_property_set_bool(OBJECT(&s->cpusecctrl[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]= ), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154809868426058.959682169841244; Mon, 21 Jan 2019 11:24:44 -0800 (PST) Received: from localhost ([127.0.0.1]:58579 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glfBa-0004Q7-VT for importer@patchew.org; Mon, 21 Jan 2019 14:24:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevP-00081G-LA for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gleff-0002ue-Q6 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:48 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38218) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gleff-0002sP-Gy for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:43 -0500 Received: by mail-wm1-x342.google.com with SMTP id m22so11907574wml.3 for ; Mon, 21 Jan 2019 10:51:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ptElJAOC24V6aCwdEwgL13NkItv2g2+5CEz3KW95t8w=; b=WFIkmDzwGTUR/d4XtIBue0PmRyHGfjn/zBABzmHq8uB3lM2vPa/5lSypbCInheqrGu P5oC9v+vF1oTX7Xe9HVHLsCiz7vZT4pho36KQp9ihgLNbnbKD5fPcDrXhUSWIs/GDd3Y kVh8nXca6cKp//P4B+PCZBdQF6Sekflec1OOs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ptElJAOC24V6aCwdEwgL13NkItv2g2+5CEz3KW95t8w=; b=UIkbGAne8Trf4WT8WK6CxUPe9NXwr/S7odZWQ6XvgFeqG+hc1/DywjIIZuo14JXxnW Ug0CqtR+Ovkv4UFVkFjTz/RHjIKr83lTS4cmo4lc83rFC4Dmv7P5QuGNBxzyZJCSTJH4 U9Da5QznZ5YGz/UShNTrNKp+wYe2Zt50Z3ojZdhpdE3NHK7XjqqTBKoK9MofFg557Auy KTf0HRUqYGcMIHzaK92WW69S5jGsqtr7wkA1Rg6dbfh9e20/lrspxb2BGA9urt7zVKWR pTrWL/rwqjIwyjklhpEa8GbH/r7gYfJL8qtk3Jmt6hVcXOqrtcN46qsA+LUrfsTshLhS iuww== X-Gm-Message-State: AJcUukdxQi7SKG9F283Ty4m/7iVY67G1AbiV4JAqhXz1jc22MnG+UfLK +wYh8pScA7aRIQHZSDYi8jj8IPznro1Rwg== X-Google-Smtp-Source: ALg8bN6ZfUmKolV2PAJRXSQ5hHtFy8lpEgvmzvnBpme19JD/Wkb7AYSYdEYeFXCnFC7bk/0FjMjVrA== X-Received: by 2002:a1c:bc82:: with SMTP id m124mr527840wmf.77.1548096702192; Mon, 21 Jan 2019 10:51:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:14 +0000 Message-Id: <20190121185118.18550-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH 19/23] hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/misc/Makefile.objs | 1 + include/hw/misc/armsse-cpuid.h | 41 ++++++++++ hw/misc/armsse-cpuid.c | 134 ++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + default-configs/arm-softmmu.mak | 1 + hw/misc/trace-events | 4 + 6 files changed, 183 insertions(+) create mode 100644 include/hw/misc/armsse-cpuid.h create mode 100644 hw/misc/armsse-cpuid.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 04f3bfa516e..74c91d250c8 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -69,6 +69,7 @@ obj-$(CONFIG_TZ_PPC) +=3D tz-ppc.o obj-$(CONFIG_IOTKIT_SECCTL) +=3D iotkit-secctl.o obj-$(CONFIG_IOTKIT_SYSCTL) +=3D iotkit-sysctl.o obj-$(CONFIG_IOTKIT_SYSINFO) +=3D iotkit-sysinfo.o +obj-$(CONFIG_ARMSSE_CPUID) +=3D armsse-cpuid.o =20 obj-$(CONFIG_PVPANIC) +=3D pvpanic.o obj-$(CONFIG_AUX) +=3D auxbus.o diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h new file mode 100644 index 00000000000..0ef33fcaba2 --- /dev/null +++ b/include/hw/misc/armsse-cpuid.h @@ -0,0 +1,41 @@ +/* + * ARM SSE-200 CPU_IDENTITY register block + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "CPU_IDENTITY" register block which is part of t= he + * Arm SSE-200 and documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * + * QEMU interface: + * + QOM property "CPUID": the value to use for the CPUID register + * + sysbus MMIO region 0: the system information register bank + */ + +#ifndef HW_MISC_ARMSSE_CPUID_H +#define HW_MISC_ARMSSE_CPUID_H + +#include "hw/sysbus.h" + +#define TYPE_ARMSSE_CPUID "armsse-cpuid" +#define ARMSSE_CPUID(obj) OBJECT_CHECK(ARMSSECPUID, (obj), TYPE_ARMSSE_CPU= ID) + +typedef struct ARMSSECPUID { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + /* Properties */ + uint32_t cpuid; +} ARMSSECPUID; + +#endif diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c new file mode 100644 index 00000000000..7788f6ced6a --- /dev/null +++ b/hw/misc/armsse-cpuid.c @@ -0,0 +1,134 @@ +/* + * ARM SSE-200 CPU_IDENTITY register block + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the "CPU_IDENTITY" register block which is part of t= he + * Arm SSE-200 and documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * + * It consists of one read-only CPUID register (set by QOM property), plus= the + * usual ID registers. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/sysbus.h" +#include "hw/registerfields.h" +#include "hw/misc/armsse-cpuid.h" + +REG32(CPUID, 0x0) +REG32(PID4, 0xfd0) +REG32(PID5, 0xfd4) +REG32(PID6, 0xfd8) +REG32(PID7, 0xfdc) +REG32(PID0, 0xfe0) +REG32(PID1, 0xfe4) +REG32(PID2, 0xfe8) +REG32(PID3, 0xfec) +REG32(CID0, 0xff0) +REG32(CID1, 0xff4) +REG32(CID2, 0xff8) +REG32(CID3, 0xffc) + +/* PID/CID values */ +static const int sysinfo_id[] =3D { + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ + 0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ +}; + +static uint64_t armsse_cpuid_read(void *opaque, hwaddr offset, + unsigned size) +{ + ARMSSECPUID *s =3D ARMSSE_CPUID(opaque); + uint64_t r; + + switch (offset) { + case A_CPUID: + r =3D s->cpuid; + break; + case A_PID4 ... A_CID3: + r =3D sysinfo_id[(offset - A_PID4) / 4]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SSE CPU_IDENTITY read: bad offset 0x%x\n", (int)off= set); + r =3D 0; + break; + } + trace_armsse_cpuid_read(offset, r, size); + return r; +} + +static void armsse_cpuid_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + trace_armsse_cpuid_write(offset, value, size); + + qemu_log_mask(LOG_GUEST_ERROR, + "SSE CPU_IDENTITY: write to RO offset 0x%x\n", (int)offs= et); +} + +static const MemoryRegionOps armsse_cpuid_ops =3D { + .read =3D armsse_cpuid_read, + .write =3D armsse_cpuid_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + /* byte/halfword accesses are just zero-padded on reads and writes */ + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 4, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, +}; + +static Property armsse_cpuid_props[] =3D { + DEFINE_PROP_UINT32("CPUID", ARMSSECPUID, cpuid, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void armsse_cpuid_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + ARMSSECPUID *s =3D ARMSSE_CPUID(obj); + + memory_region_init_io(&s->iomem, obj, &armsse_cpuid_ops, + s, "armsse-cpuid", 0x1000); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void armsse_cpuid_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + /* + * This device has no guest-modifiable state and so it + * does not need a reset function or VMState. + */ + + dc->props =3D armsse_cpuid_props; +} + +static const TypeInfo armsse_cpuid_info =3D { + .name =3D TYPE_ARMSSE_CPUID, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(ARMSSECPUID), + .instance_init =3D armsse_cpuid_init, + .class_init =3D armsse_cpuid_class_init, +}; + +static void armsse_cpuid_register_types(void) +{ + type_register_static(&armsse_cpuid_info); +} + +type_init(armsse_cpuid_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index 52222117d77..42719880bad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -633,6 +633,8 @@ F: hw/misc/iotkit-sysctl.c F: include/hw/misc/iotkit-sysctl.h F: hw/misc/iotkit-sysinfo.c F: include/hw/misc/iotkit-sysinfo.h +F: hw/misc/armsse-cpuid.c +F: include/hw/misc/armsse-cpuid.h =20 Musicpal M: Jan Kiszka diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 3f200157879..be88870799c 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -118,6 +118,7 @@ CONFIG_ARMSSE=3Dy CONFIG_IOTKIT_SECCTL=3Dy CONFIG_IOTKIT_SYSCTL=3Dy CONFIG_IOTKIT_SYSINFO=3Dy +CONFIG_ARMSSE_CPUID=3Dy =20 CONFIG_VERSATILE=3Dy CONFIG_VERSATILE_PCI=3Dy diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 52466c77c4e..b0701bddd3c 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -132,3 +132,7 @@ iotkit_sysinfo_write(uint64_t offset, uint64_t data, un= signed size) "IoTKit SysI iotkit_sysctl_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit = SysCtl read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" iotkit_sysctl_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit= SysCtl write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" iotkit_sysctl_reset(void) "IoTKit SysCtl: reset" + +# hw/misc/armsse-cpuid.c +armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 = CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200= CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bbMrEQttECEQjo2HwYbstwzK4LFM5IR2j7Wqx0jx8pQ=; b=e2LCMT9LQ1Mdjr+1MMgPhcU5vqCfD42pcIcOC2kWUhNHqY2Hc1atNU7gxGo9xrxpVm 0L2D8irYgnl4IBD04V40VfOQYRYlzIR5e6GK+UuaKXe7jWiSzJfkCIwAARWuc+K/R7co Zck7bUIm2d70xj0kbfJ6chpxPUq+9MVMgmAnc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bbMrEQttECEQjo2HwYbstwzK4LFM5IR2j7Wqx0jx8pQ=; b=Cg7OdnGA+sZ0VVJacceMeT0yJuOcrqgkouHUdI/F29pn4MW11lx7z/mdLzqnE5vUbJ BiQ4C6Q/OFY5xDTMzC7+dQ8vh32e0+1cxcPMS3KJaqHZxKgj9o6qj2QIUKBN5RDgB1AP 22gCBlezTXv5T1mBpr2sL5lOaN9YBvAcQHsUXfaW5fw+W1LFk/wlqH+e/Zj1TJKmTR7Y 9jdObt5OkwikBj87B4LERhguYEWoYN5beRQ+LnxOlF0kdIOyiDNC7/ARdx0dM1j9/+tK PxDaNV6L6cwWcWLEmyTHgk61RqOHgA+Fv0lebkGenwvnicJKqrYCch3EmXKO3klQYXVh 2gHQ== X-Gm-Message-State: AJcUuke0fzpk3/HYKYrJ1kLnCac9a1tgLIAb3nZaVpRa6aHhMgYKtaHw Y9NpkDblVMFqXK52nS5JyvsZC9MTRwhP4A== X-Google-Smtp-Source: ALg8bN4uM0f+FMSiaksFJBXbe+NEu1SdpRLUM/SLXZfFST86d4sMexyn4KJPVciGmLmOvdTkKR0Iog== X-Received: by 2002:a7b:c757:: with SMTP id w23mr504644wmk.59.1548096703334; Mon, 21 Jan 2019 10:51:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:15 +0000 Message-Id: <20190121185118.18550-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH 20/23] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instantiate a copy of the CPU_IDENTITY register block for each CPU in an SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 961dbb3032a..3914e8e4bf2 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -78,6 +78,7 @@ #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" +#include "hw/misc/armsse-cpuid.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -153,6 +154,8 @@ typedef struct ARMSSE { UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 + ARMSSECPUID cpuid[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 9c111ac6a40..eb691faf720 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -34,6 +34,7 @@ struct ARMSSEInfo { bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; + bool has_cpuid; }; =20 static const ARMSSEInfo armsse_variants[] =3D { @@ -47,6 +48,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_ppus =3D false, .has_cachectrl =3D false, .has_cpusecctrl =3D false, + .has_cpuid =3D false, }, }; =20 @@ -314,6 +316,16 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpuid%d", i); + + sysbus_init_child_obj(obj, name, &s->cpuid[i], + sizeof(s->cpuid[i]), + TYPE_ARMSSE_CPUID); + g_free(name); + } + } object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, sizeof(s->nmi_orgate), TYPE_OR_IRQ, &error_abort, NULL); @@ -864,6 +876,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) memory_region_add_subregion(&s->cpu_container[i], 0x50011000, = mr); } } + if (info->has_cpuid) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i); + object_property_set_bool(OBJECT(&s->cpuid[i]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); + } + } =20 /* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region = */ /* Devices behind APB PPC1: --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098487634128.4224410201573; Mon, 21 Jan 2019 11:21:27 -0800 (PST) Received: from localhost ([127.0.0.1]:58547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf8N-0002CR-3G for importer@patchew.org; Mon, 21 Jan 2019 14:21:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevP-0007jF-Nl for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:08:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefh-0002wL-JN for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:48 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:33433) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefh-0002vv-CI for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:45 -0500 Received: by mail-wr1-x442.google.com with SMTP id c14so24667087wrr.0 for ; Mon, 21 Jan 2019 10:51:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y0iJP1/0IWSi2a//xChFZD3ZT9ballXzK0ZjLQwVNl8=; b=L/V3fAmOrajnLxIzBOWs3x+pFR3SCRdZ1OX/H++FufMgmt8nooRFHp8b+BOJxnOAyk N7daPs0ZVixlYoj23Q/4gEeVdRWkQXUNdvGGG43WZtU0NtXTbPk8bd9O2z0a6QSvgVGO VmWSHiIGcDjEFRp+2ge/EXNA87V3598kxjMTo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y0iJP1/0IWSi2a//xChFZD3ZT9ballXzK0ZjLQwVNl8=; b=SH4kalsZn4YDAJETeFfLlGDQADbWq/aTewbugDw+cIpowULhAnilcX2/qJjHxpgACk TgQTiHBay820sS51vCLU7jCA867FF7bA3dUnWm+wEy/XU83oCcPMQ7I8/TPe2EXqAHq9 ld8pOqKz3l836U6oAnnPyOHxQ4C+Pkw0v6wiRRM9eSjjZQm2tD3aNHky8ASiQGYuLPQc KE9TlWeBEFQjfVeQth7XdLLU4u5+YduDfC+dVGTzZM/EhZv5/lBrnUdljOCF4VOgkouN as5bWw3ANXuoRehYBbl0VqP5wUkTWMhFbkiBm8SGzJdwsi7yS6VmGjy1W/8ua5nnqZU/ fHVg== X-Gm-Message-State: AJcUukfAjvsTk2byUG9grmAXNoFjELcJjOYy3nvvy3HfuX/gbBCB/dVU VnHYUIgHdtLDj0u/cr8hVlS7uw== X-Google-Smtp-Source: ALg8bN7mn8BBfV+t0ww8EfNNo+ogUUTdsnWiD2ensAtoc0SxdHlyxwLKoAWKGDoAMxZoH3NtRSJCIw== X-Received: by 2002:adf:9f10:: with SMTP id l16mr30473940wrf.206.1548096704432; Mon, 21 Jan 2019 10:51:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:16 +0000 Message-Id: <20190121185118.18550-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH 21/23] hw/arm/armsse: Add SSE-200 model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a model of the SSE-200, now we have put in all the code that lets us make it different from the IoTKit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/armsse.h | 19 ++++++++++++++++--- hw/arm/armsse.c | 12 ++++++++++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 3914e8e4bf2..f800bafb14a 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -1,5 +1,5 @@ /* - * ARM SSE (Subsystems for Embedded): IoTKit + * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 * * Copyright (c) 2018 Linaro Limited * Written by Peter Maydell @@ -12,9 +12,13 @@ /* * This is a model of the Arm "Subsystems for Embedded" family of * hardware, which include the IoT Kit and the SSE-050, SSE-100 and - * SSE-200. Currently we model only the Arm IoT Kit which is documented in + * SSE-200. Currently we model: + * - the Arm IoT Kit which is documented in * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm060125= 6/index.html - * It contains: + * - the SSE-200 which is documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/core= link_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_0= 0_en.pdf + * + * The IoTKit contains: * a Cortex-M33 * the IDAU * some timers and watchdogs @@ -23,6 +27,14 @@ * a security controller * a bus fabric which arranges that some parts of the address * space are secure and non-secure aliases of each other + * The SSE-200 additionally contains: + * a second Cortex-M33 + * two Message Handling Units (MHUs) + * an optional CryptoCell (which we do not model) + * more SRAM banks with associated MPCs + * multiple Power Policy Units (PPUs) + * a control interface for an icache for each CPU + * per-CPU identity and control register blocks * * QEMU interface: * + QOM property "memory" is a MemoryRegion containing the devices provi= ded @@ -93,6 +105,7 @@ * them via the ARMSSE base class, so they have no IOTKIT() etc macros. */ #define TYPE_IOTKIT "iotkit" +#define TYPE_SSE200 "sse-200" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index eb691faf720..5d53071a5a0 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -50,6 +50,18 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D false, .has_cpuid =3D false, }, + { + .name =3D TYPE_SSE200, + .sram_banks =3D 4, + .num_cpus =3D 2, + .sys_version =3D 0x22041743, + .sys_config_format =3D SSE200Format, + .has_mhus =3D true, + .has_ppus =3D true, + .has_cachectrl =3D true, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + }, }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098107472525.5824288415731; Mon, 21 Jan 2019 11:15:07 -0800 (PST) Received: from localhost ([127.0.0.1]:58402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf2I-0005kJ-71 for importer@patchew.org; Mon, 21 Jan 2019 14:15:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevN-00081G-Uj for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:07:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefi-0002xA-UU for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:49 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:33445) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefi-0002we-K3 for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:46 -0500 Received: by mail-wm1-x341.google.com with SMTP id r24so6819296wmh.0 for ; Mon, 21 Jan 2019 10:51:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yb+iGSLny/NNKQr0eBfsaeiJgzhFFuz8UhpvCuLEuGQ=; b=A7I/5q9cXc9mckH8SWkYhVVGGpKGt1aG6AbtZF9CIN6RK69DzBblaj3ory+n/dJ3B+ wKYaW2jQpEWcdm4dIzxCA7gybsgO+QWFyUszgYWKFB2cAo41ASUlCfM7Fbg6Jdg56Gsm jwGei6/ir6KSAwMnXVJ/t3bYmn7CQI0xJ0NNM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yb+iGSLny/NNKQr0eBfsaeiJgzhFFuz8UhpvCuLEuGQ=; b=HUzun1nj6R6cDil/r1sPyNGzg/bYXZvZnaBrRcq8jrnn6JpaCBhwY1lhUn9j/kOXIx gPXYXErBDAjCsgO/xEMxasfgmy7JeZt86qgvsJbEmSY/6yX4VqO+UV5AMqtu5FCPlzxg I1enFjWnSW+ySgOhl3EyjtsUsVBIWBR24YgkedWji92wGia789SO241NoQ6yK6VO05uu TPazxVRhqZjru3yVtw5s5frdNvzTtfl4SrDScD+gU+H+fR4kZoHDNMLXdm673PEXUwi9 oo+HL+/1xBakzOZY492bhohGvB1IgKKKJcfmIJpuoLR6D+LoOl77sjn1MdDbEwmKbnE0 PVww== X-Gm-Message-State: AJcUukfiuIy7sVanfZbbgwgq+rIUrOW9zgj9CWm0FqSRqf9j9jtCLMUi swlUh9AEjgs6+aXhbVT0ThiMQQ== X-Google-Smtp-Source: ALg8bN6yesf6W/5VfsxAPADUYmK/8rflni+KaKI1SwDDcNF35Y2zfK0E7VTwnXjz9bll+gd5mJbJQQ== X-Received: by 2002:a1c:e046:: with SMTP id x67mr558024wmg.122.1548096705604; Mon, 21 Jan 2019 10:51:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:17 +0000 Message-Id: <20190121185118.18550-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH 22/23] hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In preparation for adding support for the AN521 MPS2 image, we need to handle wiring up the MPS2 device interrupt lines to both CPUs in the SSE-200, rather than just the one that the IoTKit has. Abstract out a "connect to the IoTKit interrupt line" function and make it connect to a splitter which feeds both sets of inputs for the SSE-200 case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 79 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 20 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 3859f17d98b..95adcd478ab 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -53,8 +53,11 @@ #include "net/net.h" #include "hw/core/split-irq.h" =20 +#define MPS2TZ_NUMIRQ 92 + typedef enum MPS2TZFPGAType { FPGA_AN505, + FPGA_AN521, } MPS2TZFPGAType; =20 typedef struct { @@ -85,6 +88,7 @@ typedef struct { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; } MPS2TZMachineState; =20 #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -111,6 +115,23 @@ static void make_ram_alias(MemoryRegion *mr, const cha= r *name, memory_region_add_subregion(get_system_memory(), base, mr); } =20 +static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) +{ + /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + + assert(irqno < MPS2TZ_NUMIRQ); + + switch (mmc->fpga_type) { + case FPGA_AN505: + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); + case FPGA_AN521: + return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); + default: + g_assert_not_reached(); + } +} + /* Most of the devices in the AN505 FPGA image sit behind * Peripheral Protection Controllers. These data structures * define the layout of which devices sit behind which PPCs. @@ -161,7 +182,6 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,= void *opaque, int txirqno =3D i * 2 + 1; int combirqno =3D i + 10; SysBusDevice *s; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); DeviceState *orgate_dev =3D DEVICE(&mms->uart_irq_orgate); =20 sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), @@ -170,14 +190,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mm= s, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); s =3D SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", txirqno)); - sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } =20 @@ -213,7 +230,6 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, const char *name, hwaddr size) { SysBusDevice *s; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); NICInfo *nd =3D &nd_table[0]; =20 /* In hardware this is a LAN9220; the LAN9118 is software compatible @@ -225,7 +241,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *m= ms, void *opaque, qdev_init_nofail(mms->lan9118); =20 s =3D SYS_BUS_DEVICE(mms->lan9118); - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", = 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); return sysbus_mmio_get_region(s, 0); } =20 @@ -315,12 +331,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms,= void *opaque, =20 s =3D SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 58 + i * 3)= ); - sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 56 + i * 3)= ); - sysbus_connect_irq(s, 2, qdev_get_gpio_in_named(iotkitdev, - "EXP_IRQ", 57 + i * 3)= ); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); =20 g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -339,21 +352,20 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms= , void *opaque, */ PL022State *spi =3D opaque; int i =3D spi - &mms->spi[0]; - DeviceState *iotkitdev =3D DEVICE(&mms->iotkit); SysBusDevice *s; =20 sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]), TYPE_PL022); object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); s =3D SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 51 + i= )); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); return sysbus_mmio_get_region(s, 0); } =20 static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); MachineClass *mc =3D MACHINE_GET_CLASS(machine); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *iotkitdev; @@ -371,11 +383,38 @@ static void mps2tz_common_init(MachineState *machine) iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), "memory", &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", &error_fatal); =20 + /* + * The AN521 needs us to create splitters to feed the IRQ inputs + * for each CPU in the SSE-200 from each device in the board. + */ + if (mmc->fpga_type =3D=3D FPGA_AN521) { + for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { + char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); + SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; + + object_initialize_child(OBJECT(machine), name, + splitter, sizeof(*splitter), + TYPE_SPLIT_IRQ, &error_fatal, NULL); + g_free(name); + + object_property_set_int(OBJECT(splitter), 2, "num-lines", + &error_fatal); + object_property_set_bool(OBJECT(splitter), true, "realized", + &error_fatal); + qdev_connect_gpio_out(DEVICE(splitter), 0, + qdev_get_gpio_in_named(DEVICE(&mms->iotk= it), + "EXP_IRQ", i)); + qdev_connect_gpio_out(DEVICE(splitter), 1, + qdev_get_gpio_in_named(DEVICE(&mms->iotk= it), + "EXP_CPU1_IRQ", i= )); + } + } + /* The sec_resp_cfg output from the IoTKit must be split into multiple * lines, one for each of the PPCs we create here, plus one per MSC. */ @@ -426,7 +465,7 @@ static void mps2tz_common_init(MachineState *machine) object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, "realized", &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15)= ); + get_sse_irq_in(mms, 15)); =20 /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: --=20 2.20.1 From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1548098127987463.4184783612832; Mon, 21 Jan 2019 11:15:27 -0800 (PST) Received: from localhost ([127.0.0.1]:58404 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glf2V-0005wZ-9K for importer@patchew.org; Mon, 21 Jan 2019 14:15:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1glevN-000888-SZ for qemu-devel@nongnu.org; Mon, 21 Jan 2019 14:07:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1glefk-0002yI-3O for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:49 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:52812) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1glefj-0002xS-QF for qemu-devel@nongnu.org; Mon, 21 Jan 2019 13:51:47 -0500 Received: by mail-wm1-x343.google.com with SMTP id m1so11842356wml.2 for ; Mon, 21 Jan 2019 10:51:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n82sm50386660wma.42.2019.01.21.10.51.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 10:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JNtduwYQb9S31DnKOmDqWMP8TZCY2KnxF33CO6L/1os=; b=UmFxpTCyQNPsd5yCz3IUG6NDUQgDTjtRNvrJkg/jl0KKO9fLl6vg6uJsaM+7eIVoOC Oze52UFN9sCOQqMHMzDYLIvmT6oMGkaY8HzgYdEp+f9QGE+hqqQeLrJ0zDb7uPapXqMw EHeR8uZdmLNyhUH7P/18x96aaILmDt8Nwxweo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JNtduwYQb9S31DnKOmDqWMP8TZCY2KnxF33CO6L/1os=; b=DS1FPKEHzJpABp3xXLSZScywaMjLZFEpq2xbZ8O38yZsTSf1dK6I8ZzItfVUBaDdms cJj+G2b8hv3+L9QlozwijXOoC5HTJA0s/wNfbLaziPsCghXRG8nm6+Bf1y/HdOuROuQa /Zb8xYqn8TBylGSOhZLZ1mZSxuQKET39zf6kLolyfR0YoODdqF80hlCLBVFhBWk6GMRt 97drtsqMtLOINJs6U9yd/7EjBMSm9zFrwpGmMJDedgThMinL6MOLVjownrnIMuPUWXpk f6kdem3svqNRtOJZqIb8HkASN96Bs28NO+nDkFk8LnZakcQ26EwQXAUIwwdRyzfE6yra /0FA== X-Gm-Message-State: AJcUukeQISqNqzvEI8e5al5tJU5IUgkGpkqvjH3iHtBP3BDS2UYt3Kid HnwP50CMuOSQ3xaeZPPpkPl68w== X-Google-Smtp-Source: ALg8bN69eiRqlsu349udfgkapvP9rtlYzrrbqAcJPe9kkJfgGAjBPd7BDEtg37MjdCYsq+HZZFuJaQ== X-Received: by 2002:a1c:d74a:: with SMTP id o71mr531544wmg.73.1548096706692; Mon, 21 Jan 2019 10:51:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 21 Jan 2019 18:51:18 +0000 Message-Id: <20190121185118.18550-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190121185118.18550-1-peter.maydell@linaro.org> References: <20190121185118.18550-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH 23/23] hw/arm/mps2-tz: Add mps2-an521 model X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a model of the MPS2 FPGA image described in Application Note AN521. This is identical to the AN505 image, except that it uses the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/mps2-tz.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 95adcd478ab..f5f0b0e0fa5 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -15,6 +15,7 @@ * as seen by the guest depend significantly on the FPGA image. * This source file covers the following FPGA images, for TrustZone cores: * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 + * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -24,10 +25,16 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/vers= atile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_techni= cal_reference_100112_0200_06_en.pdf * Application Note AN505: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * Application Note AN521: + * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=3D/com.arm.doc.ecm0601= 256/index.html + * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * most of the device layout: + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/cor= elink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_= 00_en.pdf + * */ =20 #include "qemu/osdep.h" @@ -64,6 +71,7 @@ typedef struct { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + const char *armsse_type; } MPS2TZMachineClass; =20 typedef struct { @@ -93,6 +101,7 @@ typedef struct { =20 #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") +#define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") =20 #define MPS2TZ_MACHINE(obj) \ OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) @@ -379,7 +388,7 @@ static void mps2tz_common_init(MachineState *machine) } =20 sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, - sizeof(mms->iotkit), TYPE_IOTKIT); + sizeof(mms->iotkit), mmc->armsse_type); iotkitdev =3D DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), "memory", &error_abort); @@ -632,7 +641,6 @@ static void mps2tz_class_init(ObjectClass *oc, void *da= ta) IDAUInterfaceClass *iic =3D IDAU_INTERFACE_CLASS(oc); =20 mc->init =3D mps2tz_common_init; - mc->max_cpus =3D 1; iic->check =3D mps2_tz_idau_check; } =20 @@ -642,9 +650,28 @@ static void mps2tz_an505_class_init(ObjectClass *oc, v= oid *data) MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); =20 mc->desc =3D "ARM MPS2 with AN505 FPGA image for Cortex-M33"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; mmc->fpga_type =3D FPGA_AN505; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id =3D 0x41045050; + mmc->armsse_type =3D TYPE_IOTKIT; +} + +static void mps2tz_an521_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; + mc->default_cpus =3D 2; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN521; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id =3D 0x41045210; + mmc->armsse_type =3D TYPE_SSE200; } =20 static const TypeInfo mps2tz_info =3D { @@ -666,10 +693,17 @@ static const TypeInfo mps2tz_an505_info =3D { .class_init =3D mps2tz_an505_class_init, }; =20 +static const TypeInfo mps2tz_an521_info =3D { + .name =3D TYPE_MPS2TZ_AN521_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps2tz_an521_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); + type_register_static(&mps2tz_an521_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1