Series comparison

v1->v2 changes: fix a clang warning about bitfields;
drop a patch from Julia that I accidentally included
(it will likely be in a future series).

The following changes since commit a8d2b0685681e2f291faaa501efbbd76875f8ec8:

Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190118' into staging (2019-01-18 16:56:15 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190121

for you to fetch changes up to 0d4bfd7df809863b1f45fad35229fb9419527d06:

target/arm: Implement PMSWINC (2019-01-21 10:38:56 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/char/stm32f2xx_usart: Do not update data register when device is disabled
 * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
 * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
 * ftgmac100: implement the new MDIO interface on Aspeed SoC
 * implement the ARMv8.3-PAuth extension
 * improve emulation of the ARM PMU

----------------------------------------------------------------
Aaron Lindsay (13):
      migration: Add post_save function to VMStateDescription
      target/arm: Reorganize PMCCNTR accesses
      target/arm: Swap PMU values before/after migrations
      target/arm: Filter cycle counter based on PMCCFILTR_EL0
      target/arm: Allow AArch32 access for PMCCFILTR
      target/arm: Implement PMOVSSET
      target/arm: Define FIELDs for ID_DFR0
      target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
      target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
      target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
      target/arm: PMU: Add instruction and cycle events
      target/arm: PMU: Set PMCR.N to 4
      target/arm: Implement PMSWINC

Alexander Graf (1):
      target/arm: Allow Aarch32 exception return to switch from Mon->Hyp

Cédric Le Goater (1):
      ftgmac100: implement the new MDIO interface on Aspeed SoC

Eric Auger (1):
      hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node

Philippe Mathieu-Daudé (1):
      hw/char/stm32f2xx_usart: Do not update data register when device is disabled

Richard Henderson (31):
      target/arm: Add state for the ARMv8.3-PAuth extension
      target/arm: Add SCTLR bits through ARMv8.5
      target/arm: Add PAuth active bit to tbflags
      target/arm: Introduce raise_exception_ra
      target/arm: Add PAuth helpers
      target/arm: Decode PAuth within system hint space
      target/arm: Rearrange decode in disas_data_proc_1src
      target/arm: Decode PAuth within disas_data_proc_1src
      target/arm: Decode PAuth within disas_data_proc_2src
      target/arm: Move helper_exception_return to helper-a64.c
      target/arm: Add new_pc argument to helper_exception_return
      target/arm: Rearrange decode in disas_uncond_b_reg
      target/arm: Decode PAuth within disas_uncond_b_reg
      target/arm: Decode Load/store register (pac)
      target/arm: Move cpu_mmu_index out of line
      target/arm: Introduce arm_mmu_idx
      target/arm: Introduce arm_stage1_mmu_idx
      target/arm: Create ARMVAParameters and helpers
      target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
      target/arm: Export aa64_va_parameters to internals.h
      target/arm: Add aa64_va_parameters_both
      target/arm: Decode TBID from TCR
      target/arm: Reuse aa64_va_parameters for setting tbflags
      target/arm: Implement pauth_strip
      target/arm: Implement pauth_auth
      target/arm: Implement pauth_addpac
      target/arm: Implement pauth_computepac
      target/arm: Add PAuth system registers
      target/arm: Enable PAuth for -cpu max
      target/arm: Enable PAuth for user-only
      target/arm: Tidy TBI handling in gen_a64_set_pc

v3->v4: Windows headers define an INT type which clashed
with an enum value name in arm_gicv3_its.c...

The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3

for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814:

hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100)

----------------------------------------------------------------
target-arm queue:
 * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
   line user-created devices are not plugged into them
 * Take an exception if PSTATE.IL is set
 * Support an emulated ITS in the virt board
 * Add support for kudo-bmc board
 * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
 * cadence_uart: Fix clock handling issues that prevented
   u-boot from running

----------------------------------------------------------------
Bin Meng (6):
      hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase
      hw/char: cadence_uart: Disable transmit when input clock is disabled
      hw/char: cadence_uart: Move clock/reset check to uart_can_receive()
      hw/char: cadence_uart: Convert to memop_with_attrs() ops
      hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}()
      hw/char: cadence_uart: Log a guest error when device is unclocked or in reset

Chris Rauer (1):
      hw/arm: Add support for kudo-bmc board.

Marc Zyngier (1):
      hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM

Peter Maydell (5):
      target/arm: Take an exception if PSTATE.IL is set
      qdev: Support marking individual buses as 'full'
      hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
      hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
      hw/arm/mps2.c: Mark internal-only I2C buses as 'full'

Richard Henderson (1):
      target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn

Shashi Mallela (9):
      hw/intc: GICv3 ITS initial framework
      hw/intc: GICv3 ITS register definitions added
      hw/intc: GICv3 ITS command queue framework
      hw/intc: GICv3 ITS Command processing
      hw/intc: GICv3 ITS Feature enablement
      hw/intc: GICv3 redistributor ITS processing
      tests/data/acpi/virt: Add IORT files for ITS
      hw/arm/virt: add ITS support in virt GIC
      tests/data/acpi/virt: Update IORT files for ITS