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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kHTSX5NGByNnmxvKz+XqxQ+dW8UgrlMDmlLspukCIzE=; b=ht2SPQbLrrTaTW7eelwETRY5XKrxCZWH7zjONPq9gWyPwS7gQ9iuEZ+D9T0D992s4z eFp7OWw51JVFoktuva/TvvFDJZROfrKrO5npL0OWauspmlAd/AWZlu80pepgTXr5oceT 3u3g5b/eXojsXeJl8I6SkTd4sMWWoPymmOna8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kHTSX5NGByNnmxvKz+XqxQ+dW8UgrlMDmlLspukCIzE=; b=aZaT9Q7FdnCgXgOHEiGSY8agLEHjR0BKGQToJYi06lOjoXZkZtanMRvmmS7TD6fetj DDPGtBB54y9IoBmQdu1fn6xHkHDNxYCItSh8mkHv5Z7HylG/ur3LgIVUQHTc4/8EKiG5 TSL1+7yqXSS6dLJGWAsnbbffkCHDnIhqayjwUaGeDrFPu7pJYodsxdyxqCIe1iubT/aZ 9ut12PJCz4/5H5bBJCC7oeDd+ZIH2ribM3kshb3u6GR0BiM04fr1as2xTvDRUwBai7Sq ZhTluVomEvPI3Orqvje4CCL9hDCmt6oCzsRZQM/VNzLQKCdz6JSmN0eqMpmcNJoyhc0+ saIw== X-Gm-Message-State: AJcUukfdp7XaFixoZ0dKm8ouw2Dhm6gfpt1+t17dmqi72HJsvhuksA7v Fmfo/bVRcaXgboSbC4AV3zKjBQ9ViJh+dQ== X-Google-Smtp-Source: ALg8bN4JUbZEvUTl974B22YCONNZi0D4uhAK4WZ1q0Twedffg0TxUbtdxofY4r3Iby77Z1OdjfMLtg== X-Received: by 2002:a5d:61c4:: with SMTP id q4mr16190212wrv.308.1547823495359; Fri, 18 Jan 2019 06:58:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:23 +0000 Message-Id: <20190118145805.6852-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 Subject: [Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190108223129.5570-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/translate.h | 2 ++ target/arm/helper.c | 19 +++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 843d5936ead..9ad7b2d11ed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3014,6 +3014,7 @@ FIELD(TBFLAG_A64, TBI0, 0, 1) FIELD(TBFLAG_A64, TBI1, 1, 1) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) =20 static inline bool bswap_code(bool sctlr_b) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 1550aa8bc7f..d8a8bb4e9c0 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -68,6 +68,8 @@ typedef struct DisasContext { bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; + /* True if v8.3-PAuth is active. */ + bool pauth_active; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ int c15_cpar; /* TCG op of the current insn_start. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 9bf8fbd8f9b..caea722c9b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12983,6 +12983,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); flags =3D FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } + + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + uint64_t sctlr; + if (current_el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr =3D env->cp15.sctlr_el[1]; + } else { + sctlr =3D env->cp15.sctlr_el[current_el]; + } + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB= )) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b7b6ab63716..37a57af7150 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13409,6 +13409,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->fp_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); dc->sve_excp_el =3D FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); dc->sve_len =3D (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; + dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.20.1