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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.59.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:59:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A0tTd0Ye0qOEy2FvxSDHiS9QolicCnqicPFFMf3sHVQ=; b=MeCkT3B5PNyaCHEGlC2UnTuSsk8uGfURMRzRp+GqfwHYhCdFnkdZil1/mXZUsa1iII P2vrQJZMpUYG/NM2PbGiO9XpNkK0xnPnnB5dy0AfzibQFB6bOCJZKcQEY0f4Gzl83+4g KdJmLLNw+5LReWfPF/3uC2EEPQEEROkQ9rS4o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A0tTd0Ye0qOEy2FvxSDHiS9QolicCnqicPFFMf3sHVQ=; b=Pvk6ruMnwif55UgYNAbHYAe/T96VbPKf6AXaaDDySn/0FOUZnjQvYG8K6tPfGNYQX2 +HaJR//A90iSpC8OorHCH4x/fpQBN92qbptu77VwFlvYeGce9p84J+NSL6tl74mB9q30 Km2tDA4k/75LUpvlf1wCYDbjiTlVAQ8e38aGlln8BW+xPFEfKVo5kZF0GJCj4LLL67PF ScAcVMstOS7VUubxM0C363fzDdEUvPiyNZk5lkVTdv8AKOIj+ru2wW6S7vmbAw22FTVW J0maOKOCXGIMal2aphNXNrkQ2keLaYYchBt3DbSYKvC3OdnXuj42rqFVCj6SUYrQYIL5 xw+Q== X-Gm-Message-State: AJcUukcQPRYrLpwt1TeyRsKAH6A7xJTNJgYfHYPBWsUKb8P5bf4RaMN/ 1ZdQllYfOYCTWdekzXN/hw9K6EohsOoucQ== X-Google-Smtp-Source: ALg8bN4XDvTm1kMZNb7PW0zx0AXeZN1rs5Y4ZxoxnAKZhbWaWw1+00PhWC+9renoKtXu1LjBLtaQ3w== X-Received: by 2002:a5d:5409:: with SMTP id g9mr17165949wrv.88.1547823542628; Fri, 18 Jan 2019 06:59:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:58:03 +0000 Message-Id: <20190118145805.6852-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 Subject: [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 35c105a8618..44f1340ee13 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1777,7 +1777,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5671,10 +5671,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement only the cycle - * count register. + * field as main ID register, and we implement four counters in + * addition to the cycle count register. */ - unsigned int i, pmcrn =3D 0; + unsigned int i, pmcrn =3D 4; ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5689,7 +5689,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 2.20.1