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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=S/qqrw9ofUyLKjwrlgJWgrQVe/kmqv1T17tQGkWmER4=; b=Cc+VdnpDIv3gwTi0UlygiUPdmawrAlA3YXOot9rxvYyIx5rX9Ut9ZRkhJ/bgs/qZwi FvCIAc5kBjvrvCmphVOmb/ZGd6RM+yGcnc3LJXnAzX6pNqMOFZMp+/bPOCd57sJodvMn 3xRGh7TEhGkn5EJ2nBLWolq0oxPLA7A0jUaXM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S/qqrw9ofUyLKjwrlgJWgrQVe/kmqv1T17tQGkWmER4=; b=G0m9IUWrZ3SfSSOCREDrVML7MxFVXuvrU/Avz4QESHaogYMaUyW9vnKYnvklf0CHN/ rL3paZ72Z8Gy9Fa4Dc0wNcYP3jL/cv5fXvA/d9IRLjdSjssgXQPpLyTqvQvhHoYR7PNk VWTkLYxkefTRmkL8jv2FZSJTtms7YXNP0L0IVxupENRbWC1Rs9WoYREFVq8biIDE4ODf PcTfJnms/Fg1K4RljmamwtqYnjNv+Xxl+Ql0ZK+XW0cWA2jSz99ikiNdF+Exs/uBikwf 3T1YR3AxiCft1vvg5QTD6Foxzt0f23IpdBirLYreY109bmU4x7U4MC1RuivhFVKxlWeq fREg== X-Gm-Message-State: AJcUukeNC2Z4rPnEB633T3nh+CAhOkOvCIFnE7s8gRm/jsCoSg0+2Mfh fzdftBzySg2u3lWj8RN6rZrI59DkJ2XZjQ== X-Google-Smtp-Source: ALg8bN5gSVhmi9fo4jjcH0O4pTTqQV8J/cKE8p8ml1iH+5X/m20MO4AFXD0QaYNTm6c7fFvosRhafg== X-Received: by 2002:a1c:834c:: with SMTP id f73mr16179452wmd.126.1547823534125; Fri, 18 Jan 2019 06:58:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:57 +0000 Message-Id: <20190118145805.6852-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c Subject: [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8635220f34a..460ab713d20 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const ARM= CPRegInfo *ri, env->cp15.c9_pmovsr &=3D ~value; } =20 +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr |=3D value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1718,6 +1725,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5360,6 +5385,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle --=20 2.20.1