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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hq4QS5RPobZeGpNsDMA6FS3mXhorl1b6YwcgrpD/q/I=; b=TWidqEleIAG3J9f2GV+T8CRI7wMPIKMiFZN2itJoKOvPtVANyPqAghgzcEzuYtLX2l v+GfTTorYnIvyuIdeLVM4xCES1XlI86VnSpkqIzXFiyBOGv6VEjy6QjpEgs7dUy7LHIW iyQVeqpIvXFUtf8bF3YtutUCLgKhBXUIpqt8o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hq4QS5RPobZeGpNsDMA6FS3mXhorl1b6YwcgrpD/q/I=; b=gWHigj/EV7PwMJH87xomEUttMDNALR+eQptO7bxAu4cOi4+hn32SXEvu+nXoyXl8qh +whWb+ZmOHmGh5PcWzVWrK+iD3vUgudYfDRMcD/JXkfunCc5YHloWSFrhYmK2W98cSZf Gf+wxrUH4hZlX6cNs7ZulGsJDQv30+zau4frfo4nIR7Q18Qu9XuDyKyYTHonoUWEtTu1 LC56GE2CmJlZSQW85HM5o3uaVGJb9PAmrb05OBNeRuxJTkl5EhS6W42dYZIsKsWN6l2U zJ+LMuqgVFlVFd+rtuS8WEhekZBXYrXMKyRdCoTiru6Kv/tx4zYjl1W+b9WQ3IGsVD5i kdPQ== X-Gm-Message-State: AJcUukcywZ6rUyn1ywEjkCBFlY+3/+1d6y2k6oX6FEaP1+QsDiTDbqi+ DKh9F6iBy0X6eYiMKy4OX0H0XjKi1D+iSQ== X-Google-Smtp-Source: ALg8bN50JxzYpq3iGRDCGLj1Mg28GCDEJwn3/vJlwMI6E/fW23g+8aABkDx0fzqBQsS9lSsB1+UE0A== X-Received: by 2002:adf:fe8f:: with SMTP id l15mr2053255wrr.313.1547823530447; Fri, 18 Jan 2019 06:58:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:54 +0000 Message-Id: <20190118145805.6852-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 Subject: [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- target/arm/machine.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c49e0d70cbb..733cfdc5a0f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1459,11 +1459,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, #endif { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, + .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), diff --git a/target/arm/machine.c b/target/arm/machine.c index 7a22ebc2098..b2925496148 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ @@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque) return 0; } =20 +static int cpu_post_save(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + + return 0; +} + static int cpu_pre_load(void *opaque) { ARMCPU *cpu =3D opaque; @@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + return 0; } =20 @@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + return 0; } =20 @@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu =3D { .version_id =3D 22, .minimum_version_id =3D 22, .pre_save =3D cpu_pre_save, + .post_save =3D cpu_post_save, .pre_load =3D cpu_pre_load, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { --=20 2.20.1