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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ibJA1Pn4ZggBQ0KWPQjUjTUyhTXKj0cTxBtMKg2jwrY=; b=Qh+0iGIzYDjqF2pCo9MfNtxvoXl7pgE3ZbDeZrkhAoam7KdnTfAEcZkVZwwz3yajpl NcIguJ+BAb98wOkjP2fZ19/baIIUmRAwNPl6f9KnNwLAoNTAbILq1k444h6V1D32o2zP pf23MQ3pTYOMIadEYW+AN0/zwyaoScgBEsA8k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ibJA1Pn4ZggBQ0KWPQjUjTUyhTXKj0cTxBtMKg2jwrY=; b=MV7k0vDZEkdP8HpnHkhec2yMbFdTDp3zTUiWzE/N+qbGPi4BZqscnTR57qgcRkkhmJ ro8TParZX++tTx1Ax1ZwvXh0oMW7IHRuDL7W+ilMkLeyISYONDPT8BN7+AjX20Vx5gPR foUB2mPqnqMvxHoH+xtUhLb4q76ck+/wmW6w1G4YZTBw+HhFIvtO0FBTiuJz5tQVJX7V EvOwqFKgJOVLqECJ5+TO7BuB0byxEkzSfuu+kX0y5s03b6RTxbkZBki34qOkK3NNNcSy MP6uKNwpw9eJyslv3vjIFmOfzxRSYSiYQt+VGeMrBVdyI5yhAWDFEmEK5xvS3DpAn5cK dQaw== X-Gm-Message-State: AJcUuketmTXRpK7JtuG1DYTUS29fJPFMOxVFb7ZHhQBLbiQ5wSvbMJVi Ww6qxI+KXmC24HhKKzhA/99l3cp64wQ5CQ== X-Google-Smtp-Source: ALg8bN4uwXzT0bjU4I37Uwqd5UZdxalhSzPHrEEZyFbx5MjlT4zGDDN+vRRVJz2Z3oOdr5i8R1O/Uw== X-Received: by 2002:a1c:4e08:: with SMTP id g8mr15634834wmh.46.1547823527127; Fri, 18 Jan 2019 06:58:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:51 +0000 Message-Id: <20190118145805.6852-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We can perform this with fewer operations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190108223129.5570-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 62 +++++++++++++------------------------- 1 file changed, 21 insertions(+), 41 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f49fe1de3a8..4d28a27c3bd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -261,7 +261,7 @@ void gen_a64_set_pc_im(uint64_t val) /* Load the PC from a generic TCG variable. * * If address tagging is enabled via the TCR TBI bits, then loading - * an address into the PC will clear out any tag in the it: + * an address into the PC will clear out any tag in it: * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 @@ -280,54 +280,34 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) int tbi =3D s->tbii; =20 if (s->current_el <=3D 1) { - /* Test if NEITHER or BOTH TBI values are set. If so, no need to - * examine bit 55 of address, can just generate code. - * If mixed, then test via generated code - */ - if (tbi =3D=3D 3) { - TCGv_i64 tmp_reg =3D tcg_temp_new_i64(); - /* Both bits set, sign extension from bit 55 into [63:56] will - * cover both cases - */ - tcg_gen_shli_i64(tmp_reg, src, 8); - tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); - tcg_temp_free_i64(tmp_reg); - } else if (tbi =3D=3D 0) { - /* Neither bit set, just load it as-is */ - tcg_gen_mov_i64(cpu_pc, src); - } else { - TCGv_i64 tcg_tmpval =3D tcg_temp_new_i64(); - TCGv_i64 tcg_bit55 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + if (tbi !=3D 0) { + /* Sign-extend from bit 55. */ + tcg_gen_sextract_i64(cpu_pc, src, 0, 56); =20 - tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); + if (tbi !=3D 3) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); =20 - if (tbi =3D=3D 1) { - /* tbi0=3D=3D1, tbi1=3D=3D0, so 0-fill upper byte if bit 5= 5 =3D 0 */ - tcg_gen_andi_i64(tcg_tmpval, src, - 0x00FFFFFFFFFFFFFFull); - tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); - } else { - /* tbi0=3D=3D0, tbi1=3D=3D1, so 1-fill upper byte if bit 5= 5 =3D 1 */ - tcg_gen_ori_i64(tcg_tmpval, src, - 0xFF00000000000000ull); - tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_ze= ro, - tcg_tmpval, src); + /* + * The two TBI bits differ. + * If tbi0, then !tbi1: only use the extension if positive. + * if !tbi0, then tbi1: only use the extension if negative. + */ + tcg_gen_movcond_i64(tbi =3D=3D 1 ? TCG_COND_GE : TCG_COND_= LT, + cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); + tcg_temp_free_i64(tcg_zero); } - tcg_temp_free_i64(tcg_zero); - tcg_temp_free_i64(tcg_bit55); - tcg_temp_free_i64(tcg_tmpval); + return; } - } else { /* EL > 1 */ + } else { if (tbi !=3D 0) { /* Force tag byte to all zero */ - tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); - } else { - /* Load unmodified address */ - tcg_gen_mov_i64(cpu_pc, src); + tcg_gen_extract_i64(cpu_pc, src, 0, 56); + return; } } + + /* Load unmodified address */ + tcg_gen_mov_i64(cpu_pc, src); } =20 typedef struct DisasCompare64 { --=20 2.20.1