From nobody Thu Dec 18 22:26:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547825208949592.9539183001026; Fri, 18 Jan 2019 07:26:48 -0800 (PST) Received: from localhost ([127.0.0.1]:41430 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkW2h-0000uV-UA for importer@patchew.org; Fri, 18 Jan 2019 10:26:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVbc-0002tw-Bu for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkVbb-0007Wn-AN for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:48 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46684) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gkVbb-0007WL-4B for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:47 -0500 Received: by mail-wr1-x42d.google.com with SMTP id l9so15349398wrt.13 for ; Fri, 18 Jan 2019 06:58:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Q/iKc1b7Ptvw05FtPrBH1F4iiqkzdyUjBpBBa90oCZo=; b=J8AJmB3mLhXJDXzGm9r8BAHhcBTQW0DgIu9gq7GgdzezGH/lP1g/8Kp6X6Lw++PqpD X0xnZwF+OKfSp2PLA2ZTiWCahIEZln/S2REvCzkX9lyVPQPsDsxdpWVSN8YjMjhOinxC h7gpj2HVmtIAy5IRWB5E7CE4Ee+OB6K7JFtpo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q/iKc1b7Ptvw05FtPrBH1F4iiqkzdyUjBpBBa90oCZo=; b=awnjncJivO2lppz69bikTo9h2dohw0od2ZxIZPGbTMAblsctmDedVS4VcZ6b6V609r xXvZwbIZCKPwFOl8MTK5fQNFTr8+W3pMBgenaAIPgFon+BGSQIfqiWX3tHR0Txpk4l8A pYV/yt8kx+BYP9WJLr1PZ+tgLqbWMD1i/u5TzYfbCYcjZGsJeffL54Vqd8mSOYLgR+9l DHjIwxgfTryExzui90KjjchDcnf4XOMz0mZnTUS5mcKMQaljMDJGQBnVBcuUvTeXybPW +j0VbmrTkGdVdNmV4CSfNQ5KGUL0EcemO8T9hWgL7xW6ozwUEy24UL/fl3erDze7Weve SvhA== X-Gm-Message-State: AJcUukfC09FVYpMjWbvvF08C2T3Zg3UT25k2IYdTXF4TMHg+5CF/W0hC uqoKreQPcZp5C81Rzf3rOGFvA3fnC1WGEw== X-Google-Smtp-Source: ALg8bN5h83L+IJf/H44DaTlxNmtXQNwsO10FHm+uWR+7sxA+arfyGL1D44hqhHgSwmrcvH8VQ7AdpA== X-Received: by 2002:a5d:47d1:: with SMTP id l17mr16600155wrs.319.1547823525960; Fri, 18 Jan 2019 06:58:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:50 +0000 Message-Id: <20190118145805.6852-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d Subject: [Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190108223129.5570-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4c4e9e169ed..14bc24a35ae 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -162,6 +162,9 @@ static void arm_cpu_reset(CPUState *s) env->pstate =3D PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ env->cp15.sctlr_el[1] |=3D SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + /* Enable all PAC instructions */ + env->cp15.hcr_el2 |=3D HCR_API; + env->cp15.scr_el3 |=3D SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1974f1aeb74..d0de0d5dcfa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -285,6 +285,38 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v= , const char *name, error_propagate(errp, err); } =20 +#ifdef CONFIG_USER_ONLY +static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + const uint64_t *bit =3D opaque; + bool enabled =3D (cpu->env.cp15.sctlr_el[1] & *bit) !=3D 0; + + visit_type_bool(v, name, &enabled, errp); +} + +static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + Error *err =3D NULL; + const uint64_t *bit =3D opaque; + bool enabled; + + visit_type_bool(v, name, &enabled, errp); + + if (!err) { + if (enabled) { + cpu->env.cp15.sctlr_el[1] |=3D *bit; + } else { + cpu->env.cp15.sctlr_el[1] &=3D ~*bit; + } + } + error_propagate(errp, err); +} +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -360,6 +392,34 @@ static void aarch64_max_initfn(Object *obj) */ cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ + + /* + * Note that Linux will enable enable all of the keys at once. + * But doing it this way will allow experimentation beyond that. + */ + { + static const uint64_t apia_bit =3D SCTLR_EnIA; + static const uint64_t apib_bit =3D SCTLR_EnIB; + static const uint64_t apda_bit =3D SCTLR_EnDA; + static const uint64_t apdb_bit =3D SCTLR_EnDB; + + object_property_add(obj, "apia", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apia_bit, &error_fatal); + object_property_add(obj, "apib", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apib_bit, &error_fatal); + object_property_add(obj, "apda", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apda_bit, &error_fatal); + object_property_add(obj, "apdb", "bool", cpu_max_get_packey, + cpu_max_set_packey, NULL, + (void *)&apdb_bit, &error_fatal); + + /* Enable all PAC keys by default. */ + cpu->env.cp15.sctlr_el[1] |=3D SCTLR_EnIA | SCTLR_EnIB; + cpu->env.cp15.sctlr_el[1] |=3D SCTLR_EnDA | SCTLR_EnDB; + } #endif =20 cpu->sve_max_vq =3D ARM_MAX_VQ; --=20 2.20.1