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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qSXFJ1LzF5H0ldfMF/jTtGfhLTtl03OoFGWkZ82YmKY=; b=Myuz2LW8kdNzhnj/5fEV5tf/xSIc8xp/bHfTifGuiBXUlAETu3rJO+Opjhm1SzbGzm 3AKpHl9L7fq2sRd+u5s6v6Wnt6gle++yEJN2K5IXNqF7XXKVNkg5t34PV2tfSyoLghxY Ko5lpza/k+u92IKiQM5+LvAhmOoHNVTYTE9h4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qSXFJ1LzF5H0ldfMF/jTtGfhLTtl03OoFGWkZ82YmKY=; b=Ou5/0Lx8KhwoPNZylfWH+wHPkj7gi16SLw2fc3+V+7Hn1+OxSMXJtS05jnzrirxj/z lVuvnjDiwpy5WETuLL11LcPCwnRjPeu/FcKd8A3io/bK5sgrJAKinpIkeTr5Q8QeJTXX 15OBEJQoh2uMULQlIijkGCYmjgTRffF21MvQZMapctc9l2SfXm+aFiRTYRESzYIFozFL YzUnfjqmTRZ90Da65E0AetH4X02XK5WZkYvhXqKa5lee008AcC9++1Jit3lwrG6DTJ1P fC4+TixZgO1bb1oWEXXTTAueEfWFDe8OE4j3LyGpQk4q3l8+7EdxfviYs6cwnUeDbIiC Mmpg== X-Gm-Message-State: AJcUuke4gahIDZsKtjCtkpZKArz57lbjuHO5oBrFc5nPSFQAQ4XhDMFN 0wnSUyXobzFBSkPf7k7vgMEGS6Pj0mmdBw== X-Google-Smtp-Source: ALg8bN5KJpO+czekfYzYXTwdYuEXf4iZuJeaxcNAvwYHR8mJf+ZPlvJ4hgxDbrTaN0/ciqdDr3vaMA== X-Received: by 2002:adf:d243:: with SMTP id o3mr17466474wri.66.1547823518349; Fri, 18 Jan 2019 06:58:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:43 +0000 Message-Id: <20190118145805.6852-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 Subject: [Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190108223129.5570-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 35 ----------------------- target/arm/helper.c | 70 ++++++++++++++++----------------------------- 2 files changed, 24 insertions(+), 81 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea9b8ec4a1e..8512ca35528 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3015,41 +3015,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *e= nv) } #endif =20 -#ifndef CONFIG_USER_ONLY -/** - * arm_regime_tbi0: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI0 value from the appropriate TCR for the current EL - * - * Returns: the TBI0 value. - */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); - -/** - * arm_regime_tbi1: - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * - * Extracts the TBI1 value from the appropriate TCR for the current EL - * - * Returns: the TBI1 value. - */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); -#else -/* We can't handle tagged addresses properly in user-only mode */ -static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} - -static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return 0; -} -#endif - void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index d9b580e3316..a62ce2a76e6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8957,48 +8957,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mm= u_idx) return mmu_idx; } =20 -/* Returns TBI0 value for current regime el */ -uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return extract64(tcr->raw_tcr, 20, 1); - } else { - return extract64(tcr->raw_tcr, 37, 1); - } -} - -/* Returns TBI1 value for current regime el */ -uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - TCR *tcr; - uint32_t el; - - /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert - * a stage 1+2 mmu index into the appropriate stage 1 mmu index. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - tcr =3D regime_tcr(env, mmu_idx); - el =3D regime_el(env, mmu_idx); - - if (el > 1) { - return 0; - } else { - return extract64(tcr->raw_tcr, 38, 1); - } -} - /* Return the TTBR associated with this translation regime */ static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) @@ -13054,10 +13012,30 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - /* Get control bits for tagged addresses */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, - (arm_regime_tbi1(env, mmu_idx) << 1) | - arm_regime_tbi0(env, mmu_idx)); + +#ifndef CONFIG_USER_ONLY + /* + * Get control bits for tagged addresses. Note that the + * translator only uses this for instruction addresses. + */ + { + ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + int tbii, tbid; + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, st= age1); + tbid =3D (p1.tbi << 1) | p0.tbi; + tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid =3D p0.tbi; + tbii =3D tbid & !p0.tbid; + } + + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + } +#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.20.1