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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hkgVHKdZBGY72NDGSUIBQykiHWWRqxX4J+Ss1XL1D1Y=; b=HF7b9D9xNYJ6fVr6Ut8Ka9iKLQOePgP5XgVcwUzzmWHI/VfPbl8GX3xQRFkCRNoXhe AN9E/CkRaM8W8vTHvgaP7GYBA8Vgdwovj1/Xx0JIIiwHDle8o33vucyFErkN60G+1nQ4 ZYY/Tm+95MK0AYMmzutJmpHV0zC0su/9XZTtk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hkgVHKdZBGY72NDGSUIBQykiHWWRqxX4J+Ss1XL1D1Y=; b=UsR5lS4+HdoQuEXaKfLZd2UspEayiAiylKwlk3f4Ap/giP2SEV4hlaRJhWPH2MDUFI M5lXY8lkbQc4J2lOR8EyaeNH2SG+1dgBMdp9IXWXarqVZ4OqdIX4VHQmfjn7jUuAMi/P /SFtWNPBGMJh5Q0sjzD5EUm4M7ANwk+MsF2YUgv7mEin/foqPyewIeDXNLMBWy4VWwto oa6o107T4cR0BYO0S5ubrY7raVXqFUaeczuC9tGOXN/0Gk5IMlIzEcBhLtZsSWqavD3f jffWZQ+QX+KcT4jK0XN6yK9E4SfuAVWYRcdg/jGtIyY1x77VLFUuB41DKE6Q/hGu6CBl VZGg== X-Gm-Message-State: AJcUukfkLRhA/ZHxWzX+yQPyNYobuw6amwKFWD8/OY1A4WNM2MumMEns JeMgjbJodcPp4xkiqVUulYcERmI1ar6mIw== X-Google-Smtp-Source: ALg8bN6yZfqKNFXynJCsDxYUqZhabwbZiGgyzV4zM36s57osrB9pLg0UQyVwLstrMXGC4PkbGSxeQg== X-Received: by 2002:a1c:9a0d:: with SMTP id c13mr16454167wme.41.1547823514010; Fri, 18 Jan 2019 06:58:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:39 +0000 Message-Id: <20190118145805.6852-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190108223129.5570-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +-- target/arm/translate.h | 3 +-- target/arm/helper.c | 5 ++--- target/arm/translate-a64.c | 13 +++++++------ 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1d511f274c..ea9b8ec4a1e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2979,8 +2979,7 @@ FIELD(TBFLAG_A32, HANDLER, 21, 1) FIELD(TBFLAG_A32, STACKCHECK, 22, 1) =20 /* Bit usage when in AArch64 state */ -FIELD(TBFLAG_A64, TBI0, 0, 1) -FIELD(TBFLAG_A64, TBI1, 1, 1) +FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) diff --git a/target/arm/translate.h b/target/arm/translate.h index d8a8bb4e9c0..bb37d35741c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -26,8 +26,7 @@ typedef struct DisasContext { int user; #endif ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ - bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */ - bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */ + uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ diff --git a/target/arm/helper.c b/target/arm/helper.c index f09404e931f..97a24ed5908 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13041,10 +13041,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); /* Get control bits for tagged addresses */ - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI0, + flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, + (arm_regime_tbi1(env, mmu_idx) << 1) | arm_regime_tbi0(env, mmu_idx)); - flags =3D FIELD_DP32(flags, TBFLAG_A64, TBI1, - arm_regime_tbi1(env, mmu_idx)); =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8d8f0a60b38..f49fe1de3a8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -276,13 +276,15 @@ void gen_a64_set_pc_im(uint64_t val) */ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) { + /* Note that TBII is TBI1:TBI0. */ + int tbi =3D s->tbii; =20 if (s->current_el <=3D 1) { /* Test if NEITHER or BOTH TBI values are set. If so, no need to * examine bit 55 of address, can just generate code. * If mixed, then test via generated code */ - if (s->tbi0 && s->tbi1) { + if (tbi =3D=3D 3) { TCGv_i64 tmp_reg =3D tcg_temp_new_i64(); /* Both bits set, sign extension from bit 55 into [63:56] will * cover both cases @@ -290,7 +292,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) tcg_gen_shli_i64(tmp_reg, src, 8); tcg_gen_sari_i64(cpu_pc, tmp_reg, 8); tcg_temp_free_i64(tmp_reg); - } else if (!s->tbi0 && !s->tbi1) { + } else if (tbi =3D=3D 0) { /* Neither bit set, just load it as-is */ tcg_gen_mov_i64(cpu_pc, src); } else { @@ -300,7 +302,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) =20 tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55)); =20 - if (s->tbi0) { + if (tbi =3D=3D 1) { /* tbi0=3D=3D1, tbi1=3D=3D0, so 0-fill upper byte if bit 5= 5 =3D 0 */ tcg_gen_andi_i64(tcg_tmpval, src, 0x00FFFFFFFFFFFFFFull); @@ -318,7 +320,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) tcg_temp_free_i64(tcg_tmpval); } } else { /* EL > 1 */ - if (s->tbi0) { + if (tbi !=3D 0) { /* Force tag byte to all zero */ tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull); } else { @@ -13807,8 +13809,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->condexec_cond =3D 0; core_mmu_idx =3D FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); - dc->tbi0 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI0); - dc->tbi1 =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBI1); + dc->tbii =3D FIELD_EX32(tb_flags, TBFLAG_A64, TBII); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); --=20 2.20.1