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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vnvuXq27Z26C5kZa0C94arm1+44fOQdqCuiCn8RHNIU=; b=a6JvR4eeJANAawJ9Erz+lYIat/2/BQLypfU9JmCA4dVzPHnFDT8WvQH6RqrGh8nEGW TxdfG2yP/6yq3JwZb3PZ5LSlcoWMtDPSXVsmqTAOr5GOiJ3eROKTUXLRSXMm2B3w/S8g m8SVHXG57L2+UXF9yuH95yPGy6RbqEvPkZyto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vnvuXq27Z26C5kZa0C94arm1+44fOQdqCuiCn8RHNIU=; b=GHoIaOLbm4Gd1QVIahtL95VHLEelSwJL4+d6Vz6vF/x6zPz4dz9EXmd9SjhmQRvKlc hf57nKpZRq/O3+Fw0o7D4cRkPXHoOd/Zoq2OXH4EYwmPQpwva45w9Hjv1dnGAqxQ5iwk 5NQwc1kcZrGIKiEkNzzueP6TJpyGqMaLJJJjY6WLspBVxmweIaIY6C1K9q/fZU44mfaZ fBP4A0AFnAyAQY7LoIBY2OollbWETvnJmNylo0hsfpwUGLvavoDd5+eELhfBDNIJLH7X dee0btLQLrTt1tmaipM/o6W2dilZvn1vVOhHbMAOLbYlx96drzlJY6gdFablNk4Jsc6U UbDQ== X-Gm-Message-State: AJcUukf/gQSCKCpkvMsds8jDD/IvoDVvvbybYXy/5INpc8uvlCu2qhoD 2D0FZt0mrI7WSdmknImZZAjh3LJhiuvkKg== X-Google-Smtp-Source: ALg8bN7WqUoK9IRy0G6K+V4/NRtlBSOkKfJcBxtba/VOqQaH+94wCuTWc1UnezdenfLT4XAT7OcHnQ== X-Received: by 2002:adf:e284:: with SMTP id v4mr16305924wri.26.1547823508057; Fri, 18 Jan 2019 06:58:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 18 Jan 2019 14:57:34 +0000 Message-Id: <20190118145805.6852-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20190108223129.5570-15-richard.henderson@linaro.org [fixed trivial comment nit] Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 61 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fa50003f0b0..8d8f0a60b38 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3146,6 +3146,64 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, s->be_data | size | MO_ALIGN); } =20 +/* + * PAC memory operations + * + * 31 30 27 26 24 22 21 12 11 10 5 0 + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | + * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ + * + * Rt: the result register + * Rn: base address or SP + * V: vector flag (always 0 as of v8.3) + * M: clear for key DA, set for key DB + * W: pre-indexing flag + * S: sign for imm9. + */ +static void disas_ldst_pac(DisasContext *s, uint32_t insn, + int size, int rt, bool is_vector) +{ + int rn =3D extract32(insn, 5, 5); + bool is_wback =3D extract32(insn, 11, 1); + bool use_key_a =3D !extract32(insn, 23, 1); + int offset; + TCGv_i64 tcg_addr, tcg_rt; + + if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { + unallocated_encoding(s); + return; + } + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_addr =3D read_cpu_reg_sp(s, rn, 1); + + if (s->pauth_active) { + if (use_key_a) { + gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } else { + gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); + } + } + + /* Form the 10-bit signed, scaled offset. */ + offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); + offset =3D sextract32(offset << size, 0, 10 + size); + tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); + + tcg_rt =3D cpu_reg(s, rt); + + do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, + /* extend */ false, /* iss_valid */ !is_wback, + /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + + if (is_wback) { + tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3171,6 +3229,9 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) case 2: disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); return; + default: + disas_ldst_pac(s, insn, size, rt, is_vector); + return; } break; case 1: --=20 2.20.1