From nobody Fri Nov 7 10:27:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547711759091544.5850820157299; Wed, 16 Jan 2019 23:55:59 -0800 (PST) Received: from localhost ([127.0.0.1]:38156 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gk2Wr-0003Yk-42 for importer@patchew.org; Thu, 17 Jan 2019 02:55:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:47977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gk2Ur-0002EZ-E4 for qemu-devel@nongnu.org; Thu, 17 Jan 2019 02:53:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gk2Un-0005Vw-0D for qemu-devel@nongnu.org; Thu, 17 Jan 2019 02:53:51 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:55532 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gk2Uj-0005P3-Rx for qemu-devel@nongnu.org; Thu, 17 Jan 2019 02:53:47 -0500 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x0H7rcO8049035 for ; Thu, 17 Jan 2019 02:53:40 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q2mjxtn5a-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 17 Jan 2019 02:53:40 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 17 Jan 2019 07:53:33 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0H7rW0u5308780 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 17 Jan 2019 07:53:32 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 87511A405F; Thu, 17 Jan 2019 07:53:32 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6D3BAA405C; Thu, 17 Jan 2019 07:53:32 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 17 Jan 2019 07:53:32 +0000 (GMT) Received: from zorba.kaod.org.com (sig-9-145-26-141.uk.ibm.com [9.145.26.141]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id C79FD220211; Thu, 17 Jan 2019 08:53:31 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Date: Thu, 17 Jan 2019 08:53:24 +0100 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190117075327.22194-1-clg@kaod.org> References: <20190117075327.22194-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19011707-0020-0000-0000-000003079B45 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19011707-0021-0000-0000-00002158BB28 Message-Id: <20190117075327.22194-2-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-17_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=846 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901170059 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0b-001b2d01.pphosted.com id x0H7rcO8049035 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 1/4] xive: add a get_tctx() method to the XiveRouter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , qemu-ppc@nongnu.org, Greg Kurz , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" It provides a mean to retrieve the XiveTCTX of a CPU. This will become necessary with future changes which move the interrupt presenter object pointers under the PowerPCCPU machine_data. The PowerNV machine has an extra requirement on TIMA accesses that this new method addresses. The machine can perform indirect loads and stores on the TIMA on behalf of another CPU. The PIR being defined in the controller registers, we need a way to peek in the controller model to find the PIR value. The XiveTCTX is moved above the XiveRouter definition to avoid forward typedef declarations. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- include/hw/ppc/xive.h | 57 ++++++++++++++++++++++--------------------- hw/intc/spapr_xive.c | 8 ++++++ hw/intc/xive.c | 16 +++++++----- 3 files changed, 47 insertions(+), 34 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 5d31c801ee53..ec3bb2aae45a 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -294,6 +294,33 @@ static inline void xive_source_irq_set(XiveSource *xsr= c, uint32_t srcno, =20 void xive_source_set_irq(void *opaque, int srcno, int val); =20 +/* + * XIVE Thread interrupt Management (TM) context + */ + +#define TYPE_XIVE_TCTX "xive-tctx" +#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) + +/* + * XIVE Thread interrupt Management register rings : + * + * QW-0 User event-based exception state + * QW-1 O/S OS context for priority management, interrupt acks + * QW-2 Pool hypervisor pool context for virtual processors dispa= tched + * QW-3 Physical physical thread context and security context + */ +#define XIVE_TM_RING_COUNT 4 +#define XIVE_TM_RING_SIZE 0x10 + +typedef struct XiveTCTX { + DeviceState parent_obj; + + CPUState *cs; + qemu_irq output; + + uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; +} XiveTCTX; + /* * XIVE Router */ @@ -324,6 +351,7 @@ typedef struct XiveRouterClass { XiveNVT *nvt); int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); } XiveRouterClass; =20 void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); @@ -338,7 +366,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_b= lk, uint32_t nvt_idx, XiveNVT *nvt); int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_= idx, XiveNVT *nvt, uint8_t word_number); - +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); =20 /* * XIVE END ESBs @@ -371,33 +399,6 @@ typedef struct XiveENDSource { void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon); void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *= mon); =20 -/* - * XIVE Thread interrupt Management (TM) context - */ - -#define TYPE_XIVE_TCTX "xive-tctx" -#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX) - -/* - * XIVE Thread interrupt Management register rings : - * - * QW-0 User event-based exception state - * QW-1 O/S OS context for priority management, interrupt acks - * QW-2 Pool hypervisor pool context for virtual processors dispa= tched - * QW-3 Physical physical thread context and security context - */ -#define XIVE_TM_RING_COUNT 4 -#define XIVE_TM_RING_SIZE 0x10 - -typedef struct XiveTCTX { - DeviceState parent_obj; - - CPUState *cs; - qemu_irq output; - - uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; -} XiveTCTX; - /* * XIVE Thread Interrupt Management Aera (TIMA) * diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index d391177ab81f..136d872f16bc 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -390,6 +390,13 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint= 8_t nvt_blk, g_assert_not_reached(); } =20 +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + return cpu->tctx; +} + static const VMStateDescription vmstate_spapr_xive_end =3D { .name =3D TYPE_SPAPR_XIVE "/end", .version_id =3D 1, @@ -454,6 +461,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) xrc->write_end =3D spapr_xive_write_end; xrc->get_nvt =3D spapr_xive_get_nvt; xrc->write_nvt =3D spapr_xive_write_nvt; + xrc->get_tctx =3D spapr_xive_get_tctx; } =20 static const TypeInfo spapr_xive_info =3D { diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 7f567a57d25a..2e9b8efd4342 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -320,8 +320,7 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, u= nsigned size, bool write) static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); const XiveTmOp *xto; =20 /* @@ -359,8 +358,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, =20 static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { - PowerPCCPU *cpu =3D POWERPC_CPU(current_cpu); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current_c= pu); const XiveTmOp *xto; =20 /* @@ -1107,6 +1105,13 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t = nvt_blk, uint32_t nvt_idx, return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); } =20 +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) +{ + XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->get_tctx(xrtr, cs); +} + /* * The thread context register words are in big-endian format. */ @@ -1182,8 +1187,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, ui= nt8_t format, */ =20 CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - XiveTCTX *tctx =3D cpu->tctx; + XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); int ring; =20 /* --=20 2.20.1