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X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v2 4/7] softfloat: fallback to __int128 maths for s390x and others X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , cohuck@redhat.com, "open list:S390" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Apparently some versions of clang can't handle inline assembly with __int128 parameters, especially on s390. Instead of hand-coding the s390 divide provide a generic fallback for anything that provides __int128 capable maths. Signed-off-by: Alex Benn=C3=A9e Cc: Thomas Huth --- include/fpu/softfloat-macros.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index b1d772e6d4..1a43609eef 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -641,12 +641,6 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_= t n1, uint64_t q; asm("divq %4" : "=3Da"(q), "=3Dd"(*r) : "0"(n0), "1"(n1), "rm"(d)); return q; -#elif defined(__s390x__) - /* Need to use a TImode type to get an even register pair for DLGR. */ - unsigned __int128 n =3D (unsigned __int128)n1 << 64 | n0; - asm("dlgr %0, %1" : "+r"(n) : "r"(d)); - *r =3D n >> 64; - return n; #elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7) /* From Power ISA 2.06, programming note for divdeu. */ uint64_t q1, q2, Q, r1, r2, R; @@ -663,6 +657,10 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_= t n1, } *r =3D R; return Q; +#elif defined(CONFIG_INT128) + unsigned __int128 n =3D (unsigned __int128)n1 << 64 | n0; + *r =3D n % d; + return n / d; #else uint64_t d0, d1, q0, q1, r1, r0, m; =20 --=20 2.17.1