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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 125sm47835842wmm.26.2019.01.14.03.56.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Jan 2019 03:56:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kBvSXrDaVNbHgyLrktW8tQ0AJ0MM4jIMZHDOYQRgy5w=; b=eDzbeB6JKcos+axA+8vYHVV+EpMCB7bksyYAQsEGYe/PewNzDGdlTZidxoT1ezC+Kr SEFoMgDjUecJjdkst2dBSuWgfNhEla4nQzOuvNE/kyksxOKB4iOPleRmXpfAnBfXMnfz 8dzq2ohI/MbggbWpbRsfFNFcMo14uRu0xZkOE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kBvSXrDaVNbHgyLrktW8tQ0AJ0MM4jIMZHDOYQRgy5w=; b=HMSd+63m72RLG8FnGhMsjoJgkxafqmMdxR5u9xAOeMNzHL0ZIUCLolYhAOQrDXUBlW t9ZOF+eOGD1OVtD5C9/4SNOj98ygVrfojV6Rffb/TQbcBXTWHckiMQYfwbGXaM+w/Y0a GTrWZipS/uKC5Qc8fvs0yoD/Jn2ERnlZJzJrCfFYuX38TT3R3M+xhfO4IRSqYTeN5Q1X wxaqOVlm+Pp/rGicNhouBz/r9GcKejP9CxWfK2Gkrz0njAnv5o6Hj+KqEyR52CQU6ZMW hFcEcsFm5ieMfAFe3sgWvuYbSwfHBOgafm3pBYLkIFlwNdPi/eLrGPNlpKZ1Bqt4Uc29 w57g== X-Gm-Message-State: AJcUukcWbGMM/w6CkyL0/PxkcK66QdglvWJDbp9sHJ2rWoGQh+53WbO/ XYtVeqBRmBhSVHsYBkbsyQZZuGOiPehTmg== X-Google-Smtp-Source: ALg8bN6MV4mWJH5gNLMluZjEB6R1sReWgDVA2/BWb1rp8PQUFbh0N7TPtRwh1Hnic0T3PyS4QR6+Yg== X-Received: by 2002:adf:f149:: with SMTP id y9mr25684348wro.284.1547467003494; Mon, 14 Jan 2019 03:56:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 11:56:35 +0000 Message-Id: <20190114115637.6335-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190114115637.6335-1-peter.maydell@linaro.org> References: <20190114115637.6335-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v2 2/4] qom/cpu: Add cluster_index to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Peter Crosthwaite , Alistair Francis , Richard Henderson , "Emilio G . Cota" , "Edgar E. Iglesias" , Paolo Bonzini , Aleksandar Markovic Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel --- include/hw/cpu/cluster.h | 19 +++++++++++++++++++ include/qom/cpu.h | 7 +++++++ hw/cpu/cluster.c | 33 +++++++++++++++++++++++++++++++++ qom/cpu.c | 1 + 4 files changed, 60 insertions(+) diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 73818232437..d1bef315d10 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -34,12 +34,31 @@ * Arm big.LITTLE system) they should be in different clusters. If the CPU= s do * not have the same view of memory (for example the main CPU and a manage= ment * controller processor) they should be in different clusters. + * + * A cluster is created by creating an object of TYPE_CPU_CLUSTER, and then + * adding the CPUs to it as QOM child objects (e.g. using the + * object_initialize_child() or object_property_add_child() functions). + * All CPUs must be added as children before the cluster is realized. + * (Regrettably QOM provides no way to prevent adding children to a realiz= ed + * object and no way for the parent to be notified when a new child is add= ed + * to it, so this restriction is not checked for, but the system will not + * behave correctly if it is not adhered to.) + * + * A CPU which is not put into any cluster will be considered implicitly + * to be in a cluster with all the other "loose" CPUs, so all CPUs that are + * not assigned to clusters must be identical. */ =20 #define TYPE_CPU_CLUSTER "cpu-cluster" #define CPU_CLUSTER(obj) \ OBJECT_CHECK(CPUClusterState, (obj), TYPE_CPU_CLUSTER) =20 +/* + * This limit is imposed by TCG, which puts the cluster ID into an + * 8 bit field (and uses all-1s for the default "not in any cluster"). + */ +#define MAX_CLUSTERS 255 + /** * CPUClusterState: * @cluster_id: The cluster ID. This value is for internal use only and sh= ould diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 1396f53e5b5..844becbcedc 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -279,6 +279,11 @@ struct qemu_work_item; /** * CPUState: * @cpu_index: CPU index (informative). + * @cluster_index: Identifies which cluster this CPU is in. + * For boards which don't define clusters or for "loose" CPUs not assign= ed + * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will + * be the same as the cluster-id property of the CPU object's TYPE_CPU_C= LUSTER + * QOM parent. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -404,6 +409,7 @@ struct CPUState { =20 /* TODO Move common fields from CPUArchState here. */ int cpu_index; + int cluster_index; uint32_t halted; uint32_t can_do_io; int32_t exception_index; @@ -1109,5 +1115,6 @@ extern const struct VMStateDescription vmstate_cpu_co= mmon; #endif /* NEED_CPU_H */ =20 #define UNASSIGNED_CPU_INDEX -1 +#define UNASSIGNED_CLUSTER_INDEX -1 =20 #endif diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 9d50a235d5c..d672f54a620 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -20,19 +20,52 @@ =20 #include "qemu/osdep.h" #include "hw/cpu/cluster.h" +#include "qom/cpu.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" =20 static Property cpu_cluster_properties[] =3D { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), DEFINE_PROP_END_OF_LIST() }; =20 +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + /* Iterate through all our CPU children and set their cluster_index */ + CPUClusterState *cluster =3D CPU_CLUSTER(dev); + ObjectPropertyIterator iter; + ObjectProperty *prop; + Object *cluster_obj =3D OBJECT(dev); + + if (cluster->cluster_id >=3D MAX_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + return; + } + + object_property_iter_init(&iter, cluster_obj); + while ((prop =3D object_property_iter_next(&iter))) { + Object *cpu_obj; + CPUState *cpu; + + if (!strstart(prop->type, "child<", NULL)) { + continue; + } + cpu_obj =3D object_property_get_link(cluster_obj, prop->name, NULL= ); + cpu =3D (CPUState *)object_dynamic_cast(cpu_obj, TYPE_CPU); + if (!cpu) { + continue; + } + cpu->cluster_index =3D cluster->cluster_id; + } +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->props =3D cpu_cluster_properties; + dc->realize =3D cpu_cluster_realize; } =20 static const TypeInfo cpu_cluster_type_info =3D { diff --git a/qom/cpu.c b/qom/cpu.c index 5442a7323be..f5579b1cd50 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -364,6 +364,7 @@ static void cpu_common_initfn(Object *obj) CPUClass *cc =3D CPU_GET_CLASS(obj); =20 cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; + cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; /* *-user doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for softmmu */ --=20 2.20.1