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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ydqil1w8iCE5YBsDMBM3q0kPbxIVe6yKVnFnE2WocKs=; b=h+9QZQeaiBhJ32tXFLzsb4p4jvlYNir+c4cvylHyvfeK4p0G1MYoy07ZpnRChgG42F qxiwLa3kBpsbVMf4CqrmyFn5FzgMc/WY6AKPdMfB8QxIAck7Xnjv9t+KcmxwHd3WPxJS nxz6Ha0But+a3OQLyECwPhuoSCvShAQQokrA9nXczKid2DP+SNZd8tCpOxVrMnA5a/kQ +1/l0FqLiStHJBR9JrQw2MeE1wHGPMACxb1MXUDFtzgJl27B1L1T68tZ3RaP6kwhyhwY 2nFMXVRS4e3IjjYXRaCbdNQTHJNzapNyt2oNUUvRHTCLV1HMMwmwNIxIDVPbjbkd6nw7 FpLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ydqil1w8iCE5YBsDMBM3q0kPbxIVe6yKVnFnE2WocKs=; b=izreNddOfdkLrdo3CQEY/Zi0ty0b6p5NOeZAlhf4ewVHk1FRyV6qtF/BxUlobpwmbC tUACUMLP6sKSpEUoi8w5Ol1/qsV6CWgNOIk3pzFTe1pLJ0BhIdIlc0FeMoYDZKISn+zp Y04xPOazGCO8BspjnMArkrg0EMbo1D/I9Ex6J9wgHzLIDIUv+FmtdSOvoWpwENziNO2i Gaky7/EQQrYa89ZkFb5HU600FkBccJ3odWVGwNas/sdiZCgMjBRpK4Mmsup6bpSosd3j WD+S03wpaSjMnrYXcrIqanctS3ZsWjWE34ozv3t8+ShyU2bg6MuXE0IBAzhU20gv6GCr uR/Q== X-Gm-Message-State: AJcUukd0Rd8M65G6U1pnT0q4PsCZr0JGX8rCbjMUMNio9MJ2Xr4v0TVy qID4dE/ONKJfQnCygjXgcIJGgsQC9zY= X-Google-Smtp-Source: ALg8bN4yNxzFAy0vcWWHexCAToPZ/Sx9KFuqySQG+/L0ZMhkcRwax1WLSNqi68SPbGrYJMi0y597NA== X-Received: by 2002:a2e:974a:: with SMTP id f10-v6mr15110638ljj.61.1547452173371; Sun, 13 Jan 2019 23:49:33 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:55 -0800 Message-Id: <20190114074855.16891-8-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH 7/7] target/xtensa: move non-HELPER functions to helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move remaining non-HELPER functions from op_helper.c to helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/helper.c | 61 +++++++++++++++++++++++++++++++++++++++++++= +--- target/xtensa/op_helper.c | 56 ------------------------------------------- 2 files changed, 58 insertions(+), 59 deletions(-) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2f1dec5c63e9..323c47a7fb54 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,10 +29,8 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "exec/helper-proto.h" #include "qemu/host-utils.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif =20 static struct XtensaConfigList *xtensa_cores; =20 @@ -188,6 +186,63 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, =20 #else =20 +void xtensa_cpu_do_unaligned_access(CPUState *cs, + vaddr addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTI= ON) && + !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { + cpu_restore_state(CPU(cpu), retaddr, true); + HELPER(exception_cause_vaddr)(env, + env->pc, LOAD_STORE_ALIGNMENT_CAUSE, + addr); + } +} + +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + uint32_t paddr; + uint32_t page_size; + unsigned access; + int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, + &paddr, &page_size, &access); + + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", + __func__, vaddr, access_type, mmu_idx, paddr, ret); + + if (ret =3D=3D 0) { + tlb_set_page(cs, + vaddr & TARGET_PAGE_MASK, + paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); + } else { + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); + } +} + +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, + unsigned size, MMUAccessType access_= type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t reta= ddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, + access_type =3D=3D MMU_INST_FETCH ? + INSTR_PIF_ADDR_ERROR_CAUSE : + LOAD_STORE_PIF_ADDR_ERROR_CAUSE, + addr); +} + void xtensa_runstall(CPUXtensaState *env, bool runstall) { CPUState *cpu =3D CPU(xtensa_env_get_cpu(env)); diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index b0ef828f9ae5..1865f46c4b5f 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -37,62 +37,6 @@ =20 #ifndef CONFIG_USER_ONLY =20 -void xtensa_cpu_do_unaligned_access(CPUState *cs, - vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTI= ON) && - !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT= )) { - cpu_restore_state(CPU(cpu), retaddr, true); - HELPER(exception_cause_vaddr)(env, - env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); - } -} - -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, - &paddr, &page_size, &access); - - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); - - if (ret =3D=3D 0) { - tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); - } else { - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); - } -} - -void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, - unsigned size, MMUAccessType access_= type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t reta= ddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, - access_type =3D=3D MMU_INST_FETCH ? - INSTR_PIF_ADDR_ERROR_CAUSE : - LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - addr); -} - void HELPER(update_ccount)(CPUXtensaState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); --=20 2.11.0