From nobody Mon Feb 9 00:01:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547452551402786.7015823035767; Sun, 13 Jan 2019 23:55:51 -0800 (PST) Received: from localhost ([127.0.0.1]:55481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix5s-0001yn-E2 for importer@patchew.org; Mon, 14 Jan 2019 02:55:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix0A-0006Vw-R9 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gix08-00022T-Cn for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:42 -0500 Received: from mail-lf1-x143.google.com ([2a00:1450:4864:20::143]:34660) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gix08-0001ud-07 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:40 -0500 Received: by mail-lf1-x143.google.com with SMTP id p6so14897736lfc.1 for ; Sun, 13 Jan 2019 23:49:31 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net. (jcmvbkbc-1-pt.tunnel.tserv24.sto1.ipv6.he.net. [2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hDd7+1WVhHSP3atBUucRfi7XjQcHIYxNX+PrYAJ7u/s=; b=SMlyTYVrQIvHpQ6oZwRHZ9Rbhx6LzC2MEUVjTjIME2fRbuDdGFlx/TG0g1y4/6r1LD PRcoL78E8R6Fe6Sf1yljMMxgtFgYzs6uVCrS0x1oqrroLO9W3uW4cO6boIxb7aukdR5U FprV0QEt7qmJUgd9L6eVtrVF2hcpKgDyYhjb+1NZOxySILStqWlKTHUS/kAtuSK7LsJJ 6y3KduMdid2cepTvIsZ5+UW9GaMde8dGDV28kvSJyni6MvGlvPoRS3VzGBVFO39W+ax6 CEL2OD9vaGQSuHl71IjitYKHHU9xVoFZsRQEDDiDvLbymDbpJiCShIjgOwudFuOXzvMY rx+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hDd7+1WVhHSP3atBUucRfi7XjQcHIYxNX+PrYAJ7u/s=; b=jyl6PQIjfN6S1bn1Lo5pPAeSeQMTHUsNNxL4OYyoJnaGzrxYs36WeUIwYJlcggdP3N s15ldzednSucAg59RpOyhk9a62T9FEsfpMUGwLtNUqaCspl9Aam2iuc/rKNpBE5+SbPy 9JrZ4t1t4iIkR09geeNgh0+INrvp1O1wY6wd9BVa9aY1yvcXtv07PpcMX/fRasFfjA0V St4bAQIYd+EJ68yb4pa1NvlSfBQoQB/3M069VcALxpvIWeib0W4qB7RO52kSFhtBc1OQ pUGK423xJ1h5kapKlAeV41DBtF4O85tWG9VYQMVCfBJ01XgOCu0vfyJS6m7ceM7zM3n1 rT2Q== X-Gm-Message-State: AJcUukeBcb86PN86DsLynPYDrA3Cmy4WQnJeL3/P4m1n4hpBm+zJ2fYK xjiGQDrWjx9GKOz5p1dy/FfHbeU9aT4= X-Google-Smtp-Source: ALg8bN7mvJ4buqIjND6qA86mcMo9NVkwD/PYmuF3TIXDqxIIFQCoANfrnbSPjcNP/IZI+rSdZWBOFw== X-Received: by 2002:a19:1994:: with SMTP id 142mr13361856lfz.134.1547452169223; Sun, 13 Jan 2019 23:49:29 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:53 -0800 Message-Id: <20190114074855.16891-6-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 Subject: [Qemu-devel] [PATCH 5/7] target/xtensa: extract interrupt and exception helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/exc_helper.c | 258 ++++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/helper.c | 127 ---------------------- target/xtensa/op_helper.c | 93 ---------------- 4 files changed, 259 insertions(+), 220 deletions(-) create mode 100644 target/xtensa/exc_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index cfd33ba1d951..808f7e3fceb8 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SOFTMMU) +=3D monitor.o xtensa-semi.o obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-$(CONFIG_SOFTMMU) +=3D dbg_helper.o +obj-y +=3D exc_helper.o obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o obj-$(CONFIG_SOFTMMU) +=3D mmu_helper.o diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c new file mode 100644 index 000000000000..371a32ba5ad9 --- /dev/null +++ b/target/xtensa/exc_helper.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" + +void HELPER(exception)(CPUXtensaState *env, uint32_t excp) +{ + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + + cs->exception_index =3D excp; + if (excp =3D=3D EXCP_YIELD) { + env->yield_needed =3D 0; + } + if (excp =3D=3D EXCP_DEBUG) { + env->exception_taken =3D 0; + } + cpu_loop_exit(cs); +} + +void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) +{ + uint32_t vector; + + env->pc =3D pc; + if (env->sregs[PS] & PS_EXCM) { + if (env->config->ndepc) { + env->sregs[DEPC] =3D pc; + } else { + env->sregs[EPC1] =3D pc; + } + vector =3D EXC_DOUBLE; + } else { + env->sregs[EPC1] =3D pc; + vector =3D (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; + } + + env->sregs[EXCCAUSE] =3D cause; + env->sregs[PS] |=3D PS_EXCM; + + HELPER(exception)(env, vector); +} + +void HELPER(exception_cause_vaddr)(CPUXtensaState *env, + uint32_t pc, uint32_t cause, uint32_t v= addr) +{ + env->sregs[EXCVADDR] =3D vaddr; + HELPER(exception_cause)(env, pc, cause); +} + +void debug_exception_env(CPUXtensaState *env, uint32_t cause) +{ + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + HELPER(debug_exception)(env, env->pc, cause); + } +} + +void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) +{ + unsigned level =3D env->config->debug_level; + + env->pc =3D pc; + env->sregs[DEBUGCAUSE] =3D cause; + env->sregs[EPC1 + level - 1] =3D pc; + env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; + env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | + (level << PS_INTLEVEL_SHIFT); + HELPER(exception)(env, EXC_DEBUG); +} + +#ifndef CONFIG_USER_ONLY + +void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) +{ + CPUState *cpu; + + env->pc =3D pc; + env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | + (intlevel << PS_INTLEVEL_SHIFT); + + qemu_mutex_lock_iothread(); + check_interrupts(env); + qemu_mutex_unlock_iothread(); + + if (env->pending_irq_level) { + cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); + return; + } + + cpu =3D CPU(xtensa_env_get_cpu(env)); + cpu->halted =3D 1; + HELPER(exception)(env, EXCP_HLT); +} + +void HELPER(check_interrupts)(CPUXtensaState *env) +{ + qemu_mutex_lock_iothread(); + check_interrupts(env); + qemu_mutex_unlock_iothread(); +} + +static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) +{ + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_RELOCATABLE_VECTOR)) { + return vector - env->config->vecbase + env->sregs[VECBASE]; + } else { + return vector; + } +} + +/*! + * Handle penging IRQ. + * For the high priority interrupt jump to the corresponding interrupt vec= tor. + * For the level-1 interrupt convert it to either user, kernel or double + * exception with the 'level-1 interrupt' exception cause. + */ +static void handle_interrupt(CPUXtensaState *env) +{ + int level =3D env->pending_irq_level; + + if (level > xtensa_get_cintlevel(env) && + level <=3D env->config->nlevel && + (env->config->level_mask[level] & + env->sregs[INTSET] & + env->sregs[INTENABLE])) { + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + + if (level > 1) { + env->sregs[EPC1 + level - 1] =3D env->pc; + env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; + env->sregs[PS] =3D + (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; + env->pc =3D relocated_vector(env, + env->config->interrupt_vector[level= ]); + } else { + env->sregs[EXCCAUSE] =3D LEVEL1_INTERRUPT_CAUSE; + + if (env->sregs[PS] & PS_EXCM) { + if (env->config->ndepc) { + env->sregs[DEPC] =3D env->pc; + } else { + env->sregs[EPC1] =3D env->pc; + } + cs->exception_index =3D EXC_DOUBLE; + } else { + env->sregs[EPC1] =3D env->pc; + cs->exception_index =3D + (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; + } + env->sregs[PS] |=3D PS_EXCM; + } + env->exception_taken =3D 1; + } +} + +/* Called from cpu_handle_interrupt with BQL held */ +void xtensa_cpu_do_interrupt(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + if (cs->exception_index =3D=3D EXC_IRQ) { + qemu_log_mask(CPU_LOG_INT, + "%s(EXC_IRQ) level =3D %d, cintlevel =3D %d, " + "pc =3D %08x, a0 =3D %08x, ps =3D %08x, " + "intset =3D %08x, intenable =3D %08x, " + "ccount =3D %08x\n", + __func__, env->pending_irq_level, + xtensa_get_cintlevel(env), + env->pc, env->regs[0], env->sregs[PS], + env->sregs[INTSET], env->sregs[INTENABLE], + env->sregs[CCOUNT]); + handle_interrupt(env); + } + + switch (cs->exception_index) { + case EXC_WINDOW_OVERFLOW4: + case EXC_WINDOW_UNDERFLOW4: + case EXC_WINDOW_OVERFLOW8: + case EXC_WINDOW_UNDERFLOW8: + case EXC_WINDOW_OVERFLOW12: + case EXC_WINDOW_UNDERFLOW12: + case EXC_KERNEL: + case EXC_USER: + case EXC_DOUBLE: + case EXC_DEBUG: + qemu_log_mask(CPU_LOG_INT, "%s(%d) " + "pc =3D %08x, a0 =3D %08x, ps =3D %08x, ccount =3D %= 08x\n", + __func__, cs->exception_index, + env->pc, env->regs[0], env->sregs[PS], + env->sregs[CCOUNT]); + if (env->config->exception_vector[cs->exception_index]) { + uint32_t vector; + + vector =3D env->config->exception_vector[cs->exception_index]; + env->pc =3D relocated_vector(env, vector); + env->exception_taken =3D 1; + } else { + qemu_log_mask(CPU_LOG_INT, + "%s(pc =3D %08x) bad exception_index: %d\n", + __func__, env->pc, cs->exception_index); + } + break; + + case EXC_IRQ: + break; + + default: + qemu_log("%s(pc =3D %08x) unknown exception_index: %d\n", + __func__, env->pc, cs->exception_index); + break; + } + check_interrupts(env); +} +#else +void xtensa_cpu_do_interrupt(CPUState *cs) +{ +} +#endif + +bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + cs->exception_index =3D EXC_IRQ; + xtensa_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index c344241bd06e..2f1dec5c63e9 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -169,133 +169,6 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fp= rintf) } } =20 -#ifndef CONFIG_USER_ONLY - -static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) -{ - if (xtensa_option_enabled(env->config, - XTENSA_OPTION_RELOCATABLE_VECTOR)) { - return vector - env->config->vecbase + env->sregs[VECBASE]; - } else { - return vector; - } -} - -/*! - * Handle penging IRQ. - * For the high priority interrupt jump to the corresponding interrupt vec= tor. - * For the level-1 interrupt convert it to either user, kernel or double - * exception with the 'level-1 interrupt' exception cause. - */ -static void handle_interrupt(CPUXtensaState *env) -{ - int level =3D env->pending_irq_level; - - if (level > xtensa_get_cintlevel(env) && - level <=3D env->config->nlevel && - (env->config->level_mask[level] & - env->sregs[INTSET] & - env->sregs[INTENABLE])) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - - if (level > 1) { - env->sregs[EPC1 + level - 1] =3D env->pc; - env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; - env->sregs[PS] =3D - (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; - env->pc =3D relocated_vector(env, - env->config->interrupt_vector[level]); - } else { - env->sregs[EXCCAUSE] =3D LEVEL1_INTERRUPT_CAUSE; - - if (env->sregs[PS] & PS_EXCM) { - if (env->config->ndepc) { - env->sregs[DEPC] =3D env->pc; - } else { - env->sregs[EPC1] =3D env->pc; - } - cs->exception_index =3D EXC_DOUBLE; - } else { - env->sregs[EPC1] =3D env->pc; - cs->exception_index =3D - (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; - } - env->sregs[PS] |=3D PS_EXCM; - } - env->exception_taken =3D 1; - } -} - -/* Called from cpu_handle_interrupt with BQL held */ -void xtensa_cpu_do_interrupt(CPUState *cs) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - if (cs->exception_index =3D=3D EXC_IRQ) { - qemu_log_mask(CPU_LOG_INT, - "%s(EXC_IRQ) level =3D %d, cintlevel =3D %d, " - "pc =3D %08x, a0 =3D %08x, ps =3D %08x, " - "intset =3D %08x, intenable =3D %08x, " - "ccount =3D %08x\n", - __func__, env->pending_irq_level, xtensa_get_cintlevel(env= ), - env->pc, env->regs[0], env->sregs[PS], - env->sregs[INTSET], env->sregs[INTENABLE], - env->sregs[CCOUNT]); - handle_interrupt(env); - } - - switch (cs->exception_index) { - case EXC_WINDOW_OVERFLOW4: - case EXC_WINDOW_UNDERFLOW4: - case EXC_WINDOW_OVERFLOW8: - case EXC_WINDOW_UNDERFLOW8: - case EXC_WINDOW_OVERFLOW12: - case EXC_WINDOW_UNDERFLOW12: - case EXC_KERNEL: - case EXC_USER: - case EXC_DOUBLE: - case EXC_DEBUG: - qemu_log_mask(CPU_LOG_INT, "%s(%d) " - "pc =3D %08x, a0 =3D %08x, ps =3D %08x, ccount =3D %08x\n", - __func__, cs->exception_index, - env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); - if (env->config->exception_vector[cs->exception_index]) { - env->pc =3D relocated_vector(env, - env->config->exception_vector[cs->exception_index]); - env->exception_taken =3D 1; - } else { - qemu_log_mask(CPU_LOG_INT, "%s(pc =3D %08x) bad exception_inde= x: %d\n", - __func__, env->pc, cs->exception_index); - } - break; - - case EXC_IRQ: - break; - - default: - qemu_log("%s(pc =3D %08x) unknown exception_index: %d\n", - __func__, env->pc, cs->exception_index); - break; - } - check_interrupts(env); -} -#else -void xtensa_cpu_do_interrupt(CPUState *cs) -{ -} -#endif - -bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - cs->exception_index =3D EXC_IRQ; - xtensa_cpu_do_interrupt(cs); - return true; - } - return false; -} - #ifdef CONFIG_USER_ONLY =20 int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index e13e686479db..d3e61e22fe82 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -95,70 +95,6 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, vaddr addr, =20 #endif =20 -void HELPER(exception)(CPUXtensaState *env, uint32_t excp) -{ - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - - cs->exception_index =3D excp; - if (excp =3D=3D EXCP_YIELD) { - env->yield_needed =3D 0; - } - if (excp =3D=3D EXCP_DEBUG) { - env->exception_taken =3D 0; - } - cpu_loop_exit(cs); -} - -void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) -{ - uint32_t vector; - - env->pc =3D pc; - if (env->sregs[PS] & PS_EXCM) { - if (env->config->ndepc) { - env->sregs[DEPC] =3D pc; - } else { - env->sregs[EPC1] =3D pc; - } - vector =3D EXC_DOUBLE; - } else { - env->sregs[EPC1] =3D pc; - vector =3D (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; - } - - env->sregs[EXCCAUSE] =3D cause; - env->sregs[PS] |=3D PS_EXCM; - - HELPER(exception)(env, vector); -} - -void HELPER(exception_cause_vaddr)(CPUXtensaState *env, - uint32_t pc, uint32_t cause, uint32_t vaddr) -{ - env->sregs[EXCVADDR] =3D vaddr; - HELPER(exception_cause)(env, pc, cause); -} - -void debug_exception_env(CPUXtensaState *env, uint32_t cause) -{ - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - HELPER(debug_exception)(env, env->pc, cause); - } -} - -void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) -{ - unsigned level =3D env->config->debug_level; - - env->pc =3D pc; - env->sregs[DEBUGCAUSE] =3D cause; - env->sregs[EPC1 + level - 1] =3D pc; - env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; - env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | - (level << PS_INTLEVEL_SHIFT); - HELPER(exception)(env, EXC_DEBUG); -} - void HELPER(dump_state)(CPUXtensaState *env) { XtensaCPU *cpu =3D xtensa_env_get_cpu(env); @@ -168,28 +104,6 @@ void HELPER(dump_state)(CPUXtensaState *env) =20 #ifndef CONFIG_USER_ONLY =20 -void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) -{ - CPUState *cpu; - - env->pc =3D pc; - env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | - (intlevel << PS_INTLEVEL_SHIFT); - - qemu_mutex_lock_iothread(); - check_interrupts(env); - qemu_mutex_unlock_iothread(); - - if (env->pending_irq_level) { - cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); - return; - } - - cpu =3D CPU(xtensa_env_get_cpu(env)); - cpu->halted =3D 1; - HELPER(exception)(env, EXCP_HLT); -} - void HELPER(update_ccount)(CPUXtensaState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -222,13 +136,6 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint= 32_t i) env->yield_needed =3D 1; } =20 -void HELPER(check_interrupts)(CPUXtensaState *env) -{ - qemu_mutex_lock_iothread(); - check_interrupts(env); - qemu_mutex_unlock_iothread(); -} - /*! * Check vaddr accessibility/cache attributes and raise an exception if * specified by the ATOMCTL SR. --=20 2.11.0