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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bWesseHbRg5KmDDJQeD065l6Krya82JW3p7IuVEcnuc=; b=nv8S8AMIKc8T/MG7l3XQ//Dk0CeT4Vks9vwh08XonidEhSqemZ+oHcBGaO9MLK2NYY RdU9d1aR0nsMtesnNTEtVLvzQx6QjDqWdFk3j/9Fraq2oVke9bJoRlR5eG4V1dsCFzFY GRe5+SKtUrqkiYkBKZf54j+CUgg3x2Ov7gpwjN8/kENEOjC7HEk3ytZIfDroNQe5M2/t igX4cP/hC5+waKn/w1Tl7BxxYRguVS4xt8nrK4ckOaSscg6WGpIpC1ZYVAQ6dOCsEPwT YUFGwB1nYCJ4H0gWnqDG1EEhp4Hs/b4AyuK9IkLUUEijQ2rm1fZR9erG27gRWSKbsQjB CnOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bWesseHbRg5KmDDJQeD065l6Krya82JW3p7IuVEcnuc=; b=jlqJQFXz2crxQ2GzHhPcKl8FPO9fG5rilQXUb1xd6ZX/yAD64Uil8dPR8GrS7i+qLM b+TAv6GSbczRCphzX5NiNFXxAckhjaTjcZF4zwj6evvSLWDzG/Emz+D7k+qaQ/uZD46H bVdVxuEgfesRHQXkGAIcLEHvpjmd7RTDzqBuOfO6jkCLrup+4fS2EItWCSfRPnXDpYAX 5jmWmi09d3n6X3cj5b0wIrQT31sBVd8/zXv+bFkEOa7yhGHrTuemwfFCXd5n27vnjzlP Dv7xQH7LXmPUoO8TuX6J3dLIuZjX3LjLxx8jxYLJryIEORUhuKeLdXcdbF9TmYy3OncJ tK/g== X-Gm-Message-State: AJcUukcY+i/sDr7RsRA1BYTzCrFNC7YnPV8QL8r2DpbneOy2QluvYs6e SynA3/vo3H7qwuGgOuxkDFx7JOeK X-Google-Smtp-Source: ALg8bN5OtUqPwBkbWfTsZM728BG3NSAo72h5XO3liFj30rpM70teTIIkALaHku8trOT3XztOnL15mQ== X-Received: by 2002:a19:9508:: with SMTP id x8mr13090926lfd.112.1547452159505; Sun, 13 Jan 2019 23:49:19 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:49 -0800 Message-Id: <20190114074855.16891-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::144 Subject: [Qemu-devel] [PATCH 1/7] target/xtensa: extract FPU helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move FPU-related HELPER functions from op_helper.c to fpu_helper.c No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/fpu_helper.c | 166 ++++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/op_helper.c | 135 ----------------------------------- 3 files changed, 167 insertions(+), 135 deletions(-) create mode 100644 target/xtensa/fpu_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index f63352cc04db..1508714c4475 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -7,4 +7,5 @@ obj-y +=3D core-test_kc705_be.o obj-$(CONFIG_SOFTMMU) +=3D monitor.o xtensa-semi.o obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o +obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c new file mode 100644 index 000000000000..f8bbb6cdd824 --- /dev/null +++ b/target/xtensa/fpu_helper.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "fpu/softfloat.h" + +void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) +{ + static const int rounding_mode[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down, + }; + + env->uregs[FCR] =3D v & 0xfffff07f; + set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); +} + +float32 HELPER(abs_s)(float32 v) +{ + return float32_abs(v); +} + +float32 HELPER(neg_s)(float32 v) +{ + return float32_chs(v); +} + +float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_add(a, b, &env->fp_status); +} + +float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_sub(a, b, &env->fp_status); +} + +float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_mul(a, b, &env->fp_status); +} + +float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 = c) +{ + return float32_muladd(b, c, a, 0, &env->fp_status); +} + +float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 = c) +{ + return float32_muladd(b, c, a, float_muladd_negate_product, + &env->fp_status); +} + +uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status =3D {0}; + + set_float_rounding_mode(rounding_mode, &fp_status); + return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_stat= us); +} + +uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) +{ + float_status fp_status =3D {0}; + float32 res; + + set_float_rounding_mode(rounding_mode, &fp_status); + + res =3D float32_scalbn(v, scale, &fp_status); + + if (float32_is_neg(v) && !float32_is_any_nan(v)) { + return float32_to_int32(res, &fp_status); + } else { + return float32_to_uint32(res, &fp_status); + } +} + +float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(int32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} + +float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) +{ + return float32_scalbn(uint32_to_float32(v, &env->fp_status), + (int32_t)scale, &env->fp_status); +} + +static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) +{ + if (v) { + env->sregs[BR] |=3D br; + } else { + env->sregs[BR] &=3D ~br; + } +} + +void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); +} + +void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v =3D float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v =3D=3D float_relation_equal || v =3D=3D float_relation_u= nordered, br); +} + +void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v =3D float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v =3D=3D float_relation_less || v =3D=3D float_relation_un= ordered, br); +} + +void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + set_br(env, float32_le_quiet(a, b, &env->fp_status), br); +} + +void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) +{ + int v =3D float32_compare_quiet(a, b, &env->fp_status); + set_br(env, v !=3D float_relation_greater, br); +} diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 078aeb6c2c94..47517359ca67 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -34,7 +34,6 @@ #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "qemu/timer.h" -#include "fpu/softfloat.h" =20 #ifndef CONFIG_USER_ONLY =20 @@ -890,140 +889,6 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_= t i, uint32_t v) } #endif =20 -void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) -{ - static const int rounding_mode[] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down, - }; - - env->uregs[FCR] =3D v & 0xfffff07f; - set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); -} - -float32 HELPER(abs_s)(float32 v) -{ - return float32_abs(v); -} - -float32 HELPER(neg_s)(float32 v) -{ - return float32_chs(v); -} - -float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) -{ - return float32_add(a, b, &env->fp_status); -} - -float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) -{ - return float32_sub(a, b, &env->fp_status); -} - -float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) -{ - return float32_mul(a, b, &env->fp_status); -} - -float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 = c) -{ - return float32_muladd(b, c, a, 0, - &env->fp_status); -} - -float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 = c) -{ - return float32_muladd(b, c, a, float_muladd_negate_product, - &env->fp_status); -} - -uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale) -{ - float_status fp_status =3D {0}; - - set_float_rounding_mode(rounding_mode, &fp_status); - return float32_to_int32( - float32_scalbn(v, scale, &fp_status), &fp_status); -} - -uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale) -{ - float_status fp_status =3D {0}; - float32 res; - - set_float_rounding_mode(rounding_mode, &fp_status); - - res =3D float32_scalbn(v, scale, &fp_status); - - if (float32_is_neg(v) && !float32_is_any_nan(v)) { - return float32_to_int32(res, &fp_status); - } else { - return float32_to_uint32(res, &fp_status); - } -} - -float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale) -{ - return float32_scalbn(int32_to_float32(v, &env->fp_status), - (int32_t)scale, &env->fp_status); -} - -float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale) -{ - return float32_scalbn(uint32_to_float32(v, &env->fp_status), - (int32_t)scale, &env->fp_status); -} - -static inline void set_br(CPUXtensaState *env, bool v, uint32_t br) -{ - if (v) { - env->sregs[BR] |=3D br; - } else { - env->sregs[BR] &=3D ~br; - } -} - -void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br); -} - -void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - set_br(env, float32_eq_quiet(a, b, &env->fp_status), br); -} - -void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - int v =3D float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v =3D=3D float_relation_equal || v =3D=3D float_relation_u= nordered, br); -} - -void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - set_br(env, float32_lt_quiet(a, b, &env->fp_status), br); -} - -void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - int v =3D float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v =3D=3D float_relation_less || v =3D=3D float_relation_un= ordered, br); -} - -void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - set_br(env, float32_le_quiet(a, b, &env->fp_status), br); -} - -void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b) -{ - int v =3D float32_compare_quiet(a, b, &env->fp_status); - set_br(env, v !=3D float_relation_greater, br); -} - uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr) { #ifndef CONFIG_USER_ONLY --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I9cO+HiCW5QlzzCTe5B+FRNDlWFB5rbQn6JvWgUzc9g=; b=TBBKvwRSy/coRswNMygo+vSqORfo7Ef0sxQPFYn53OiCFBGqhInym4wLKbhXaGoM4q 3wS5oe4l3B9cdy9paOPq8qjbVg8nkkj803znq8lgSaFN42lUTLJI7UKzeyviHAbBBc9K 31oTidQYHoShVXTWOxFpVnwkP0YPzS42lQDId7fPAxgoxj9og0sFfR+5onHOW1wVSrBY PraedpwUthphfd5B8o5pZ2dXzZgnF9rkaGRXeZElS+dbbFUzZRsGv+Y5OF+aSxKMdzU8 058bjiCDJ+OAS+NtnArvctt4aRZSQEtdyZXREBizRDEsYUWqVgV2kS1svFq3Z27wPdXt xB4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I9cO+HiCW5QlzzCTe5B+FRNDlWFB5rbQn6JvWgUzc9g=; b=p8NZOqO5hScHeKMP0USfapf12yfl8j6xnWwWxtf32rUUjpc5h1ZOIevIwdTjiXzGTJ bA7IWNunSXAneLecW3LvwOHVXMugR+9p7ElFoa0UCx19oMdM827SBWmGYJnk0c1KKiRC 1rTIRqwLiwpxLk9C0dOJCMYf5tx1rw9G0gwxqypU3SzDmzSx9qDuxxw1vMABT8TnD1R+ 24DDOTP5b1oypnsVjCPSEk6STKNpbfSrgX1R6w4TqEc4q/ypwzFm6KJ8A+/mcuXdNmNs Zg2fClv4zdyknO0mpNqo+jjDKmHVpRVI+34GfUtJBU2rzx8fBtProFKzBSFeabTiSpH2 NHuw== X-Gm-Message-State: AJcUukfZvzDAsFi0tRXLXYIFKyzLP1Z/tCi9nIRoF7SCytk8LyvvS4RI eORNZkV5mcRZ8bDgEdvdWA97Co+U X-Google-Smtp-Source: ALg8bN5CMQEUrMbMwrWzbNl5QAhL1AhNU9ybWFkJqED7n1+vQrliiMVUrEpogXfoejbip5v1Nx2edQ== X-Received: by 2002:a19:280f:: with SMTP id o15mr2755133lfo.0.1547452161979; Sun, 13 Jan 2019 23:49:21 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:50 -0800 Message-Id: <20190114074855.16891-3-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::142 Subject: [Qemu-devel] [PATCH 2/7] target/xtensa: extract windowed registers helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move helper functions related to register windows from op_helper.c to win_helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/op_helper.c | 190 ------------------------------------- target/xtensa/win_helper.c | 222 ++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 223 insertions(+), 190 deletions(-) create mode 100644 target/xtensa/win_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index 1508714c4475..cc550c2ccb51 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -9,3 +9,4 @@ obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o +obj-y +=3D win_helper.o diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 47517359ca67..946ae1f91b0c 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -172,196 +172,6 @@ void HELPER(debug_exception)(CPUXtensaState *env, uin= t32_t pc, uint32_t cause) HELPER(exception)(env, EXC_DEBUG); } =20 -static void copy_window_from_phys(CPUXtensaState *env, - uint32_t window, uint32_t phys, uint32_t n) -{ - assert(phys < env->config->nareg); - if (phys + n <=3D env->config->nareg) { - memcpy(env->regs + window, env->phys_regs + phys, - n * sizeof(uint32_t)); - } else { - uint32_t n1 =3D env->config->nareg - phys; - memcpy(env->regs + window, env->phys_regs + phys, - n1 * sizeof(uint32_t)); - memcpy(env->regs + window + n1, env->phys_regs, - (n - n1) * sizeof(uint32_t)); - } -} - -static void copy_phys_from_window(CPUXtensaState *env, - uint32_t phys, uint32_t window, uint32_t n) -{ - assert(phys < env->config->nareg); - if (phys + n <=3D env->config->nareg) { - memcpy(env->phys_regs + phys, env->regs + window, - n * sizeof(uint32_t)); - } else { - uint32_t n1 =3D env->config->nareg - phys; - memcpy(env->phys_regs + phys, env->regs + window, - n1 * sizeof(uint32_t)); - memcpy(env->phys_regs, env->regs + window + n1, - (n - n1) * sizeof(uint32_t)); - } -} - - -static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *= env) -{ - return a & (env->config->nareg / 4 - 1); -} - -static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *e= nv) -{ - return 1 << windowbase_bound(a, env); -} - -void xtensa_sync_window_from_phys(CPUXtensaState *env) -{ - copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); -} - -void xtensa_sync_phys_from_window(CPUXtensaState *env) -{ - copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); -} - -static void xtensa_rotate_window_abs(CPUXtensaState *env, uint32_t positio= n) -{ - xtensa_sync_phys_from_window(env); - env->sregs[WINDOW_BASE] =3D windowbase_bound(position, env); - xtensa_sync_window_from_phys(env); -} - -void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) -{ - xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); -} - -void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) -{ - xtensa_rotate_window_abs(env, v); -} - -void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t = imm) -{ - int callinc =3D (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; - - env->regs[(callinc << 2) | (s & 3)] =3D env->regs[s] - imm; - xtensa_rotate_window(env, callinc); - env->sregs[WINDOW_START] |=3D - windowstart_bit(env->sregs[WINDOW_BASE], env); -} - -void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) -{ - uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t n =3D ctz32(windowstart) + 1; - - assert(n <=3D w); - - xtensa_rotate_window(env, n); - env->sregs[PS] =3D (env->sregs[PS] & ~PS_OWB) | - (windowbase << PS_OWB_SHIFT) | PS_EXCM; - env->sregs[EPC1] =3D env->pc =3D pc; - - switch (ctz32(windowstart >> n)) { - case 0: - HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); - break; - case 1: - HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); - break; - default: - HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); - break; - } -} - -void HELPER(test_ill_retw)(CPUXtensaState *env, uint32_t pc) -{ - int n =3D (env->regs[0] >> 30) & 0x3; - int m =3D 0; - uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); - uint32_t windowstart =3D env->sregs[WINDOW_START]; - - if (windowstart & windowstart_bit(windowbase - 1, env)) { - m =3D 1; - } else if (windowstart & windowstart_bit(windowbase - 2, env)) { - m =3D 2; - } else if (windowstart & windowstart_bit(windowbase - 3, env)) { - m =3D 3; - } - - if (n =3D=3D 0 || (m !=3D 0 && m !=3D n)) { - qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc =3D %0= 8x), " - "PS =3D %08x, m =3D %d, n =3D %d\n", - pc, env->sregs[PS], m, n); - HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); - } -} - -void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc) -{ - int n =3D (env->regs[0] >> 30) & 0x3; - - if (!(env->sregs[WINDOW_START] & - windowstart_bit(env->sregs[WINDOW_BASE] - n, env))) { - uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], = env); - - xtensa_rotate_window(env, -n); - /* window underflow */ - env->sregs[PS] =3D (env->sregs[PS] & ~PS_OWB) | - (windowbase << PS_OWB_SHIFT) | PS_EXCM; - env->sregs[EPC1] =3D env->pc =3D pc; - - if (n =3D=3D 1) { - HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); - } else if (n =3D=3D 2) { - HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); - } else if (n =3D=3D 3) { - HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); - } - } -} - -uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) -{ - int n =3D (env->regs[0] >> 30) & 0x3; - uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); - uint32_t ret_pc =3D (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); - - xtensa_rotate_window(env, -n); - env->sregs[WINDOW_START] &=3D ~windowstart_bit(windowbase, env); - return ret_pc; -} - -void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) -{ - xtensa_rotate_window(env, imm4); -} - -void xtensa_restore_owb(CPUXtensaState *env) -{ - xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIF= T); -} - -void HELPER(restore_owb)(CPUXtensaState *env) -{ - xtensa_restore_owb(env); -} - -void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) -{ - if ((env->sregs[WINDOW_START] & - (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | - windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | - windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) =3D=3D 0)= { - HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); - } -} - void HELPER(dump_state)(CPUXtensaState *env) { XtensaCPU *cpu =3D xtensa_env_get_cpu(env); diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c new file mode 100644 index 000000000000..7d793d4f9cff --- /dev/null +++ b/target/xtensa/win_helper.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" + +static void copy_window_from_phys(CPUXtensaState *env, + uint32_t window, uint32_t phys, uint32_t= n) +{ + assert(phys < env->config->nareg); + if (phys + n <=3D env->config->nareg) { + memcpy(env->regs + window, env->phys_regs + phys, + n * sizeof(uint32_t)); + } else { + uint32_t n1 =3D env->config->nareg - phys; + memcpy(env->regs + window, env->phys_regs + phys, + n1 * sizeof(uint32_t)); + memcpy(env->regs + window + n1, env->phys_regs, + (n - n1) * sizeof(uint32_t)); + } +} + +static void copy_phys_from_window(CPUXtensaState *env, + uint32_t phys, uint32_t window, uint32_t= n) +{ + assert(phys < env->config->nareg); + if (phys + n <=3D env->config->nareg) { + memcpy(env->phys_regs + phys, env->regs + window, + n * sizeof(uint32_t)); + } else { + uint32_t n1 =3D env->config->nareg - phys; + memcpy(env->phys_regs + phys, env->regs + window, + n1 * sizeof(uint32_t)); + memcpy(env->phys_regs, env->regs + window + n1, + (n - n1) * sizeof(uint32_t)); + } +} + +static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *= env) +{ + return a & (env->config->nareg / 4 - 1); +} + +static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *e= nv) +{ + return 1 << windowbase_bound(a, env); +} + +void xtensa_sync_window_from_phys(CPUXtensaState *env) +{ + copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); +} + +void xtensa_sync_phys_from_window(CPUXtensaState *env) +{ + copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); +} + +static void xtensa_rotate_window_abs(CPUXtensaState *env, uint32_t positio= n) +{ + xtensa_sync_phys_from_window(env); + env->sregs[WINDOW_BASE] =3D windowbase_bound(position, env); + xtensa_sync_window_from_phys(env); +} + +void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) +{ + xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); +} + +void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) +{ + xtensa_rotate_window_abs(env, v); +} + +void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t = imm) +{ + int callinc =3D (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; + + env->regs[(callinc << 2) | (s & 3)] =3D env->regs[s] - imm; + xtensa_rotate_window(env, callinc); + env->sregs[WINDOW_START] |=3D + windowstart_bit(env->sregs[WINDOW_BASE], env); +} + +void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) +{ + uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t n =3D ctz32(windowstart) + 1; + + assert(n <=3D w); + + xtensa_rotate_window(env, n); + env->sregs[PS] =3D (env->sregs[PS] & ~PS_OWB) | + (windowbase << PS_OWB_SHIFT) | PS_EXCM; + env->sregs[EPC1] =3D env->pc =3D pc; + + switch (ctz32(windowstart >> n)) { + case 0: + HELPER(exception)(env, EXC_WINDOW_OVERFLOW4); + break; + case 1: + HELPER(exception)(env, EXC_WINDOW_OVERFLOW8); + break; + default: + HELPER(exception)(env, EXC_WINDOW_OVERFLOW12); + break; + } +} + +void HELPER(test_ill_retw)(CPUXtensaState *env, uint32_t pc) +{ + int n =3D (env->regs[0] >> 30) & 0x3; + int m =3D 0; + uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); + uint32_t windowstart =3D env->sregs[WINDOW_START]; + + if (windowstart & windowstart_bit(windowbase - 1, env)) { + m =3D 1; + } else if (windowstart & windowstart_bit(windowbase - 2, env)) { + m =3D 2; + } else if (windowstart & windowstart_bit(windowbase - 3, env)) { + m =3D 3; + } + + if (n =3D=3D 0 || (m !=3D 0 && m !=3D n)) { + qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc =3D %0= 8x), " + "PS =3D %08x, m =3D %d, n =3D %d\n", + pc, env->sregs[PS], m, n); + HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE); + } +} + +void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc) +{ + int n =3D (env->regs[0] >> 30) & 0x3; + + if (!(env->sregs[WINDOW_START] & + windowstart_bit(env->sregs[WINDOW_BASE] - n, env))) { + uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], = env); + + xtensa_rotate_window(env, -n); + /* window underflow */ + env->sregs[PS] =3D (env->sregs[PS] & ~PS_OWB) | + (windowbase << PS_OWB_SHIFT) | PS_EXCM; + env->sregs[EPC1] =3D env->pc =3D pc; + + if (n =3D=3D 1) { + HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4); + } else if (n =3D=3D 2) { + HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8); + } else if (n =3D=3D 3) { + HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12); + } + } +} + +uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) +{ + int n =3D (env->regs[0] >> 30) & 0x3; + uint32_t windowbase =3D windowbase_bound(env->sregs[WINDOW_BASE], env); + uint32_t ret_pc =3D (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); + + xtensa_rotate_window(env, -n); + env->sregs[WINDOW_START] &=3D ~windowstart_bit(windowbase, env); + return ret_pc; +} + +void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) +{ + xtensa_rotate_window(env, imm4); +} + +void xtensa_restore_owb(CPUXtensaState *env) +{ + xtensa_rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIF= T); +} + +void HELPER(restore_owb)(CPUXtensaState *env) +{ + xtensa_restore_owb(env); +} + +void HELPER(movsp)(CPUXtensaState *env, uint32_t pc) +{ + if ((env->sregs[WINDOW_START] & + (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) | + windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) | + windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) =3D=3D 0) { + HELPER(exception_cause)(env, pc, ALLOCA_CAUSE); + } +} --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BvbgsAGNMO5bSxoR+P/dL3FolbPZf50nLUnjFeqIVt8=; b=PrpzO98fDbZTalKurwHVdtVjqhtIUB6bO1HXVnh9RxNc1BppN99yLEueYk+WIjEICK Zf5KoOnL6QSphrScIOzJhDLAbzN/iQBlf527UzctOCOj4cpSODe7X5UYZTtFLLklOnt0 2/DYQ8Yrtu1VaRiRMS2wl6EaOEtb+m74gQ5oawSr8ZkTr1LWk9lpztb/uwlU4Q7TNgBd EoLxvRdM1J9KV1HKri54hi6AHv7btS9L0F/n0ifzzwhS0CaSkOuvmf4yoSIXTYsFufsh 92FViflNLdLjMy2E3W3H28SvUPDAMjM4JJ8ex1s7lVIINaBdOU98bF2bquVcfoSLVNlB AUeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BvbgsAGNMO5bSxoR+P/dL3FolbPZf50nLUnjFeqIVt8=; b=KHP1AkiXd22iUWCJlTi1GA99ny/5ifCEghx8fD/sfKzJ2EqFtkbaMnT4SXm2xUmjSv EluAZfDF+jA3EuzQlqHAODAmCQgVOYI9mBnHhJAorwzchKYgveLWe1d9oj96hUl9e5d7 kWw9kuEH4S/WMhLBrH9J8kH/PWhlBplLPKmg96DNBl5nLh68DnnOnJr0Z1ykMB4Zcs03 wEJggli0KqQfaRxNlmm2tij/Rbm/1ws3kak7XF8RMlUvdkjLhzKuAXEAHBtN+h2KSLeo 3YOUaJuAg60+5c5Wlo73f+CLzUuvDt7FoxyJJfxy+61JHhSN1IT0hn1O30nkmAWz1Fb+ /qfA== X-Gm-Message-State: AJcUukcg0ElTCXA9Ygk7ufljTixkdVDyDRBldpfLCf0FCFhIceLtOo60 ZV2q/B7KtTXHoI8okh2njq3vxqym X-Google-Smtp-Source: ALg8bN5pEo+oGtM1z4cWo9yv6WWaigSVWLihPPYMrBGCDDZ2Qyftmu0cZSzFku7x4so02WLcGrEbQA== X-Received: by 2002:a2e:9181:: with SMTP id f1-v6mr2605856ljg.64.1547452164651; Sun, 13 Jan 2019 23:49:24 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:51 -0800 Message-Id: <20190114074855.16891-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::241 Subject: [Qemu-devel] [PATCH 3/7] target/xtensa: extract MMU helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move MMU-related helper functions from op_helper.c and helper.c to mmu_helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/helper.c | 487 -------------------------- target/xtensa/mmu_helper.c | 818 ++++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/op_helper.c | 293 ---------------- 4 files changed, 819 insertions(+), 780 deletions(-) create mode 100644 target/xtensa/mmu_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index cc550c2ccb51..b2c720b2df9b 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -9,4 +9,5 @@ obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o +obj-$(CONFIG_SOFTMMU) +=3D mmu_helper.o obj-y +=3D win_helper.o diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 501082f55b55..c344241bd06e 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -26,7 +26,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" @@ -170,28 +169,6 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fpr= intf) } } =20 -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ -#ifndef CONFIG_USER_ONLY - XtensaCPU *cpu =3D XTENSA_CPU(cs); - uint32_t paddr; - uint32_t page_size; - unsigned access; - - if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, - &paddr, &page_size, &access) =3D=3D 0) { - return paddr; - } - if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, - &paddr, &page_size, &access) =3D=3D 0) { - return paddr; - } - return ~0; -#else - return addr; -#endif -} - #ifndef CONFIG_USER_ONLY =20 static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) @@ -338,470 +315,6 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr a= ddress, int size, int rw, =20 #else =20 -static void reset_tlb_mmu_all_ways(CPUXtensaState *env, - const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - unsigned wi, ei; - - for (wi =3D 0; wi < tlb->nways; ++wi) { - for (ei =3D 0; ei < tlb->way_size[wi]; ++ei) { - entry[wi][ei].asid =3D 0; - entry[wi][ei].variable =3D true; - } - } -} - -static void reset_tlb_mmu_ways56(CPUXtensaState *env, - const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - if (!tlb->varway56) { - static const xtensa_tlb_entry way5[] =3D { - { - .vaddr =3D 0xd0000000, - .paddr =3D 0, - .asid =3D 1, - .attr =3D 7, - .variable =3D false, - }, { - .vaddr =3D 0xd8000000, - .paddr =3D 0, - .asid =3D 1, - .attr =3D 3, - .variable =3D false, - } - }; - static const xtensa_tlb_entry way6[] =3D { - { - .vaddr =3D 0xe0000000, - .paddr =3D 0xf0000000, - .asid =3D 1, - .attr =3D 7, - .variable =3D false, - }, { - .vaddr =3D 0xf0000000, - .paddr =3D 0xf0000000, - .asid =3D 1, - .attr =3D 3, - .variable =3D false, - } - }; - memcpy(entry[5], way5, sizeof(way5)); - memcpy(entry[6], way6, sizeof(way6)); - } else { - uint32_t ei; - for (ei =3D 0; ei < 8; ++ei) { - entry[6][ei].vaddr =3D ei << 29; - entry[6][ei].paddr =3D ei << 29; - entry[6][ei].asid =3D 1; - entry[6][ei].attr =3D 3; - } - } -} - -static void reset_tlb_region_way0(CPUXtensaState *env, - xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - unsigned ei; - - for (ei =3D 0; ei < 8; ++ei) { - entry[0][ei].vaddr =3D ei << 29; - entry[0][ei].paddr =3D ei << 29; - entry[0][ei].asid =3D 1; - entry[0][ei].attr =3D 2; - entry[0][ei].variable =3D true; - } -} - -void reset_mmu(CPUXtensaState *env) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - env->sregs[RASID] =3D 0x04030201; - env->sregs[ITLBCFG] =3D 0; - env->sregs[DTLBCFG] =3D 0; - env->autorefill_idx =3D 0; - reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); - reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); - reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); - reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); - } else { - reset_tlb_region_way0(env, env->itlb); - reset_tlb_region_way0(env, env->dtlb); - } -} - -static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) -{ - unsigned i; - for (i =3D 0; i < 4; ++i) { - if (((env->sregs[RASID] >> i * 8) & 0xff) =3D=3D asid) { - return i; - } - } - return 0xff; -} - -/*! - * Lookup xtensa TLB for the given virtual address. - * See ISA, 4.6.2.2 - * - * \param pwi: [out] way index - * \param pei: [out] entry index - * \param pring: [out] access ring - * \return 0 if ok, exception cause code otherwise - */ -int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, - uint32_t *pwi, uint32_t *pei, uint8_t *pring) -{ - const xtensa_tlb *tlb =3D dtlb ? - &env->config->dtlb : &env->config->itlb; - const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] =3D dtlb ? - env->dtlb : env->itlb; - - int nhits =3D 0; - unsigned wi; - - for (wi =3D 0; wi < tlb->nways; ++wi) { - uint32_t vpn; - uint32_t ei; - split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); - if (entry[wi][ei].vaddr =3D=3D vpn && entry[wi][ei].asid) { - unsigned ring =3D get_ring(env, entry[wi][ei].asid); - if (ring < 4) { - if (++nhits > 1) { - return dtlb ? - LOAD_STORE_TLB_MULTI_HIT_CAUSE : - INST_TLB_MULTI_HIT_CAUSE; - } - *pwi =3D wi; - *pei =3D ei; - *pring =3D ring; - } - } - } - return nhits ? 0 : - (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); -} - -/*! - * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, 4.6.5.10 - */ -static unsigned mmu_attr_to_access(uint32_t attr) -{ - unsigned access =3D 0; - - if (attr < 12) { - access |=3D PAGE_READ; - if (attr & 0x1) { - access |=3D PAGE_EXEC; - } - if (attr & 0x2) { - access |=3D PAGE_WRITE; - } - - switch (attr & 0xc) { - case 0: - access |=3D PAGE_CACHE_BYPASS; - break; - - case 4: - access |=3D PAGE_CACHE_WB; - break; - - case 8: - access |=3D PAGE_CACHE_WT; - break; - } - } else if (attr =3D=3D 13) { - access |=3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; - } - return access; -} - -/*! - * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, 4.6.3.3 - */ -static unsigned region_attr_to_access(uint32_t attr) -{ - static const unsigned access[16] =3D { - [0] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, - [1] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, - [2] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, - [3] =3D PAGE_EXEC | PAGE_CACHE_WB, - [4] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [5] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [14] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, - }; - - return access[attr & 0xf]; -} - -/*! - * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, A.2.14 The Cache Attribute Register - */ -static unsigned cacheattr_attr_to_access(uint32_t attr) -{ - static const unsigned access[16] =3D { - [0] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, - [1] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, - [2] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, - [3] =3D PAGE_EXEC | PAGE_CACHE_WB, - [4] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [14] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, - }; - - return access[attr & 0xf]; -} - -static bool is_access_granted(unsigned access, int is_write) -{ - switch (is_write) { - case 0: - return access & PAGE_READ; - - case 1: - return access & PAGE_WRITE; - - case 2: - return access & PAGE_EXEC; - - default: - return 0; - } -} - -static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); - -static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, unsigned *access, - bool may_lookup_pt) -{ - bool dtlb =3D is_write !=3D 2; - uint32_t wi; - uint32_t ei; - uint8_t ring; - uint32_t vpn; - uint32_t pte; - const xtensa_tlb_entry *entry =3D NULL; - xtensa_tlb_entry tmp_entry; - int ret =3D xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); - - if ((ret =3D=3D INST_TLB_MISS_CAUSE || ret =3D=3D LOAD_STORE_TLB_MISS_= CAUSE) && - may_lookup_pt && get_pte(env, vaddr, &pte)) { - ring =3D (pte >> 4) & 0x3; - wi =3D 0; - split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); - - if (update_tlb) { - wi =3D ++env->autorefill_idx & 0x3; - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); - env->sregs[EXCVADDR] =3D vaddr; - qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x= \n", - __func__, vaddr, vpn, pte); - } else { - xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, p= te); - entry =3D &tmp_entry; - } - ret =3D 0; - } - if (ret !=3D 0) { - return ret; - } - - if (entry =3D=3D NULL) { - entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); - } - - if (ring < mmu_idx) { - return dtlb ? - LOAD_STORE_PRIVILEGE_CAUSE : - INST_FETCH_PRIVILEGE_CAUSE; - } - - *access =3D mmu_attr_to_access(entry->attr) & - ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); - if (!is_access_granted(*access, is_write)) { - return dtlb ? - (is_write ? - STORE_PROHIBITED_CAUSE : - LOAD_PROHIBITED_CAUSE) : - INST_FETCH_PROHIBITED_CAUSE; - } - - *paddr =3D entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb= , wi)); - *page_size =3D ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; - - return 0; -} - -static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) -{ - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - uint32_t paddr; - uint32_t page_size; - unsigned access; - uint32_t pt_vaddr =3D - (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; - int ret =3D get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, - &paddr, &page_size, &access, false); - - if (ret =3D=3D 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s: autorefill(%08x): PTE va =3D %08x, pa =3D %08x\= n", - __func__, vaddr, pt_vaddr, paddr); - } else { - qemu_log_mask(CPU_LOG_MMU, - "%s: autorefill(%08x): PTE va =3D %08x, failed (%d)\= n", - __func__, vaddr, pt_vaddr, ret); - } - - if (ret =3D=3D 0) { - MemTxResult result; - - *pte =3D address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, - &result); - if (result !=3D MEMTX_OK) { - qemu_log_mask(CPU_LOG_MMU, - "%s: couldn't load PTE: transaction failed (%u)\= n", - __func__, (unsigned)result); - ret =3D 1; - } - } - return ret =3D=3D 0; -} - -static int get_physical_addr_region(CPUXtensaState *env, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, unsigned *access) -{ - bool dtlb =3D is_write !=3D 2; - uint32_t wi =3D 0; - uint32_t ei =3D (vaddr >> 29) & 0x7; - const xtensa_tlb_entry *entry =3D - xtensa_tlb_get_entry(env, dtlb, wi, ei); - - *access =3D region_attr_to_access(entry->attr); - if (!is_access_granted(*access, is_write)) { - return dtlb ? - (is_write ? - STORE_PROHIBITED_CAUSE : - LOAD_PROHIBITED_CAUSE) : - INST_FETCH_PROHIBITED_CAUSE; - } - - *paddr =3D entry->paddr | (vaddr & ~REGION_PAGE_MASK); - *page_size =3D ~REGION_PAGE_MASK + 1; - - return 0; -} - -/*! - * Convert virtual address to physical addr. - * MMU may issue pagewalk and change xtensa autorefill TLB way entry. - * - * \return 0 if ok, exception cause code otherwise - */ -int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, unsigned *access) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - return get_physical_addr_mmu(env, update_tlb, - vaddr, is_write, mmu_idx, paddr, page_size, access, true); - } else if (xtensa_option_bits_enabled(env->config, - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { - return get_physical_addr_region(env, vaddr, is_write, mmu_idx, - paddr, page_size, access); - } else { - *paddr =3D vaddr; - *page_size =3D TARGET_PAGE_SIZE; - *access =3D cacheattr_attr_to_access( - env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27)); - return 0; - } -} - -static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, - CPUXtensaState *env, bool dtlb) -{ - unsigned wi, ei; - const xtensa_tlb *conf =3D - dtlb ? &env->config->dtlb : &env->config->itlb; - unsigned (*attr_to_access)(uint32_t) =3D - xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? - mmu_attr_to_access : region_attr_to_access; - - for (wi =3D 0; wi < conf->nways; ++wi) { - uint32_t sz =3D ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; - const char *sz_text; - bool print_header =3D true; - - if (sz >=3D 0x100000) { - sz /=3D MiB; - sz_text =3D "MB"; - } else { - sz /=3D KiB; - sz_text =3D "KB"; - } - - for (ei =3D 0; ei < conf->way_size[wi]; ++ei) { - const xtensa_tlb_entry *entry =3D - xtensa_tlb_get_entry(env, dtlb, wi, ei); - - if (entry->asid) { - static const char * const cache_text[8] =3D { - [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] =3D "Bypass", - [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] =3D "WT", - [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] =3D "WB", - [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] =3D "Isolate", - }; - unsigned access =3D attr_to_access(entry->attr); - unsigned cache_idx =3D (access & PAGE_CACHE_MASK) >> - PAGE_CACHE_SHIFT; - - if (print_header) { - print_header =3D false; - cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); - cpu_fprintf(f, - "\tVaddr Paddr ASID Attr RWX Cach= e\n" - "\t---------- ---------- ---- ---- --- ----= ---\n"); - } - cpu_fprintf(f, - "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", - entry->vaddr, - entry->paddr, - entry->asid, - entry->attr, - (access & PAGE_READ) ? 'R' : '-', - (access & PAGE_WRITE) ? 'W' : '-', - (access & PAGE_EXEC) ? 'X' : '-', - cache_text[cache_idx] ? cache_text[cache_idx] : - "Invalid"); - } - } - } -} - -void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) -{ - if (xtensa_option_bits_enabled(env->config, - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { - - cpu_fprintf(f, "ITLB:\n"); - dump_tlb(f, cpu_fprintf, env, false); - cpu_fprintf(f, "\nDTLB:\n"); - dump_tlb(f, cpu_fprintf, env, true); - } else { - cpu_fprintf(f, "No TLB for this CPU core\n"); - } -} - void xtensa_runstall(CPUXtensaState *env, bool runstall) { CPUState *cpu =3D CPU(xtensa_env_get_cpu(env)); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c new file mode 100644 index 000000000000..2096fbbd9fc2 --- /dev/null +++ b/target/xtensa/mmu_helper.c @@ -0,0 +1,818 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "qemu/units.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" + +void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) +{ + /* + * Attempt the memory load; we don't care about the result but + * only the side-effects (ie any MMU or other exception) + */ + cpu_ldub_code_ra(env, vaddr, GETPC()); +} + +void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) +{ + XtensaCPU *cpu =3D xtensa_env_get_cpu(env); + + v =3D (v & 0xffffff00) | 0x1; + if (v !=3D env->sregs[RASID]) { + env->sregs[RASID] =3D v; + tlb_flush(CPU(cpu)); + } +} + +static uint32_t get_page_size(const CPUXtensaState *env, + bool dtlb, uint32_t way) +{ + uint32_t tlbcfg =3D env->sregs[dtlb ? DTLBCFG : ITLBCFG]; + + switch (way) { + case 4: + return (tlbcfg >> 16) & 0x3; + + case 5: + return (tlbcfg >> 20) & 0x1; + + case 6: + return (tlbcfg >> 24) & 0x1; + + default: + return 0; + } +} + +/*! + * Get bit mask for the virtual address bits translated by the TLB way + */ +uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, + bool dtlb, uint32_t way) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + bool varway56 =3D dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + switch (way) { + case 4: + return 0xfff00000 << get_page_size(env, dtlb, way) * 2; + + case 5: + if (varway56) { + return 0xf8000000 << get_page_size(env, dtlb, way); + } else { + return 0xf8000000; + } + + case 6: + if (varway56) { + return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); + } else { + return 0xf0000000; + } + + default: + return 0xfffff000; + } + } else { + return REGION_PAGE_MASK; + } +} + +/*! + * Get bit mask for the 'VPN without index' field. + * See ISA, 4.6.5.6, data format for RxTLB0 + */ +static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_= t way) +{ + if (way < 4) { + bool is32 =3D (dtlb ? + env->config->dtlb.nrefillentries : + env->config->itlb.nrefillentries) =3D=3D 32; + return is32 ? 0xffff8000 : 0xffffc000; + } else if (way =3D=3D 4) { + return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; + } else if (way <=3D 6) { + uint32_t mask =3D xtensa_tlb_get_addr_mask(env, dtlb, way); + bool varway56 =3D dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + if (varway56) { + return mask << (way =3D=3D 5 ? 2 : 3); + } else { + return mask << 1; + } + } else { + return 0xfffff000; + } +} + +/*! + * Split virtual address into VPN (with index) and entry index + * for the given TLB way + */ +void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool = dtlb, + uint32_t *vpn, uint32_t wi, uint32_t *ei) +{ + bool varway56 =3D dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + if (!dtlb) { + wi &=3D 7; + } + + if (wi < 4) { + bool is32 =3D (dtlb ? + env->config->dtlb.nrefillentries : + env->config->itlb.nrefillentries) =3D=3D 32; + *ei =3D (v >> 12) & (is32 ? 0x7 : 0x3); + } else { + switch (wi) { + case 4: + { + uint32_t eibase =3D 20 + get_page_size(env, dtlb, wi) * 2; + *ei =3D (v >> eibase) & 0x3; + } + break; + + case 5: + if (varway56) { + uint32_t eibase =3D 27 + get_page_size(env, dtlb, wi); + *ei =3D (v >> eibase) & 0x3; + } else { + *ei =3D (v >> 27) & 0x1; + } + break; + + case 6: + if (varway56) { + uint32_t eibase =3D 29 - get_page_size(env, dtlb, wi); + *ei =3D (v >> eibase) & 0x7; + } else { + *ei =3D (v >> 28) & 0x1; + } + break; + + default: + *ei =3D 0; + break; + } + } + *vpn =3D v & xtensa_tlb_get_addr_mask(env, dtlb, wi); +} + +/*! + * Split TLB address into TLB way, entry index and VPN (with index). + * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format + */ +static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtl= b, + uint32_t *vpn, uint32_t *wi, uint32_t *ei) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + *wi =3D v & (dtlb ? 0xf : 0x7); + split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + } else { + *vpn =3D v & REGION_PAGE_MASK; + *wi =3D 0; + *ei =3D (v >> 29) & 0x7; + } +} + +static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, + uint32_t v, bool dtlb, uint32_t *pwi) +{ + uint32_t vpn; + uint32_t wi; + uint32_t ei; + + split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); + if (pwi) { + *pwi =3D wi; + } + return xtensa_tlb_get_entry(env, dtlb, wi, ei); +} + +uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + } else { + return v & REGION_PAGE_MASK; + } +} + +uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); + return entry->paddr | entry->attr; +} + +void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); + if (entry->variable && entry->asid) { + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); + entry->asid =3D 0; + } + } +} + +uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + uint32_t wi; + uint32_t ei; + uint8_t ring; + int res =3D xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); + + switch (res) { + case 0: + if (ring >=3D xtensa_get_ring(env)) { + return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); + } + break; + + case INST_TLB_MULTI_HIT_CAUSE: + case LOAD_STORE_TLB_MULTI_HIT_CAUSE: + HELPER(exception_cause_vaddr)(env, env->pc, res, v); + break; + } + return 0; + } else { + return (v & REGION_PAGE_MASK) | 0x1; + } +} + +void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, + xtensa_tlb_entry *entry, bool dtlb, + unsigned wi, unsigned ei, uint32_t vpn, + uint32_t pte) +{ + entry->vaddr =3D vpn; + entry->paddr =3D pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); + entry->asid =3D (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; + entry->attr =3D pte & 0xf; +} + +void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei, uint32_t vpn, uint32_t= pte) +{ + XtensaCPU *cpu =3D xtensa_env_get_cpu(env); + CPUState *cs =3D CPU(cpu); + xtensa_tlb_entry *entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); + + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + if (entry->variable) { + if (entry->asid) { + tlb_flush_page(cs, entry->vaddr); + } + xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); + tlb_flush_page(cs, entry->vaddr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s %d, %d, %d trying to set immutable entry\n", + __func__, dtlb, wi, ei); + } + } else { + tlb_flush_page(cs, entry->vaddr); + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_REGION_TRANSLATION)) { + entry->paddr =3D pte & REGION_PAGE_MASK; + } + entry->attr =3D pte & 0xf; + } +} + +void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dt= lb) +{ + uint32_t vpn; + uint32_t wi; + uint32_t ei; + split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); +} + +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + uint32_t paddr; + uint32_t page_size; + unsigned access; + + if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, + &paddr, &page_size, &access) =3D=3D 0) { + return paddr; + } + if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, + &paddr, &page_size, &access) =3D=3D 0) { + return paddr; + } + return ~0; +} + +static void reset_tlb_mmu_all_ways(CPUXtensaState *env, + const xtensa_tlb *tlb, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SI= ZE]) +{ + unsigned wi, ei; + + for (wi =3D 0; wi < tlb->nways; ++wi) { + for (ei =3D 0; ei < tlb->way_size[wi]; ++ei) { + entry[wi][ei].asid =3D 0; + entry[wi][ei].variable =3D true; + } + } +} + +static void reset_tlb_mmu_ways56(CPUXtensaState *env, + const xtensa_tlb *tlb, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE= ]) +{ + if (!tlb->varway56) { + static const xtensa_tlb_entry way5[] =3D { + { + .vaddr =3D 0xd0000000, + .paddr =3D 0, + .asid =3D 1, + .attr =3D 7, + .variable =3D false, + }, { + .vaddr =3D 0xd8000000, + .paddr =3D 0, + .asid =3D 1, + .attr =3D 3, + .variable =3D false, + } + }; + static const xtensa_tlb_entry way6[] =3D { + { + .vaddr =3D 0xe0000000, + .paddr =3D 0xf0000000, + .asid =3D 1, + .attr =3D 7, + .variable =3D false, + }, { + .vaddr =3D 0xf0000000, + .paddr =3D 0xf0000000, + .asid =3D 1, + .attr =3D 3, + .variable =3D false, + } + }; + memcpy(entry[5], way5, sizeof(way5)); + memcpy(entry[6], way6, sizeof(way6)); + } else { + uint32_t ei; + for (ei =3D 0; ei < 8; ++ei) { + entry[6][ei].vaddr =3D ei << 29; + entry[6][ei].paddr =3D ei << 29; + entry[6][ei].asid =3D 1; + entry[6][ei].attr =3D 3; + } + } +} + +static void reset_tlb_region_way0(CPUXtensaState *env, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZ= E]) +{ + unsigned ei; + + for (ei =3D 0; ei < 8; ++ei) { + entry[0][ei].vaddr =3D ei << 29; + entry[0][ei].paddr =3D ei << 29; + entry[0][ei].asid =3D 1; + entry[0][ei].attr =3D 2; + entry[0][ei].variable =3D true; + } +} + +void reset_mmu(CPUXtensaState *env) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + env->sregs[RASID] =3D 0x04030201; + env->sregs[ITLBCFG] =3D 0; + env->sregs[DTLBCFG] =3D 0; + env->autorefill_idx =3D 0; + reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); + reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); + reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); + reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); + } else { + reset_tlb_region_way0(env, env->itlb); + reset_tlb_region_way0(env, env->dtlb); + } +} + +static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) +{ + unsigned i; + for (i =3D 0; i < 4; ++i) { + if (((env->sregs[RASID] >> i * 8) & 0xff) =3D=3D asid) { + return i; + } + } + return 0xff; +} + +/*! + * Lookup xtensa TLB for the given virtual address. + * See ISA, 4.6.2.2 + * + * \param pwi: [out] way index + * \param pei: [out] entry index + * \param pring: [out] access ring + * \return 0 if ok, exception cause code otherwise + */ +int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, + uint32_t *pwi, uint32_t *pei, uint8_t *pring) +{ + const xtensa_tlb *tlb =3D dtlb ? + &env->config->dtlb : &env->config->itlb; + const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] =3D dtlb ? + env->dtlb : env->itlb; + + int nhits =3D 0; + unsigned wi; + + for (wi =3D 0; wi < tlb->nways; ++wi) { + uint32_t vpn; + uint32_t ei; + split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); + if (entry[wi][ei].vaddr =3D=3D vpn && entry[wi][ei].asid) { + unsigned ring =3D get_ring(env, entry[wi][ei].asid); + if (ring < 4) { + if (++nhits > 1) { + return dtlb ? + LOAD_STORE_TLB_MULTI_HIT_CAUSE : + INST_TLB_MULTI_HIT_CAUSE; + } + *pwi =3D wi; + *pei =3D ei; + *pring =3D ring; + } + } + } + return nhits ? 0 : + (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); +} + +/*! + * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, 4.6.5.10 + */ +static unsigned mmu_attr_to_access(uint32_t attr) +{ + unsigned access =3D 0; + + if (attr < 12) { + access |=3D PAGE_READ; + if (attr & 0x1) { + access |=3D PAGE_EXEC; + } + if (attr & 0x2) { + access |=3D PAGE_WRITE; + } + + switch (attr & 0xc) { + case 0: + access |=3D PAGE_CACHE_BYPASS; + break; + + case 4: + access |=3D PAGE_CACHE_WB; + break; + + case 8: + access |=3D PAGE_CACHE_WT; + break; + } + } else if (attr =3D=3D 13) { + access |=3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; + } + return access; +} + +/*! + * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, 4.6.3.3 + */ +static unsigned region_attr_to_access(uint32_t attr) +{ + static const unsigned access[16] =3D { + [0] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, + [1] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, + [2] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, + [3] =3D PAGE_EXEC | PAGE_CACHE_WB, + [4] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [5] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [14] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, + }; + + return access[attr & 0xf]; +} + +/*! + * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, A.2.14 The Cache Attribute Register + */ +static unsigned cacheattr_attr_to_access(uint32_t attr) +{ + static const unsigned access[16] =3D { + [0] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, + [1] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, + [2] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, + [3] =3D PAGE_EXEC | PAGE_CACHE_WB, + [4] =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [14] =3D PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, + }; + + return access[attr & 0xf]; +} + +static bool is_access_granted(unsigned access, int is_write) +{ + switch (is_write) { + case 0: + return access & PAGE_READ; + + case 1: + return access & PAGE_WRITE; + + case 2: + return access & PAGE_EXEC; + + default: + return 0; + } +} + +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); + +static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access, bool may_lookup_pt) +{ + bool dtlb =3D is_write !=3D 2; + uint32_t wi; + uint32_t ei; + uint8_t ring; + uint32_t vpn; + uint32_t pte; + const xtensa_tlb_entry *entry =3D NULL; + xtensa_tlb_entry tmp_entry; + int ret =3D xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); + + if ((ret =3D=3D INST_TLB_MISS_CAUSE || ret =3D=3D LOAD_STORE_TLB_MISS_= CAUSE) && + may_lookup_pt && get_pte(env, vaddr, &pte)) { + ring =3D (pte >> 4) & 0x3; + wi =3D 0; + split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); + + if (update_tlb) { + wi =3D ++env->autorefill_idx & 0x3; + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); + env->sregs[EXCVADDR] =3D vaddr; + qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x= \n", + __func__, vaddr, vpn, pte); + } else { + xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, p= te); + entry =3D &tmp_entry; + } + ret =3D 0; + } + if (ret !=3D 0) { + return ret; + } + + if (entry =3D=3D NULL) { + entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); + } + + if (ring < mmu_idx) { + return dtlb ? + LOAD_STORE_PRIVILEGE_CAUSE : + INST_FETCH_PRIVILEGE_CAUSE; + } + + *access =3D mmu_attr_to_access(entry->attr) & + ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); + if (!is_access_granted(*access, is_write)) { + return dtlb ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + + *paddr =3D entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb= , wi)); + *page_size =3D ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; + + return 0; +} + +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) +{ + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + uint32_t paddr; + uint32_t page_size; + unsigned access; + uint32_t pt_vaddr =3D + (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; + int ret =3D get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, + &paddr, &page_size, &access, false); + + if (ret =3D=3D 0) { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va =3D %08x, pa =3D %08x\= n", + __func__, vaddr, pt_vaddr, paddr); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va =3D %08x, failed (%d)\= n", + __func__, vaddr, pt_vaddr, ret); + } + + if (ret =3D=3D 0) { + MemTxResult result; + + *pte =3D address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, + &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(CPU_LOG_MMU, + "%s: couldn't load PTE: transaction failed (%u)\= n", + __func__, (unsigned)result); + ret =3D 1; + } + } + return ret =3D=3D 0; +} + +static int get_physical_addr_region(CPUXtensaState *env, + uint32_t vaddr, int is_write, int mmu_= idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + bool dtlb =3D is_write !=3D 2; + uint32_t wi =3D 0; + uint32_t ei =3D (vaddr >> 29) & 0x7; + const xtensa_tlb_entry *entry =3D + xtensa_tlb_get_entry(env, dtlb, wi, ei); + + *access =3D region_attr_to_access(entry->attr); + if (!is_access_granted(*access, is_write)) { + return dtlb ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + + *paddr =3D entry->paddr | (vaddr & ~REGION_PAGE_MASK); + *page_size =3D ~REGION_PAGE_MASK + 1; + + return 0; +} + +/*! + * Convert virtual address to physical addr. + * MMU may issue pagewalk and change xtensa autorefill TLB way entry. + * + * \return 0 if ok, exception cause code otherwise + */ +int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + return get_physical_addr_mmu(env, update_tlb, + vaddr, is_write, mmu_idx, paddr, + page_size, access, true); + } else if (xtensa_option_bits_enabled(env->config, + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { + return get_physical_addr_region(env, vaddr, is_write, mmu_idx, + paddr, page_size, access); + } else { + *paddr =3D vaddr; + *page_size =3D TARGET_PAGE_SIZE; + *access =3D cacheattr_attr_to_access(env->sregs[CACHEATTR] >> + ((vaddr & 0xe0000000) >> 27)); + return 0; + } +} + +static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, + CPUXtensaState *env, bool dtlb) +{ + unsigned wi, ei; + const xtensa_tlb *conf =3D + dtlb ? &env->config->dtlb : &env->config->itlb; + unsigned (*attr_to_access)(uint32_t) =3D + xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? + mmu_attr_to_access : region_attr_to_access; + + for (wi =3D 0; wi < conf->nways; ++wi) { + uint32_t sz =3D ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; + const char *sz_text; + bool print_header =3D true; + + if (sz >=3D 0x100000) { + sz /=3D MiB; + sz_text =3D "MB"; + } else { + sz /=3D KiB; + sz_text =3D "KB"; + } + + for (ei =3D 0; ei < conf->way_size[wi]; ++ei) { + const xtensa_tlb_entry *entry =3D + xtensa_tlb_get_entry(env, dtlb, wi, ei); + + if (entry->asid) { + static const char * const cache_text[8] =3D { + [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] =3D "Bypass", + [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] =3D "WT", + [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] =3D "WB", + [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] =3D "Isolate", + }; + unsigned access =3D attr_to_access(entry->attr); + unsigned cache_idx =3D (access & PAGE_CACHE_MASK) >> + PAGE_CACHE_SHIFT; + + if (print_header) { + print_header =3D false; + cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); + cpu_fprintf(f, + "\tVaddr Paddr ASID Attr RWX = Cache\n" + "\t---------- ---------- ---- ---- --- = -------\n"); + } + cpu_fprintf(f, + "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\= n", + entry->vaddr, + entry->paddr, + entry->asid, + entry->attr, + (access & PAGE_READ) ? 'R' : '-', + (access & PAGE_WRITE) ? 'W' : '-', + (access & PAGE_EXEC) ? 'X' : '-', + cache_text[cache_idx] ? + cache_text[cache_idx] : "Invalid"); + } + } + } +} + +void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) +{ + if (xtensa_option_bits_enabled(env->config, + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | + XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { + + cpu_fprintf(f, "ITLB:\n"); + dump_tlb(f, cpu_fprintf, env, false); + cpu_fprintf(f, "\nDTLB:\n"); + dump_tlb(f, cpu_fprintf, env, true); + } else { + cpu_fprintf(f, "No TLB for this CPU core\n"); + } +} diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 946ae1f91b0c..1d3d87012c4a 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -242,15 +242,6 @@ void HELPER(check_interrupts)(CPUXtensaState *env) qemu_mutex_unlock_iothread(); } =20 -void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) -{ - /* - * Attempt the memory load; we don't care about the result but - * only the side-effects (ie any MMU or other exception) - */ - cpu_ldub_code_ra(env, vaddr, GETPC()); -} - /*! * Check vaddr accessibility/cache attributes and raise an exception if * specified by the ATOMCTL SR. @@ -334,290 +325,6 @@ void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t= v) env->sregs[MEMCTL] =3D v & env->config->memctl_mask; } =20 -void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) -{ - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - - v =3D (v & 0xffffff00) | 0x1; - if (v !=3D env->sregs[RASID]) { - env->sregs[RASID] =3D v; - tlb_flush(CPU(cpu)); - } -} - -static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32= _t way) -{ - uint32_t tlbcfg =3D env->sregs[dtlb ? DTLBCFG : ITLBCFG]; - - switch (way) { - case 4: - return (tlbcfg >> 16) & 0x3; - - case 5: - return (tlbcfg >> 20) & 0x1; - - case 6: - return (tlbcfg >> 24) & 0x1; - - default: - return 0; - } -} - -/*! - * Get bit mask for the virtual address bits translated by the TLB way - */ -uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, ui= nt32_t way) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - bool varway56 =3D dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - switch (way) { - case 4: - return 0xfff00000 << get_page_size(env, dtlb, way) * 2; - - case 5: - if (varway56) { - return 0xf8000000 << get_page_size(env, dtlb, way); - } else { - return 0xf8000000; - } - - case 6: - if (varway56) { - return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); - } else { - return 0xf0000000; - } - - default: - return 0xfffff000; - } - } else { - return REGION_PAGE_MASK; - } -} - -/*! - * Get bit mask for the 'VPN without index' field. - * See ISA, 4.6.5.6, data format for RxTLB0 - */ -static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_= t way) -{ - if (way < 4) { - bool is32 =3D (dtlb ? - env->config->dtlb.nrefillentries : - env->config->itlb.nrefillentries) =3D=3D 32; - return is32 ? 0xffff8000 : 0xffffc000; - } else if (way =3D=3D 4) { - return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; - } else if (way <=3D 6) { - uint32_t mask =3D xtensa_tlb_get_addr_mask(env, dtlb, way); - bool varway56 =3D dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - if (varway56) { - return mask << (way =3D=3D 5 ? 2 : 3); - } else { - return mask << 1; - } - } else { - return 0xfffff000; - } -} - -/*! - * Split virtual address into VPN (with index) and entry index - * for the given TLB way - */ -void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool = dtlb, - uint32_t *vpn, uint32_t wi, uint32_t *ei) -{ - bool varway56 =3D dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - if (!dtlb) { - wi &=3D 7; - } - - if (wi < 4) { - bool is32 =3D (dtlb ? - env->config->dtlb.nrefillentries : - env->config->itlb.nrefillentries) =3D=3D 32; - *ei =3D (v >> 12) & (is32 ? 0x7 : 0x3); - } else { - switch (wi) { - case 4: - { - uint32_t eibase =3D 20 + get_page_size(env, dtlb, wi) * 2; - *ei =3D (v >> eibase) & 0x3; - } - break; - - case 5: - if (varway56) { - uint32_t eibase =3D 27 + get_page_size(env, dtlb, wi); - *ei =3D (v >> eibase) & 0x3; - } else { - *ei =3D (v >> 27) & 0x1; - } - break; - - case 6: - if (varway56) { - uint32_t eibase =3D 29 - get_page_size(env, dtlb, wi); - *ei =3D (v >> eibase) & 0x7; - } else { - *ei =3D (v >> 28) & 0x1; - } - break; - - default: - *ei =3D 0; - break; - } - } - *vpn =3D v & xtensa_tlb_get_addr_mask(env, dtlb, wi); -} - -/*! - * Split TLB address into TLB way, entry index and VPN (with index). - * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format - */ -static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtl= b, - uint32_t *vpn, uint32_t *wi, uint32_t *ei) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - *wi =3D v & (dtlb ? 0xf : 0x7); - split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); - } else { - *vpn =3D v & REGION_PAGE_MASK; - *wi =3D 0; - *ei =3D (v >> 29) & 0x7; - } -} - -static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, - uint32_t v, bool dtlb, uint32_t *pwi) -{ - uint32_t vpn; - uint32_t wi; - uint32_t ei; - - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - if (pwi) { - *pwi =3D wi; - } - return xtensa_tlb_get_entry(env, dtlb, wi, ei); -} - -uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; - } else { - return v & REGION_PAGE_MASK; - } -} - -uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - const xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, NULL); - return entry->paddr | entry->attr; -} - -void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - xtensa_tlb_entry *entry =3D get_tlb_entry(env, v, dtlb, &wi); - if (entry->variable && entry->asid) { - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); - entry->asid =3D 0; - } - } -} - -uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - uint32_t wi; - uint32_t ei; - uint8_t ring; - int res =3D xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); - - switch (res) { - case 0: - if (ring >=3D xtensa_get_ring(env)) { - return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); - } - break; - - case INST_TLB_MULTI_HIT_CAUSE: - case LOAD_STORE_TLB_MULTI_HIT_CAUSE: - HELPER(exception_cause_vaddr)(env, env->pc, res, v); - break; - } - return 0; - } else { - return (v & REGION_PAGE_MASK) | 0x1; - } -} - -void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, - xtensa_tlb_entry *entry, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) -{ - entry->vaddr =3D vpn; - entry->paddr =3D pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); - entry->asid =3D (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; - entry->attr =3D pte & 0xf; -} - -void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) -{ - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - CPUState *cs =3D CPU(cpu); - xtensa_tlb_entry *entry =3D xtensa_tlb_get_entry(env, dtlb, wi, ei); - - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - if (entry->variable) { - if (entry->asid) { - tlb_flush_page(cs, entry->vaddr); - } - xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); - tlb_flush_page(cs, entry->vaddr); - } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s %d, %d, %d trying to set im= mutable entry\n", - __func__, dtlb, wi, ei); - } - } else { - tlb_flush_page(cs, entry->vaddr); - if (xtensa_option_enabled(env->config, - XTENSA_OPTION_REGION_TRANSLATION)) { - entry->paddr =3D pte & REGION_PAGE_MASK; - } - entry->attr =3D pte & 0xf; - } -} - -void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dt= lb) -{ - uint32_t vpn; - uint32_t wi; - uint32_t ei; - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); -} - - void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) { uint32_t change =3D v ^ env->sregs[IBREAKENABLE]; --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547452416101924.4704698783331; Sun, 13 Jan 2019 23:53:36 -0800 (PST) Received: from localhost ([127.0.0.1]:54932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix3v-0000c8-3m for importer@patchew.org; Mon, 14 Jan 2019 02:53:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix07-0006VL-VH for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gix06-000208-0M for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:39 -0500 Received: from mail-lf1-x12c.google.com ([2a00:1450:4864:20::12c]:37914) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gix05-0001tT-IE for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:37 -0500 Received: by mail-lf1-x12c.google.com with SMTP id a8so14858430lfk.5 for ; Sun, 13 Jan 2019 23:49:28 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net. 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7o2+rPl5Z70qU5QXfhteUVbbnuxK3zpYF6FYfiInFgk=; b=ph2d3zTxeKuRzgyBHEf+IcOI2UJ1OK3XkmN/gsFV13ZJnEcFvy4bmpv7fhJQhQUulN 5xOVYbcFqzb+1XAQq8QtP1oGmV+Wig5uARNodRis+OsMVHNB4Y8BrlkoEymJjh0ytmJz /19loMbJvcsv1LpX9rrE1Ty6xWGgqI46bZI0X7WW8ZDXPK+vSPhAz+7/rD06r38e6iGg Iw84kdd+ugYY0x/6xdR+VxtLSNyd8rWK7gBma88f3ZKERIMBZ1MX8AAWpPE4qu6qYyta 22q2jk3l214P13hdboGtrPzQ/0jLvh0HIq4p8ZdgoFROuZhbDbtEPYoiWmgDF0rmoVXC 4vDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7o2+rPl5Z70qU5QXfhteUVbbnuxK3zpYF6FYfiInFgk=; b=aeWxMqYGa8QITU+I0OOtD6KLtet3a1GMcxI+FNxIS0j02kLcBbwnDhUmwLk/quXkir ZbZCrfmtX5LzBsPItbsCBMPZVtw7m+nXZS7bzvI7Fb9BMm0gZePejGh0kjUEiZq9d4ps aFsVUi3M5O9DLbE411LrtwhM14/axKK54oDgSSCC7nhGkT5YejvILSDvlpo+Qy84R5OK 7vKevJSZsueuXPMEDcHA7ucDXH4um/6xCTMfTbyGxyy6yGlJMPEAMmX1X01oZOUn18lP tCAvc0O7wZs+bRHhN7XITvpEnduyl5N8aOB0+FVvWHFQQrNGhNQ2mTeQHQYIgxRG8d7a k49w== X-Gm-Message-State: AJcUukeBIQ4DhRG+7W0bQ4rIi6hcG3cYepNzMHfSuJXEzc8h1Oi4bTmk 9sKEDhRq5nWPG98Mkpv6gtoScEHpJLM= X-Google-Smtp-Source: ALg8bN6mOsVQB/8/X/b0ZpTI4Rvh1OjVumzMkhVNY0f3rBMt7QXM8T/e1Kv7hQc0izmivXDqQrsp1g== X-Received: by 2002:a19:d04d:: with SMTP id h74mr12108378lfg.52.1547452166895; Sun, 13 Jan 2019 23:49:26 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:52 -0800 Message-Id: <20190114074855.16891-5-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::12c Subject: [Qemu-devel] [PATCH 4/7] target/xtensa: extract debug helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move HELPER functions related to native debugging from op_helper.c to dbg_helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/dbg_helper.c | 129 ++++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/op_helper.c | 92 ------------------------------- 3 files changed, 130 insertions(+), 92 deletions(-) create mode 100644 target/xtensa/dbg_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index b2c720b2df9b..cfd33ba1d951 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -7,6 +7,7 @@ obj-y +=3D core-test_kc705_be.o obj-$(CONFIG_SOFTMMU) +=3D monitor.o xtensa-semi.o obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o +obj-$(CONFIG_SOFTMMU) +=3D dbg_helper.o obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o obj-$(CONFIG_SOFTMMU) +=3D mmu_helper.o diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c new file mode 100644 index 000000000000..cd8fbd653a1a --- /dev/null +++ b/target/xtensa/dbg_helper.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "exec/address-spaces.h" + +static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) +{ + uint32_t paddr; + uint32_t page_size; + unsigned access; + int ret =3D xtensa_get_physical_addr(env, false, vaddr, 2, 0, + &paddr, &page_size, &access); + if (ret =3D=3D 0) { + tb_invalidate_phys_addr(&address_space_memory, paddr, + MEMTXATTRS_UNSPECIFIED); + } +} + +void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) +{ + uint32_t change =3D v ^ env->sregs[IBREAKENABLE]; + unsigned i; + + for (i =3D 0; i < env->config->nibreak; ++i) { + if (change & (1 << i)) { + tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); + } + } + env->sregs[IBREAKENABLE] =3D v & ((1 << env->config->nibreak) - 1); +} + +void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) +{ + if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != =3D v) { + tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); + tb_invalidate_virtual_addr(env, v); + } + env->sregs[IBREAKA + i] =3D v; +} + +static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, + uint32_t dbreakc) +{ + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + uint32_t mask =3D dbreakc | ~DBREAKC_MASK; + + if (env->cpu_watchpoint[i]) { + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); + } + if (dbreakc & DBREAKC_SB) { + flags |=3D BP_MEM_WRITE; + } + if (dbreakc & DBREAKC_LB) { + flags |=3D BP_MEM_READ; + } + /* contiguous mask after inversion is one less than some power of 2 */ + if ((~mask + 1) & ~mask) { + qemu_log_mask(LOG_GUEST_ERROR, + "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); + /* cut mask after the first zero bit */ + mask =3D 0xffffffff << (32 - clo32(mask)); + } + if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, + flags, &env->cpu_watchpoint[i])) { + env->cpu_watchpoint[i] =3D NULL; + qemu_log_mask(LOG_GUEST_ERROR, + "Failed to set data breakpoint at 0x%08x/%d\n", + dbreaka & mask, ~mask + 1); + } +} + +void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) +{ + uint32_t dbreakc =3D env->sregs[DBREAKC + i]; + + if ((dbreakc & DBREAKC_SB_LB) && + env->sregs[DBREAKA + i] !=3D v) { + set_dbreak(env, i, v, dbreakc); + } + env->sregs[DBREAKA + i] =3D v; +} + +void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) +{ + if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { + if (v & DBREAKC_SB_LB) { + set_dbreak(env, i, env->sregs[DBREAKA + i], v); + } else { + if (env->cpu_watchpoint[i]) { + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); + env->cpu_watchpoint[i] =3D NULL; + } + } + } + env->sregs[DBREAKC + i] =3D v; +} diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 1d3d87012c4a..e13e686479db 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -93,19 +93,6 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, vaddr addr, addr); } =20 -static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) -{ - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret =3D xtensa_get_physical_addr(env, false, vaddr, 2, 0, - &paddr, &page_size, &access); - if (ret =3D=3D 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr, - MEMTXATTRS_UNSPECIFIED); - } -} - #endif =20 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) @@ -325,85 +312,6 @@ void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t = v) env->sregs[MEMCTL] =3D v & env->config->memctl_mask; } =20 -void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) -{ - uint32_t change =3D v ^ env->sregs[IBREAKENABLE]; - unsigned i; - - for (i =3D 0; i < env->config->nibreak; ++i) { - if (change & (1 << i)) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); - } - } - env->sregs[IBREAKENABLE] =3D v & ((1 << env->config->nibreak) - 1); -} - -void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) -{ - if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != =3D v) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); - tb_invalidate_virtual_addr(env, v); - } - env->sregs[IBREAKA + i] =3D v; -} - -static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, - uint32_t dbreakc) -{ - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - uint32_t mask =3D dbreakc | ~DBREAKC_MASK; - - if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); - } - if (dbreakc & DBREAKC_SB) { - flags |=3D BP_MEM_WRITE; - } - if (dbreakc & DBREAKC_LB) { - flags |=3D BP_MEM_READ; - } - /* contiguous mask after inversion is one less than some power of 2 */ - if ((~mask + 1) & ~mask) { - qemu_log_mask(LOG_GUEST_ERROR, "DBREAKC mask is not contiguous: 0x= %08x\n", dbreakc); - /* cut mask after the first zero bit */ - mask =3D 0xffffffff << (32 - clo32(mask)); - } - if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, - flags, &env->cpu_watchpoint[i])) { - env->cpu_watchpoint[i] =3D NULL; - qemu_log_mask(LOG_GUEST_ERROR, "Failed to set data breakpoint at 0= x%08x/%d\n", - dbreaka & mask, ~mask + 1); - } -} - -void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) -{ - uint32_t dbreakc =3D env->sregs[DBREAKC + i]; - - if ((dbreakc & DBREAKC_SB_LB) && - env->sregs[DBREAKA + i] !=3D v) { - set_dbreak(env, i, v, dbreakc); - } - env->sregs[DBREAKA + i] =3D v; -} - -void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) -{ - if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) { - if (v & DBREAKC_SB_LB) { - set_dbreak(env, i, env->sregs[DBREAKA + i], v); - } else { - if (env->cpu_watchpoint[i]) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - - cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); - env->cpu_watchpoint[i] =3D NULL; - } - } - } - env->sregs[DBREAKC + i] =3D v; -} #endif =20 uint32_t HELPER(rer)(CPUXtensaState *env, uint32_t addr) --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547452551402786.7015823035767; Sun, 13 Jan 2019 23:55:51 -0800 (PST) Received: from localhost ([127.0.0.1]:55481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix5s-0001yn-E2 for importer@patchew.org; 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hDd7+1WVhHSP3atBUucRfi7XjQcHIYxNX+PrYAJ7u/s=; b=SMlyTYVrQIvHpQ6oZwRHZ9Rbhx6LzC2MEUVjTjIME2fRbuDdGFlx/TG0g1y4/6r1LD PRcoL78E8R6Fe6Sf1yljMMxgtFgYzs6uVCrS0x1oqrroLO9W3uW4cO6boIxb7aukdR5U FprV0QEt7qmJUgd9L6eVtrVF2hcpKgDyYhjb+1NZOxySILStqWlKTHUS/kAtuSK7LsJJ 6y3KduMdid2cepTvIsZ5+UW9GaMde8dGDV28kvSJyni6MvGlvPoRS3VzGBVFO39W+ax6 CEL2OD9vaGQSuHl71IjitYKHHU9xVoFZsRQEDDiDvLbymDbpJiCShIjgOwudFuOXzvMY rx+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hDd7+1WVhHSP3atBUucRfi7XjQcHIYxNX+PrYAJ7u/s=; b=jyl6PQIjfN6S1bn1Lo5pPAeSeQMTHUsNNxL4OYyoJnaGzrxYs36WeUIwYJlcggdP3N s15ldzednSucAg59RpOyhk9a62T9FEsfpMUGwLtNUqaCspl9Aam2iuc/rKNpBE5+SbPy 9JrZ4t1t4iIkR09geeNgh0+INrvp1O1wY6wd9BVa9aY1yvcXtv07PpcMX/fRasFfjA0V St4bAQIYd+EJ68yb4pa1NvlSfBQoQB/3M069VcALxpvIWeib0W4qB7RO52kSFhtBc1OQ pUGK423xJ1h5kapKlAeV41DBtF4O85tWG9VYQMVCfBJ01XgOCu0vfyJS6m7ceM7zM3n1 rT2Q== X-Gm-Message-State: AJcUukeBcb86PN86DsLynPYDrA3Cmy4WQnJeL3/P4m1n4hpBm+zJ2fYK xjiGQDrWjx9GKOz5p1dy/FfHbeU9aT4= X-Google-Smtp-Source: ALg8bN7mvJ4buqIjND6qA86mcMo9NVkwD/PYmuF3TIXDqxIIFQCoANfrnbSPjcNP/IZI+rSdZWBOFw== X-Received: by 2002:a19:1994:: with SMTP id 142mr13361856lfz.134.1547452169223; Sun, 13 Jan 2019 23:49:29 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:53 -0800 Message-Id: <20190114074855.16891-6-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::143 Subject: [Qemu-devel] [PATCH 5/7] target/xtensa: extract interrupt and exception helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move helper functions related to interrupt and exception handling from op_helper.c and helper.c to exc_helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/Makefile.objs | 1 + target/xtensa/exc_helper.c | 258 ++++++++++++++++++++++++++++++++++++++++= ++++ target/xtensa/helper.c | 127 ---------------------- target/xtensa/op_helper.c | 93 ---------------- 4 files changed, 259 insertions(+), 220 deletions(-) create mode 100644 target/xtensa/exc_helper.c diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index cfd33ba1d951..808f7e3fceb8 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -8,6 +8,7 @@ obj-$(CONFIG_SOFTMMU) +=3D monitor.o xtensa-semi.o obj-y +=3D xtensa-isa.o obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-$(CONFIG_SOFTMMU) +=3D dbg_helper.o +obj-y +=3D exc_helper.o obj-y +=3D fpu_helper.o obj-y +=3D gdbstub.o obj-$(CONFIG_SOFTMMU) +=3D mmu_helper.o diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c new file mode 100644 index 000000000000..371a32ba5ad9 --- /dev/null +++ b/target/xtensa/exc_helper.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are = met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in t= he + * documentation and/or other materials provided with the distributi= on. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote produ= cts + * derived from this software without specific prior written permiss= ion. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS= IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, T= HE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP= OSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMA= GES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV= ICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED= AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR T= ORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE O= F THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" + +void HELPER(exception)(CPUXtensaState *env, uint32_t excp) +{ + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + + cs->exception_index =3D excp; + if (excp =3D=3D EXCP_YIELD) { + env->yield_needed =3D 0; + } + if (excp =3D=3D EXCP_DEBUG) { + env->exception_taken =3D 0; + } + cpu_loop_exit(cs); +} + +void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) +{ + uint32_t vector; + + env->pc =3D pc; + if (env->sregs[PS] & PS_EXCM) { + if (env->config->ndepc) { + env->sregs[DEPC] =3D pc; + } else { + env->sregs[EPC1] =3D pc; + } + vector =3D EXC_DOUBLE; + } else { + env->sregs[EPC1] =3D pc; + vector =3D (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; + } + + env->sregs[EXCCAUSE] =3D cause; + env->sregs[PS] |=3D PS_EXCM; + + HELPER(exception)(env, vector); +} + +void HELPER(exception_cause_vaddr)(CPUXtensaState *env, + uint32_t pc, uint32_t cause, uint32_t v= addr) +{ + env->sregs[EXCVADDR] =3D vaddr; + HELPER(exception_cause)(env, pc, cause); +} + +void debug_exception_env(CPUXtensaState *env, uint32_t cause) +{ + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + HELPER(debug_exception)(env, env->pc, cause); + } +} + +void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) +{ + unsigned level =3D env->config->debug_level; + + env->pc =3D pc; + env->sregs[DEBUGCAUSE] =3D cause; + env->sregs[EPC1 + level - 1] =3D pc; + env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; + env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | + (level << PS_INTLEVEL_SHIFT); + HELPER(exception)(env, EXC_DEBUG); +} + +#ifndef CONFIG_USER_ONLY + +void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) +{ + CPUState *cpu; + + env->pc =3D pc; + env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | + (intlevel << PS_INTLEVEL_SHIFT); + + qemu_mutex_lock_iothread(); + check_interrupts(env); + qemu_mutex_unlock_iothread(); + + if (env->pending_irq_level) { + cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); + return; + } + + cpu =3D CPU(xtensa_env_get_cpu(env)); + cpu->halted =3D 1; + HELPER(exception)(env, EXCP_HLT); +} + +void HELPER(check_interrupts)(CPUXtensaState *env) +{ + qemu_mutex_lock_iothread(); + check_interrupts(env); + qemu_mutex_unlock_iothread(); +} + +static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) +{ + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_RELOCATABLE_VECTOR)) { + return vector - env->config->vecbase + env->sregs[VECBASE]; + } else { + return vector; + } +} + +/*! + * Handle penging IRQ. + * For the high priority interrupt jump to the corresponding interrupt vec= tor. + * For the level-1 interrupt convert it to either user, kernel or double + * exception with the 'level-1 interrupt' exception cause. + */ +static void handle_interrupt(CPUXtensaState *env) +{ + int level =3D env->pending_irq_level; + + if (level > xtensa_get_cintlevel(env) && + level <=3D env->config->nlevel && + (env->config->level_mask[level] & + env->sregs[INTSET] & + env->sregs[INTENABLE])) { + CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); + + if (level > 1) { + env->sregs[EPC1 + level - 1] =3D env->pc; + env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; + env->sregs[PS] =3D + (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; + env->pc =3D relocated_vector(env, + env->config->interrupt_vector[level= ]); + } else { + env->sregs[EXCCAUSE] =3D LEVEL1_INTERRUPT_CAUSE; + + if (env->sregs[PS] & PS_EXCM) { + if (env->config->ndepc) { + env->sregs[DEPC] =3D env->pc; + } else { + env->sregs[EPC1] =3D env->pc; + } + cs->exception_index =3D EXC_DOUBLE; + } else { + env->sregs[EPC1] =3D env->pc; + cs->exception_index =3D + (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; + } + env->sregs[PS] |=3D PS_EXCM; + } + env->exception_taken =3D 1; + } +} + +/* Called from cpu_handle_interrupt with BQL held */ +void xtensa_cpu_do_interrupt(CPUState *cs) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + if (cs->exception_index =3D=3D EXC_IRQ) { + qemu_log_mask(CPU_LOG_INT, + "%s(EXC_IRQ) level =3D %d, cintlevel =3D %d, " + "pc =3D %08x, a0 =3D %08x, ps =3D %08x, " + "intset =3D %08x, intenable =3D %08x, " + "ccount =3D %08x\n", + __func__, env->pending_irq_level, + xtensa_get_cintlevel(env), + env->pc, env->regs[0], env->sregs[PS], + env->sregs[INTSET], env->sregs[INTENABLE], + env->sregs[CCOUNT]); + handle_interrupt(env); + } + + switch (cs->exception_index) { + case EXC_WINDOW_OVERFLOW4: + case EXC_WINDOW_UNDERFLOW4: + case EXC_WINDOW_OVERFLOW8: + case EXC_WINDOW_UNDERFLOW8: + case EXC_WINDOW_OVERFLOW12: + case EXC_WINDOW_UNDERFLOW12: + case EXC_KERNEL: + case EXC_USER: + case EXC_DOUBLE: + case EXC_DEBUG: + qemu_log_mask(CPU_LOG_INT, "%s(%d) " + "pc =3D %08x, a0 =3D %08x, ps =3D %08x, ccount =3D %= 08x\n", + __func__, cs->exception_index, + env->pc, env->regs[0], env->sregs[PS], + env->sregs[CCOUNT]); + if (env->config->exception_vector[cs->exception_index]) { + uint32_t vector; + + vector =3D env->config->exception_vector[cs->exception_index]; + env->pc =3D relocated_vector(env, vector); + env->exception_taken =3D 1; + } else { + qemu_log_mask(CPU_LOG_INT, + "%s(pc =3D %08x) bad exception_index: %d\n", + __func__, env->pc, cs->exception_index); + } + break; + + case EXC_IRQ: + break; + + default: + qemu_log("%s(pc =3D %08x) unknown exception_index: %d\n", + __func__, env->pc, cs->exception_index); + break; + } + check_interrupts(env); +} +#else +void xtensa_cpu_do_interrupt(CPUState *cs) +{ +} +#endif + +bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + cs->exception_index =3D EXC_IRQ; + xtensa_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index c344241bd06e..2f1dec5c63e9 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -169,133 +169,6 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fp= rintf) } } =20 -#ifndef CONFIG_USER_ONLY - -static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) -{ - if (xtensa_option_enabled(env->config, - XTENSA_OPTION_RELOCATABLE_VECTOR)) { - return vector - env->config->vecbase + env->sregs[VECBASE]; - } else { - return vector; - } -} - -/*! - * Handle penging IRQ. - * For the high priority interrupt jump to the corresponding interrupt vec= tor. - * For the level-1 interrupt convert it to either user, kernel or double - * exception with the 'level-1 interrupt' exception cause. - */ -static void handle_interrupt(CPUXtensaState *env) -{ - int level =3D env->pending_irq_level; - - if (level > xtensa_get_cintlevel(env) && - level <=3D env->config->nlevel && - (env->config->level_mask[level] & - env->sregs[INTSET] & - env->sregs[INTENABLE])) { - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - - if (level > 1) { - env->sregs[EPC1 + level - 1] =3D env->pc; - env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; - env->sregs[PS] =3D - (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; - env->pc =3D relocated_vector(env, - env->config->interrupt_vector[level]); - } else { - env->sregs[EXCCAUSE] =3D LEVEL1_INTERRUPT_CAUSE; - - if (env->sregs[PS] & PS_EXCM) { - if (env->config->ndepc) { - env->sregs[DEPC] =3D env->pc; - } else { - env->sregs[EPC1] =3D env->pc; - } - cs->exception_index =3D EXC_DOUBLE; - } else { - env->sregs[EPC1] =3D env->pc; - cs->exception_index =3D - (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; - } - env->sregs[PS] |=3D PS_EXCM; - } - env->exception_taken =3D 1; - } -} - -/* Called from cpu_handle_interrupt with BQL held */ -void xtensa_cpu_do_interrupt(CPUState *cs) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - if (cs->exception_index =3D=3D EXC_IRQ) { - qemu_log_mask(CPU_LOG_INT, - "%s(EXC_IRQ) level =3D %d, cintlevel =3D %d, " - "pc =3D %08x, a0 =3D %08x, ps =3D %08x, " - "intset =3D %08x, intenable =3D %08x, " - "ccount =3D %08x\n", - __func__, env->pending_irq_level, xtensa_get_cintlevel(env= ), - env->pc, env->regs[0], env->sregs[PS], - env->sregs[INTSET], env->sregs[INTENABLE], - env->sregs[CCOUNT]); - handle_interrupt(env); - } - - switch (cs->exception_index) { - case EXC_WINDOW_OVERFLOW4: - case EXC_WINDOW_UNDERFLOW4: - case EXC_WINDOW_OVERFLOW8: - case EXC_WINDOW_UNDERFLOW8: - case EXC_WINDOW_OVERFLOW12: - case EXC_WINDOW_UNDERFLOW12: - case EXC_KERNEL: - case EXC_USER: - case EXC_DOUBLE: - case EXC_DEBUG: - qemu_log_mask(CPU_LOG_INT, "%s(%d) " - "pc =3D %08x, a0 =3D %08x, ps =3D %08x, ccount =3D %08x\n", - __func__, cs->exception_index, - env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); - if (env->config->exception_vector[cs->exception_index]) { - env->pc =3D relocated_vector(env, - env->config->exception_vector[cs->exception_index]); - env->exception_taken =3D 1; - } else { - qemu_log_mask(CPU_LOG_INT, "%s(pc =3D %08x) bad exception_inde= x: %d\n", - __func__, env->pc, cs->exception_index); - } - break; - - case EXC_IRQ: - break; - - default: - qemu_log("%s(pc =3D %08x) unknown exception_index: %d\n", - __func__, env->pc, cs->exception_index); - break; - } - check_interrupts(env); -} -#else -void xtensa_cpu_do_interrupt(CPUState *cs) -{ -} -#endif - -bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - cs->exception_index =3D EXC_IRQ; - xtensa_cpu_do_interrupt(cs); - return true; - } - return false; -} - #ifdef CONFIG_USER_ONLY =20 int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int= rw, diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index e13e686479db..d3e61e22fe82 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -95,70 +95,6 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, vaddr addr, =20 #endif =20 -void HELPER(exception)(CPUXtensaState *env, uint32_t excp) -{ - CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); - - cs->exception_index =3D excp; - if (excp =3D=3D EXCP_YIELD) { - env->yield_needed =3D 0; - } - if (excp =3D=3D EXCP_DEBUG) { - env->exception_taken =3D 0; - } - cpu_loop_exit(cs); -} - -void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) -{ - uint32_t vector; - - env->pc =3D pc; - if (env->sregs[PS] & PS_EXCM) { - if (env->config->ndepc) { - env->sregs[DEPC] =3D pc; - } else { - env->sregs[EPC1] =3D pc; - } - vector =3D EXC_DOUBLE; - } else { - env->sregs[EPC1] =3D pc; - vector =3D (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; - } - - env->sregs[EXCCAUSE] =3D cause; - env->sregs[PS] |=3D PS_EXCM; - - HELPER(exception)(env, vector); -} - -void HELPER(exception_cause_vaddr)(CPUXtensaState *env, - uint32_t pc, uint32_t cause, uint32_t vaddr) -{ - env->sregs[EXCVADDR] =3D vaddr; - HELPER(exception_cause)(env, pc, cause); -} - -void debug_exception_env(CPUXtensaState *env, uint32_t cause) -{ - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - HELPER(debug_exception)(env, env->pc, cause); - } -} - -void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t ca= use) -{ - unsigned level =3D env->config->debug_level; - - env->pc =3D pc; - env->sregs[DEBUGCAUSE] =3D cause; - env->sregs[EPC1 + level - 1] =3D pc; - env->sregs[EPS2 + level - 2] =3D env->sregs[PS]; - env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM | - (level << PS_INTLEVEL_SHIFT); - HELPER(exception)(env, EXC_DEBUG); -} - void HELPER(dump_state)(CPUXtensaState *env) { XtensaCPU *cpu =3D xtensa_env_get_cpu(env); @@ -168,28 +104,6 @@ void HELPER(dump_state)(CPUXtensaState *env) =20 #ifndef CONFIG_USER_ONLY =20 -void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) -{ - CPUState *cpu; - - env->pc =3D pc; - env->sregs[PS] =3D (env->sregs[PS] & ~PS_INTLEVEL) | - (intlevel << PS_INTLEVEL_SHIFT); - - qemu_mutex_lock_iothread(); - check_interrupts(env); - qemu_mutex_unlock_iothread(); - - if (env->pending_irq_level) { - cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); - return; - } - - cpu =3D CPU(xtensa_env_get_cpu(env)); - cpu->halted =3D 1; - HELPER(exception)(env, EXCP_HLT); -} - void HELPER(update_ccount)(CPUXtensaState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -222,13 +136,6 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint= 32_t i) env->yield_needed =3D 1; } =20 -void HELPER(check_interrupts)(CPUXtensaState *env) -{ - qemu_mutex_lock_iothread(); - check_interrupts(env); - qemu_mutex_unlock_iothread(); -} - /*! * Check vaddr accessibility/cache attributes and raise an exception if * specified by the ATOMCTL SR. --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547452301788844.945751434111; Sun, 13 Jan 2019 23:51:41 -0800 (PST) Received: from localhost ([127.0.0.1]:54420 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix24-0007gD-Ru for importer@patchew.org; Mon, 14 Jan 2019 02:51:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44740) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix09-0006VP-S4 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gix08-00022H-BR for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:41 -0500 Received: from mail-lj1-x241.google.com ([2a00:1450:4864:20::241]:35598) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gix08-0001vs-49 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:40 -0500 Received: by mail-lj1-x241.google.com with SMTP id x85-v6so18121425ljb.2 for ; Sun, 13 Jan 2019 23:49:32 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net. 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fcWfQII4EbYu0Efv6TsrxR3P3jqWehDBl02qTyAn8uw=; b=tnp3JJLy4rWyvsFrWLPCLIl1W3+PBlxkl4rbmyiH3ZABAbEMpmey2q0aXrhzcB8TmE SsxTSvG6ba6Iw3XRI44kFX7iaACsPyPdqUuHEJTCzfJNW50QFTSHFX6vkSnHICa9kWfr BCXHBj6X+pGMmeJiYzPgD0boMoMH8zcqQu+CKraEQTCRX4RSAIoPNo1Db2T/5Pb7Hq6F p242tyGceZkyhYxF5x+Ct8uQWAhIhcOLSdFBUSAqTNDJoUY0Njzzd67rtHeZmp3hzemv QuTOhePmo10zNM5+/I4dHZCvjLAdBpL+eVwQzj9XIACRtWgf4lHmjiUY8942EkgjP0oW wwBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fcWfQII4EbYu0Efv6TsrxR3P3jqWehDBl02qTyAn8uw=; b=qZATys+r2xcFQrmSYIOItaa4h/gEnRvdkOqImgELSp8kKBSG0LZ5SNjYVsEg1DeaT9 kYFXSZNxXmtMblVkst3AB9LCRroPkl0xuTcYpFkX2o6I8jxbmHvShExR06Yh1KYqyXPJ +/buRF8tZoYmWXj9OvZcZqwciENeC0RKU/ISuET+rjSpgYiCX4kEpz8Xo7YYDAg7NMnr Qx8s6NGRx5PsEUWUjWOGz83BFfdF7EXogTFCTAwUx639QGXkt1Nfvwdz82HDCy/fKWX8 BhpDacWi9l4wS4RMVYxFEvME4ZGsLg118w4QkiHJywRV1xrzGpeg+l0lIUNFZpb5CXYM lVIw== X-Gm-Message-State: AJcUukdCEeDl0AP5D9tMbtsEGBZagYod46LUlbPvM0SHBDST+lt5KJY8 lodUf2g915Ehl8IBQxMB9jbJz44NBMQ= X-Google-Smtp-Source: ALg8bN41YWWRNTb/La0b5AxkCmz4q6rjdraUNMwHR6z1cExsxWi+HAYeNkyaJFXbt92xjMDcpWBPfg== X-Received: by 2002:a2e:9b84:: with SMTP id z4-v6mr13528353lji.93.1547452171305; Sun, 13 Jan 2019 23:49:31 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:54 -0800 Message-Id: <20190114074855.16891-7-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::241 Subject: [Qemu-devel] [PATCH 6/7] target/xtensa: drop dump_state helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Drop unused helper dump_state from op_helper.c Signed-off-by: Max Filippov --- target/xtensa/helper.h | 1 - target/xtensa/op_helper.c | 11 ----------- 2 files changed, 12 deletions(-) diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 2ebba0b2c2bf..89eb97e26514 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -15,7 +15,6 @@ DEF_HELPER_2(movsp, void, env, i32) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(simcall, void, env) #endif -DEF_HELPER_1(dump_state, void, env) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_3(waiti, void, env, i32, i32) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index d3e61e22fe82..b0ef828f9ae5 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -93,17 +93,6 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, vaddr addr, addr); } =20 -#endif - -void HELPER(dump_state)(CPUXtensaState *env) -{ - XtensaCPU *cpu =3D xtensa_env_get_cpu(env); - - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); -} - -#ifndef CONFIG_USER_ONLY - void HELPER(update_ccount)(CPUXtensaState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); --=20 2.11.0 From nobody Sun May 5 20:20:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547452419044816.8899468312757; Sun, 13 Jan 2019 23:53:39 -0800 (PST) Received: from localhost ([127.0.0.1]:54949 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix3y-0000eG-2P for importer@patchew.org; Mon, 14 Jan 2019 02:53:38 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44727) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gix09-0006VO-3e for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gix07-00021n-W8 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:41 -0500 Received: from mail-lj1-x242.google.com ([2a00:1450:4864:20::242]:35599) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gix06-0001xB-56 for qemu-devel@nongnu.org; Mon, 14 Jan 2019 02:49:39 -0500 Received: by mail-lj1-x242.google.com with SMTP id x85-v6so18121499ljb.2 for ; Sun, 13 Jan 2019 23:49:34 -0800 (PST) Received: from octofox.hsd1.ca.comcast.net. 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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id g17sm16181570lfg.78.2019.01.13.23.49.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jan 2019 23:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ydqil1w8iCE5YBsDMBM3q0kPbxIVe6yKVnFnE2WocKs=; b=h+9QZQeaiBhJ32tXFLzsb4p4jvlYNir+c4cvylHyvfeK4p0G1MYoy07ZpnRChgG42F qxiwLa3kBpsbVMf4CqrmyFn5FzgMc/WY6AKPdMfB8QxIAck7Xnjv9t+KcmxwHd3WPxJS nxz6Ha0But+a3OQLyECwPhuoSCvShAQQokrA9nXczKid2DP+SNZd8tCpOxVrMnA5a/kQ +1/l0FqLiStHJBR9JrQw2MeE1wHGPMACxb1MXUDFtzgJl27B1L1T68tZ3RaP6kwhyhwY 2nFMXVRS4e3IjjYXRaCbdNQTHJNzapNyt2oNUUvRHTCLV1HMMwmwNIxIDVPbjbkd6nw7 FpLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ydqil1w8iCE5YBsDMBM3q0kPbxIVe6yKVnFnE2WocKs=; b=izreNddOfdkLrdo3CQEY/Zi0ty0b6p5NOeZAlhf4ewVHk1FRyV6qtF/BxUlobpwmbC tUACUMLP6sKSpEUoi8w5Ol1/qsV6CWgNOIk3pzFTe1pLJ0BhIdIlc0FeMoYDZKISn+zp Y04xPOazGCO8BspjnMArkrg0EMbo1D/I9Ex6J9wgHzLIDIUv+FmtdSOvoWpwENziNO2i Gaky7/EQQrYa89ZkFb5HU600FkBccJ3odWVGwNas/sdiZCgMjBRpK4Mmsup6bpSosd3j WD+S03wpaSjMnrYXcrIqanctS3ZsWjWE34ozv3t8+ShyU2bg6MuXE0IBAzhU20gv6GCr uR/Q== X-Gm-Message-State: AJcUukd0Rd8M65G6U1pnT0q4PsCZr0JGX8rCbjMUMNio9MJ2Xr4v0TVy qID4dE/ONKJfQnCygjXgcIJGgsQC9zY= X-Google-Smtp-Source: ALg8bN4yNxzFAy0vcWWHexCAToPZ/Sx9KFuqySQG+/L0ZMhkcRwax1WLSNqi68SPbGrYJMi0y597NA== X-Received: by 2002:a2e:974a:: with SMTP id f10-v6mr15110638ljj.61.1547452173371; Sun, 13 Jan 2019 23:49:33 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 13 Jan 2019 23:48:55 -0800 Message-Id: <20190114074855.16891-8-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190114074855.16891-1-jcmvbkbc@gmail.com> References: <20190114074855.16891-1-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH 7/7] target/xtensa: move non-HELPER functions to helper.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move remaining non-HELPER functions from op_helper.c to helper.c. No functional changes. Signed-off-by: Max Filippov --- target/xtensa/helper.c | 61 +++++++++++++++++++++++++++++++++++++++++++= +--- target/xtensa/op_helper.c | 56 ------------------------------------------- 2 files changed, 58 insertions(+), 59 deletions(-) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2f1dec5c63e9..323c47a7fb54 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,10 +29,8 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "exec/helper-proto.h" #include "qemu/host-utils.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif =20 static struct XtensaConfigList *xtensa_cores; =20 @@ -188,6 +186,63 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int size, int rw, =20 #else =20 +void xtensa_cpu_do_unaligned_access(CPUState *cs, + vaddr addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTI= ON) && + !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) { + cpu_restore_state(CPU(cpu), retaddr, true); + HELPER(exception_cause_vaddr)(env, + env->pc, LOAD_STORE_ALIGNMENT_CAUSE, + addr); + } +} + +void tlb_fill(CPUState *cs, target_ulong vaddr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + uint32_t paddr; + uint32_t page_size; + unsigned access; + int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, + &paddr, &page_size, &access); + + qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", + __func__, vaddr, access_type, mmu_idx, paddr, ret); + + if (ret =3D=3D 0) { + tlb_set_page(cs, + vaddr & TARGET_PAGE_MASK, + paddr & TARGET_PAGE_MASK, + access, mmu_idx, page_size); + } else { + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); + } +} + +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, + unsigned size, MMUAccessType access_= type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t reta= ddr) +{ + XtensaCPU *cpu =3D XTENSA_CPU(cs); + CPUXtensaState *env =3D &cpu->env; + + cpu_restore_state(cs, retaddr, true); + HELPER(exception_cause_vaddr)(env, env->pc, + access_type =3D=3D MMU_INST_FETCH ? + INSTR_PIF_ADDR_ERROR_CAUSE : + LOAD_STORE_PIF_ADDR_ERROR_CAUSE, + addr); +} + void xtensa_runstall(CPUXtensaState *env, bool runstall) { CPUState *cpu =3D CPU(xtensa_env_get_cpu(env)); diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index b0ef828f9ae5..1865f46c4b5f 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -37,62 +37,6 @@ =20 #ifndef CONFIG_USER_ONLY =20 -void xtensa_cpu_do_unaligned_access(CPUState *cs, - vaddr addr, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTI= ON) && - !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT= )) { - cpu_restore_state(CPU(cpu), retaddr, true); - HELPER(exception_cause_vaddr)(env, - env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr); - } -} - -void tlb_fill(CPUState *cs, target_ulong vaddr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret =3D xtensa_get_physical_addr(env, true, vaddr, access_type, mm= u_idx, - &paddr, &page_size, &access); - - qemu_log_mask(CPU_LOG_MMU, "%s(%08x, %d, %d) -> %08x, ret =3D %d\n", - __func__, vaddr, access_type, mmu_idx, paddr, ret); - - if (ret =3D=3D 0) { - tlb_set_page(cs, - vaddr & TARGET_PAGE_MASK, - paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); - } else { - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr); - } -} - -void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, - unsigned size, MMUAccessType access_= type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t reta= ddr) -{ - XtensaCPU *cpu =3D XTENSA_CPU(cs); - CPUXtensaState *env =3D &cpu->env; - - cpu_restore_state(cs, retaddr, true); - HELPER(exception_cause_vaddr)(env, env->pc, - access_type =3D=3D MMU_INST_FETCH ? - INSTR_PIF_ADDR_ERROR_CAUSE : - LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - addr); -} - void HELPER(update_ccount)(CPUXtensaState *env) { uint64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); --=20 2.11.0