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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 3 ++ target/arm/mte_helper.c | 34 ++++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 87 insertions(+), 23 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7a6051fdab..47577207b2 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env,= i64) =20 DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..a5a249b001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,7 @@ static inline bool allocation_tag_access_enabled(CPUA= RMState *env, int el, return sctlr !=3D 0; } =20 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 1878393fc4..e2b1a5dd40 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -163,3 +163,37 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, ui= nt64_t rm) } return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D env->cp15.gcr_el1; + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<=3D LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D env->cp15.gcr_el1; + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<=3D LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b0349bffc4..879d6b8d46 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3652,7 +3652,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_= t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3663,10 +3665,10 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) bool setflags =3D extract32(insn, 29, 1); bool sub_op =3D extract32(insn, 30, 1); bool is_64bit =3D extract32(insn, 31, 1); + bool is_tag =3D false; =20 TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); TCGv_i64 tcg_rd =3D setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; =20 switch (shift) { case 0x0: @@ -3674,35 +3676,58 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) case 0x1: imm <<=3D 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag =3D true; + break; default: + do_unallocated: unallocated_encoding(s); return; } =20 - tcg_result =3D tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm =3D tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset =3D tcg_const_i32(imm & 15); + TCGv_i32 offset =3D tcg_const_i32(imm >> 6); =20 - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; =20 - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result =3D tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm =3D tcg_const_i64(imm); + tcg_result =3D new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } =20 /* The input should be a value in the bottom e bits (with higher --=20 2.17.2