From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547428421822679.6820696096461; Sun, 13 Jan 2019 17:13:41 -0800 (PST) Received: from localhost ([127.0.0.1]:54769 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqou-0006f4-Nb for importer@patchew.org; Sun, 13 Jan 2019 20:13:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqmx-0005Qm-63 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqmv-0000jl-Dm for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:39 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:33754) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqmv-0000jB-69 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:37 -0500 Received: by mail-pf1-x431.google.com with SMTP id c123so9556077pfb.0 for ; Sun, 13 Jan 2019 17:11:37 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GKYYcx9lSQNdeFnnHFD9RFAln0nkgQrJyU8WcGcjUB4=; b=aU1oABrwydreQQTjx40Yb83hek+ISO4l0JipnPnTpP7mR5az/F58sRoQ1AgfppwJoD C3lBrzOrNKxBA8EUagRvnGM+E+TeOAvtRlWg80/PsyZ/tKnXRd5BbM4AGLAHIZCSX7sr TeLOubu03fNB1MSV2S3NiSU1H0/z95W5AUbqI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GKYYcx9lSQNdeFnnHFD9RFAln0nkgQrJyU8WcGcjUB4=; b=opD1Ok5Le2CwajAMXTky9sk1hpMh5gzWVz61eUCOvLKh4U7i3O08dcTvJYf0Zn7FwD AGHGCgG/1hI0x9Pn1b+20OMSSw5rHOTona/5FAsS9/U4Suv32hzM6VlfQA2Ja4FyA0Dj hcSQzfk4ujstzRlYusIx3mEwJoiFEw76Bl7wOyIjIAK9EPOWSggZ4LF0EmLPwy15d2O1 aQHVrHEpqHzDLvABqFIh8mk+1K0Zl2ef9pIsVM106PLs3lbTM+eGYtmaWDPYPh1IKMWK DeOs8KGtgAA189gczyQKSgAlE4/QSTcUeOKgxwiM1ENbgNcLUvWwkHMDZ5ixQtuWEHK1 FGaQ== X-Gm-Message-State: AJcUukf7giZ6XFLJfuLKBRY2aAB1vC+DUWeyJggFuhzA8kLRIa60lDdo p+k9nkt4Y2JZ5VKSqCCMPoQUkwZk5B3vAg== X-Google-Smtp-Source: ALg8bN4YGOxS1B32BZnik89lo+/EmpOVOK/wKTC73M5q7Ugh3Ew54eKZpnretXZ4wro+y8CF0SVydA== X-Received: by 2002:a62:da5a:: with SMTP id w26mr23334590pfl.106.1547428295676; Sun, 13 Jan 2019 17:11:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:06 +1100 Message-Id: <20190114011122.5995-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 13 +++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 18 +++++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++---------- target/arm/mte_helper.c | 32 +++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++- target/arm/Makefile.objs | 2 +- 8 files changed, 110 insertions(+), 13 deletions(-) create mode 100644 target/arm/mte_helper.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f2ff52f287..22163c9c3f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1164,6 +1164,7 @@ void pmccntr_sync(CPUARMState *env); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -1640,6 +1641,7 @@ FIELD(ID_AA64PFR0, SVE, 32, 4) =20 FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, MTE, 8, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -3003,6 +3005,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) =20 static inline bool bswap_code(bool sctlr_b) { @@ -3293,6 +3296,16 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *i= d) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) !=3D 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >=3D 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..fa4c371a47 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } =20 +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &=3D (el =3D=3D 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr !=3D 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 33af50a13f..5a101e1c6d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b7b639da5..038e52af4b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3465,22 +3465,31 @@ static void sctlr_write(CPUARMState *env, const ARM= CPRegInfo *ri, { ARMCPU *cpu =3D arm_env_get_cpu(env); =20 - if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &=3D ~SCTLR_M; } =20 - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 =3D=3D 6) { /* SCTLR_EL3 */ + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) !=3D value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } =20 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -13087,6 +13096,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (is_a64(env)) { ARMCPU *cpu =3D arm_env_get_cpu(env); uint64_t sctlr; + int tbid; =20 *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13095,7 +13105,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; =20 /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -13148,6 +13158,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, } flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags =3D FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc =3D env->regs[15]; flags =3D FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..a3226c44a4 --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,32 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) +{ + /* Only unchecked implemented so far. */ + return sextract64(ptr, 0, 55); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee6f71c98f..0286507bae 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -339,7 +339,13 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 s= rc) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + /* FIXME: SP+OFS is always unchecked. */ + if (s->tbid && s->mte_active) { + gen_helper_mte_check(clean, cpu_env, addr); + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } =20 @@ -14000,6 +14006,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pauth_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt =3D FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype =3D FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active =3D FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1a4fc06448..c86cb1af5c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y +=3D translate.o op_helper.o helper.o cpu.o obj-y +=3D neon_helper.o iwmmxt_helper.o vec_helper.o obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) +=3D pauth_helper.o +obj-$(TARGET_AARCH64) +=3D pauth_helper.o mte_helper.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o =20 --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index 038e52af4b..5a59fc4315 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9789,7 +9789,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el =3D regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; =20 /* Bit 55 is always between the two regions, and is canonical for @@ -9803,11 +9803,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState= *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi =3D tbid =3D hpd =3D false; + tbi =3D tbid =3D hpd =3D tcma =3D false; } else { tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); tbid =3D extract32(tcr, 29, 1); + tcma =3D extract32(tcr, 30, 1); } epd =3D false; } else if (!select) { @@ -9818,6 +9819,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); tbid =3D extract64(tcr, 51, 1); + tcma =3D extract64(tcr, 57, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; @@ -9827,6 +9829,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); tbid =3D extract64(tcr, 52, 1); + tcma =3D extract64(tcr, 58, 1); } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -9838,6 +9841,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *= env, uint64_t va, .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, + .tcma =3D tcma, .using16k =3D using16k, .using64k =3D using64k, }; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 03/17] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/translate.h | 11 ++++++++++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++++++ 4 files changed, 72 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22163c9c3f..c8b447e30a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -482,6 +482,11 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ +#ifdef TARGET_AARCH64 + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; +#endif } cp15; =20 struct { diff --git a/target/arm/translate.h b/target/arm/translate.h index 5a101e1c6d..a24757d3d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,17 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p =3D tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + /* Clear bits within PSTATE. */ static inline void clear_pstate_bits(uint32_t bits) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a59fc4315..df43deb0f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5132,6 +5132,48 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= al) +{ + env->pstate =3D (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] =3D { + { .name =3D "TFSRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 6, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 6, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name =3D "TFSR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 6, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name =3D "RGSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 5, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name =3D "GCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 0, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + REGINFO_SENTINEL +}; #endif =20 void register_cp_regs_for_features(ARMCPU *cpu) @@ -5923,6 +5965,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0286507bae..5c2577a9ac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1668,6 +1668,17 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_UPDATE; break; =20 + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PATCH 04/17] target/arm: Fill in helper_mte_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already covered by XXX. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index a3226c44a4..6f4bc0aa04 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,86 @@ #include "exec/helper-proto.h" =20 =20 +static int get_allocation_tag(CPUARMState *env, uint64_t ptr) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { - /* Only unchecked implemented so far. */ + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + ARMVAParameters param =3D aa64_va_parameters(env, ptr, mmu_idx, true); + int ptr_tag, mem_tag; + + /* + * If TBI is disabled, then the access is unchecked. + * While we filtered out TBI0=3D=3D0 && TBI1=3D=3D0 in cpu_get_tb_cpu_= state, + * we did not save separate bits for TBI0 !=3D TBI1. + */ + if (!param.tbi) { + /* Do not ignore the top byte. */ + return ptr; + } + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag =3D allocation_tag_from_addr(ptr); + if (param.tcma && ptr_tag =3D=3D 0) { + goto pass; + } + + /* + * If an access is made to an address that does not provide tag storag= e, + * the result is implementation defined (R0006). We choose to treat t= he + * access as unchecked. + * This is similar to MemAttr !=3D Tagged, which are also unchecked. + */ + mem_tag =3D get_allocation_tag(env, ptr); + if (mem_tag < 0) { + goto pass; + } + + /* If the tags do not match, the tag check operation fails. */ + if (ptr_tag !=3D mem_tag) { + int el =3D arm_current_el(env); + int tcf; + + /* Indicate the tag check fail, both async and sync reporting. */ + env->cp15.tfsr_el[el] |=3D 1 << param.select; + + if (el =3D=3D 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf =3D extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf =3D extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf =3D=3D 1) { + /* Tag check fail causes a synchronous exception. */ + CPUState *cs =3D ENV_GET_CPU(env); + + /* + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(cs, GETPC(), true); + env->exception.vaddress =3D ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el !=3D 0, 0, 0, 0, 0, 0= x11), + exception_target_el(env)); + } + } + + pass: + /* Unchecked, or tag check pass. Ignore the top byte. */ return sextract64(ptr, 0, 55); } --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547428650479787.5584186695704; Sun, 13 Jan 2019 17:17:30 -0800 (PST) Received: from localhost ([127.0.0.1]:55717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqsb-00018b-Bc for importer@patchew.org; Sun, 13 Jan 2019 20:17:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36924) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqn8-0005Xc-PX for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqn7-0000qL-Nk for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:50 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:33362) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqn7-0000pj-Gi for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:49 -0500 Received: by mail-pf1-x442.google.com with SMTP id c123so9556250pfb.0 for ; Sun, 13 Jan 2019 17:11:49 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bXhPStNSlDCbXnTGxtTMCZgmzW/jvr/X9ejRqXKxxc8=; b=OhsAcvJla5ivgOg7E4fLADjmRBnBo+0z8LJ0PcQjQHJHYQt+HnKdagZNaeIA8yDQEn x9Pf37WZRn2ZiihKTMKeMwdSuxJqvXjXC6cgLEnfL8TdxXFraE0m+x9wYPqvxNFlZSv6 dnsfPnsJNFEt7sfrwC46Q7O43z/7yOlv6Uwhs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bXhPStNSlDCbXnTGxtTMCZgmzW/jvr/X9ejRqXKxxc8=; b=HYxDXKapXbszfPf7xGE1vlqN6CQtrjBWjAMCV3+HivqXbl+RrU89jNPOzXr8lwhvaE xZFbZgSf4ctLxHVf+TJqGdOAcDv+R+BP/LLkHE3ddO2SXxiMmhXNcKGZ3u2B1uWdms08 2DpXVLqrLutRBuWmTkYl0/djqqmnnAhCNbpyg1KNm0A03qnweq9GHjeI1IEs8Cjv+m6E g9ne0QueZXUWbAxtVpp8Zj8ucGvqzkHnIN8j1YAS8RDk4iwgu3cCSq7gThG4oQYYiz7v ErKCAZNwoOvH8SLng3rOrGSoSnmanXQa9Spxhdl8k5RSM/5t7ZmM3mzKO2j5UACaLV5Q 4t8g== X-Gm-Message-State: AJcUukfhdn4Y2eOw3H+Hg8oNWV/lQrjBQEXftkIVU5+Xhbp43QgZpnz9 p7WXIKQcCOjRAauD7gIln04AOTQr7vFZIg== X-Google-Smtp-Source: ALg8bN5aK8bYR9AlXpQdu31vblfl2MUCRy8mMh4O/SY/zR9tQHfoRoXfsBFR2qDRNJfK2Tp8wG1iog== X-Received: by 2002:a63:413:: with SMTP id 19mr10908015pge.7.1547428308050; Sun, 13 Jan 2019 17:11:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:10 +1100 Message-Id: <20190114011122.5995-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5c2577a9ac..ee95ba7165 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -336,12 +336,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool sp_off) { TCGv_i64 clean =3D new_tmp_a64(s); =20 - /* FIXME: SP+OFS is always unchecked. */ - if (s->tbid && s->mte_active) { + if (s->tbid && s->mte_active && !sp_off) { gen_helper_mte_check(clean, cpu_env, addr); } else { gen_top_byte_ignore(s, clean, addr, s->tbid); @@ -2374,7 +2373,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2392,7 +2391,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2517,7 +2516,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 @@ -2526,7 +2525,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2546,7 +2545,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2562,7 +2561,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2576,7 +2575,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D = 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2594,7 +2593,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D = 31); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2784,7 +2783,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); =20 if (is_vector) { if (is_load) { @@ -2922,7 +2921,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); =20 if (is_vector) { if (is_store) { @@ -3029,7 +3028,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, false); =20 if (is_vector) { if (is_store) { @@ -3114,7 +3113,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); =20 if (is_vector) { if (is_store) { @@ -3198,7 +3197,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn), rn =3D=3D 31); tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ @@ -3259,7 +3258,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3413,7 +3412,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) elements =3D (is_q ? 16 : 8) / ebytes; =20 tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn, rn =3D=3D 31); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (r =3D 0; r < rpt; r++) { @@ -3547,7 +3546,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } =20 tcg_rn =3D cpu_reg_sp(s, rn); - clean_addr =3D clean_data_tbi(s, tcg_rn); + clean_addr =3D clean_data_tbi(s, tcg_rn, rn =3D=3D 31); tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (xs =3D 0; xs < selem; xs++) { --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547428870868353.9480387501777; Sun, 13 Jan 2019 17:21:10 -0800 (PST) Received: from localhost ([127.0.0.1]:56590 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqw5-00046X-5Z for importer@patchew.org; Sun, 13 Jan 2019 20:21:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnB-0005aX-FC for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnA-0000rk-JG for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:53 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:40446) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnA-0000rI-Di for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:52 -0500 Received: by mail-pl1-x643.google.com with SMTP id u18so9345531plq.7 for ; Sun, 13 Jan 2019 17:11:52 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2PYs5yE9xS8a3r0HkYRgoMY35uJiqcAT1vOz7tayvVQ=; b=Zdq5yMz0fqPnb0Qmk/0HWU1unMHGGx4wKioGY+R1wJvPvxLUiEMtnsJsx49pIf/zwg tdRPO0AdheJIK7ZBvI8ykfBQUFnPlASXpfC3P6mTeYfqPl3A6yGa6UKMzQQIAQGFG6bC JDnQpms8FtMkojFa/4zQtm49WOIjde7lcq4iU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2PYs5yE9xS8a3r0HkYRgoMY35uJiqcAT1vOz7tayvVQ=; b=N/NUTEVd1CggAn+tJau/Zss/bl49t4idxRQOzQkw9yF8oqta9AQ6jy3e1ZjtArfutM GP2HsMqOtYpBYkUs7W4i4NLsy96ZrTKlzYNe91w0nXwjOuiO+n5UvIZhjV6sRZ57r4EZ PiFTGUDa19AoORqXxiX6EiDaiQQNFULOeF7ldsHG/WFkr+9feEGfA4e8bZYwQ+HOrrxa KwmV6K+dr5UrlHCvCaN9wZHwWGAjDxsrGxWeQamKGY+YxHZJTOGvzoln54og6s/T/cXE ibPCd2wxBK+/lDBVO30JKsLRgly1eXJa+BBM3bUtPG92MpcwqgLp4UZNzX9J0ERj4HDX NLJg== X-Gm-Message-State: AJcUukes4Co6+A6mg8vtV7j29xXZXXbGsAtYdQnQ5B/yWsVoEGPBfkVT KHWbPNftLpLg5dAfXR9wsbMRyJu/uolCHg== X-Google-Smtp-Source: ALg8bN7BR2The1343s/agoU7o34h3wipf0J91PP5qp82aktSrQPu4pi4wTB6yjRLEI9JAZiPPAcvxg== X-Received: by 2002:a17:902:a9c4:: with SMTP id b4mr23361136plr.298.1547428311110; Sun, 13 Jan 2019 17:11:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:11 +1100 Message-Id: <20190114011122.5995-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 06/17] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 63 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index fa4c371a47..7a6051fdab 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,3 +104,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env,= i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6f4bc0aa04..1878393fc4 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -36,6 +36,48 @@ static int allocation_tag_from_addr(uint64_t ptr) return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; } =20 +/* Like ChooseNonExcludedTag, except that GCR_EL1 is already in. */ +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude !=3D 0xffff) { + int i; + for (i =3D 0; i < offset; ++i) { + do { + tag =3D (tag + 1) & 15; + } while (exclude & (1 << tag)); + } + } + return tag; +} + +static int choose_random_nonexcluded_tag(CPUARMState *env, uint16_t exclud= e) +{ + /* Ignore GCR_EL1.RRND. Always produce deterministic results. */ + int start =3D extract32(env->cp15.rgsr_el1, 0, 4); + int seed =3D extract32(env->cp15.rgsr_el1, 8, 16); + int offset, rtag, i; + + /* RandomTag */ + for (i =3D offset =3D 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top =3D (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed =3D (top << 15) | (seed >> 1); + offset |=3D top << i; + } + rtag =3D choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 =3D rtag | (seed << 8); + + return rtag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -=3D extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); @@ -108,3 +150,16 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t = ptr) /* Unchecked, or tag check pass. Ignore the top byte. */ return sextract64(ptr, 0, 55); } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + uint16_t exclude =3D rm | env->cp15.gcr_el1; + rtag =3D choose_random_nonexcluded_tag(env, exclude); + } + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee95ba7165..b0349bffc4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5105,6 +5105,13 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547429057850839.1914578501317; Sun, 13 Jan 2019 17:24:17 -0800 (PST) Received: from localhost ([127.0.0.1]:57367 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqzA-0006Rb-PH for importer@patchew.org; Sun, 13 Jan 2019 20:24:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnE-0005dq-PU for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnD-0000uZ-OX for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:56 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43031) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnD-0000tu-JU for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:55 -0500 Received: by mail-pf1-x444.google.com with SMTP id w73so9535177pfk.10 for ; Sun, 13 Jan 2019 17:11:55 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zQWwHZdE0XEmu0eOmYlElX3aU8HsD5IKAzX45HBjqL0=; b=eVakkAEgn6TL8pgzLNe9EuYrR+dNvG07dJPTfb+6p9kFTO7iXTIr5WQXjq5hRcgHrQ Sl6svAP3zApq9qLsEtIwD702jOatMApY4hA3kPClXuO0VQXcSSN4WYtBMSAzRxK88ul8 4s3C0Pm22yOvBXQrp0dpqDsnmUuOErMblOEXQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zQWwHZdE0XEmu0eOmYlElX3aU8HsD5IKAzX45HBjqL0=; b=L8nviz2qPjzEmsgqxEv/cTHFzCzCbNAlTsalT//JWL9t6RgL59lDNVXTsXuIuVM964 HVZ9lgqntG39RhW89RoC+a686+Dbn5qTifrRv1HWa9WL4XLxVIJ4eCIz3T5lEHlBgVwl AvZ12g68JiF/2HVpQP0H6dCybvR+bUqpbuZuq3CNd0PIu/ftyNLonP24LoXZJpfCyUlD fUzlyQCop3aBXmhpEHxTyuoi0xrtYA7slqXJwN471YoObjsn47hif3yuE7L9OfCT50k7 D5tUimekrbLwZNALjCXhUP2zXgEY3DBjLNdZ+Xa7C/GRIQIpoGhDQl1cqUDWBgK+qhFS UnkQ== X-Gm-Message-State: AJcUukc49KfoGdRLH1/2IRo+gyeozMbb2IWuCKTa9LBlbkDeZN6qg0FY 3W8I7g1wq+g7G9Ku8Hp/NQ0VKwgjRyHwTA== X-Google-Smtp-Source: ALg8bN7SkKIOAAhSN2s658p/Lj5UuDufYsZm47QbLLESYnlWgyCWDu6ESrfN+0WDGK+AJ06oTuK5XQ== X-Received: by 2002:a63:88c7:: with SMTP id l190mr20683453pgd.110.1547428314189; Sun, 13 Jan 2019 17:11:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:12 +1100 Message-Id: <20190114011122.5995-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 3 ++ target/arm/mte_helper.c | 34 ++++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 87 insertions(+), 23 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7a6051fdab..47577207b2 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env,= i64) =20 DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..a5a249b001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,7 @@ static inline bool allocation_tag_access_enabled(CPUA= RMState *env, int el, return sctlr !=3D 0; } =20 +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 1878393fc4..e2b1a5dd40 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -163,3 +163,37 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, ui= nt64_t rm) } return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D env->cp15.gcr_el1; + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<=3D LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag =3D allocation_tag_from_addr(ptr); + uint16_t exclude =3D env->cp15.gcr_el1; + rtag =3D choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<=3D LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b0349bffc4..879d6b8d46 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3652,7 +3652,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_= t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3663,10 +3665,10 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) bool setflags =3D extract32(insn, 29, 1); bool sub_op =3D extract32(insn, 30, 1); bool is_64bit =3D extract32(insn, 31, 1); + bool is_tag =3D false; =20 TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); TCGv_i64 tcg_rd =3D setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; =20 switch (shift) { case 0x0: @@ -3674,35 +3676,58 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) case 0x1: imm <<=3D 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag =3D true; + break; default: + do_unallocated: unallocated_encoding(s); return; } =20 - tcg_result =3D tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm =3D tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset =3D tcg_const_i32(imm & 15); + TCGv_i32 offset =3D tcg_const_i32(imm >> 6); =20 - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; =20 - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result =3D tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm =3D tcg_const_i64(imm); + tcg_result =3D new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } =20 /* The input should be a value in the bottom e bits (with higher --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547428836699715.8061394849894; Sun, 13 Jan 2019 17:20:36 -0800 (PST) Received: from localhost ([127.0.0.1]:56441 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqvb-0003fu-Es for importer@patchew.org; Sun, 13 Jan 2019 20:20:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnH-0005gN-8a for qemu-devel@nongnu.org; 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Sun, 13 Jan 2019 17:11:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:13 +1100 Message-Id: <20190114011122.5995-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 08/17] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 47577207b2..ef340cb6f9 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -107,3 +107,4 @@ DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env,= i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e2b1a5dd40..2f6ac45150 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -197,3 +197,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, offset <<=3D LOG2_TAG_GRANULE; return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag =3D allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 879d6b8d46..6583ad93b1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5137,6 +5137,12 @@ static void disas_data_proc_2src(DisasContext *s, ui= nt32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 13 Jan 2019 17:12:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:14 +1100 Message-Id: <20190114011122.5995-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 09/17] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6583ad93b1..98ff60c161 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5111,19 +5111,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf =3D extract32(insn, 31, 1); + setflag =3D extract32(insn, 29, 1); rm =3D extract32(insn, 16, 5); opcode =3D extract32(insn, 10, 6); rn =3D extract32(insn, 5, 5); rd =3D extract32(insn, 0, 5); =20 - if (extract32(insn, 29, 1)) { + if (setflag && opcode !=3D 0) { unallocated_encoding(s); return; } =20 switch (opcode) { + case 0: /* SUBP(S) */ + if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n =3D read_cpu_reg_sp(s, rn, true); + tcg_m =3D read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 55); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 55); + tcg_d =3D cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 53 +++++++++++++++++++ target/arm/translate-a64.c | 106 +++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ef340cb6f9..ff37c8975a 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,6 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64,= i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 2f6ac45150..06fd9c18f9 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -31,6 +31,12 @@ static int get_allocation_tag(CPUARMState *env, uint64_t= ptr) return -1; } =20 +static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, int tag) +{ + /* Tag storage not implemented. */ + return false; +} + static int allocation_tag_from_addr(uint64_t ptr) { return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; @@ -203,3 +209,50 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag =3D allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag =3D 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + rtag =3D get_allocation_tag(env, ptr); + if (rtag < 0) { + rtag =3D 0; + } + } + return address_with_allocation_tag(ptr, rtag); +} + +uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int tag =3D allocation_tag_from_addr(ptr); + set_allocation_tag(env, ptr, tag); + } + + /* Clean the pointer for use by stgz. */ + /* ??? Do we need a more precise TBI here? */ + return sextract64(ptr, 0, 55); +} + +uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int tag =3D allocation_tag_from_addr(ptr); + if (set_allocation_tag(env, ptr, tag)) { + set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag); + } + } + + /* Clean the pointer for use by stgz. */ + /* ??? Do we need a more precise TBI here? */ + return sextract64(ptr, 0, 55); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 98ff60c161..60865945e4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3583,6 +3583,109 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) } } =20 +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 =3D extract32(insn, 10, 3); + int op1 =3D extract32(insn, 22, 2); + bool is_load =3D false, is_pair =3D false, is_zero =3D false; + int index =3D 0; + TCGv_i64 dirty_addr, clean_addr; + + if ((insn & 0xff200000) !=3D 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 !=3D 0) { + /* STG */ + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 !=3D 0) { + /* STZG */ + is_zero =3D true; + index =3D op2 - 2; + } else { + /* LDG */ + is_load =3D true; + } + break; + case 2: + if (op2 !=3D 0) { + /* ST2G */ + is_pair =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 !=3D 0) { + /* STZ2G */ + is_pair =3D is_zero =3D true; + index =3D op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr =3D read_cpu_reg_sp(s, rn, true); + if (index <=3D 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr =3D tcg_temp_new_i64(); + if (is_load) { + gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); + } else if (is_pair) { + gen_helper_st2g(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } + + if (is_zero) { + TCGv_i64 tcg_zero =3D tcg_const_i64(0); + int mem_index =3D get_mem_index(s); + int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i =3D 0; i < n; i +=3D 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + tcg_temp_free_i64(clean_addr); + + if (index !=3D 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3607,6 +3710,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547428916240490.1216842650257; Sun, 13 Jan 2019 17:21:56 -0800 (PST) Received: from localhost ([127.0.0.1]:56794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqwt-0004hy-5s for importer@patchew.org; Sun, 13 Jan 2019 20:21:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnQ-0005p8-JB for qemu-devel@nongnu.org; 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Sun, 13 Jan 2019 17:12:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:16 +1100 Message-Id: <20190114011122.5995-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 60865945e4..911d6f06b3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2696,7 +2696,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2721,6 +2721,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) bool is_signed =3D false; bool postindex =3D false; bool wback =3D false; + bool set_tag =3D false; =20 TCGv_i64 clean_addr, dirty_addr; =20 @@ -2733,6 +2734,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) =20 if (is_vector) { size =3D 2 + opc; + } else if (opc =3D=3D 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { + unallocated_encoding(s); + return; + } + size =3D 3; + set_tag =3D true; } else { size =3D 2 + extract32(opc, 1, 1); is_signed =3D extract32(opc, 0, 1); @@ -2783,7 +2792,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); + if (set_tag) { + clean_addr =3D new_tmp_a64(s); + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } else { + clean_addr =3D clean_data_tbi(s, dirty_addr, rn =3D=3D 31); + } =20 if (is_vector) { if (is_load) { --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 ++ target/arm/mte_helper.c | 51 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 34 ++++++++++++++++++++----- 3 files changed, 81 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ff37c8975a..5bbfe43c13 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -111,3 +111,5 @@ DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i= 64) DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(ldgv, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgv, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 06fd9c18f9..b125f49258 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -256,3 +256,54 @@ uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) /* ??? Do we need a more precise TBI here? */ return sextract64(ptr, 0, 55); } + +uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + uint64_t ret; + int rtag, i; + + if (!allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + + ptr =3D QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); + rtag =3D get_allocation_tag(env, ptr); + if (rtag < 0) { + /* The entire page does not have tags. */ + return 0; + } + + i =3D extract32(ptr, LOG2_TAG_GRANULE, 4); + ret =3D (uint64_t)rtag << i; + for (i++; i < 16; i++) { + rtag =3D get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE)); + ret |=3D (uint64_t)rtag << i; + } + + return ret; +} + +void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int el =3D arm_current_el(env); + uint64_t sctlr =3D arm_sctlr(env, el); + int rtag, i; + + if (!allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag =3D allocation_tag_from_addr(ptr); + ptr =3D QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); + if (!set_allocation_tag(env, ptr, rtag)) { + /* The entire page does not have tags. */ + return; + } + + i =3D extract32(ptr, LOG2_TAG_GRANULE, 4); + for (i++; i < 16; i++) { + set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 911d6f06b3..b4226def40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3612,7 +3612,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 =3D extract32(insn, 10, 3); int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false; + bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_tagv = =3D false; int index =3D 0; TCGv_i64 dirty_addr, clean_addr; =20 @@ -3644,17 +3644,29 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) /* ST2G */ is_pair =3D true; index =3D op2 - 2; - break; + } else { + /* STGV */ + if (s->current_el =3D=3D 0 || offset !=3D 0) { + goto do_unallocated; + } + is_tagv =3D true; + index =3D 1; } - goto do_unallocated; + break; case 3: if (op2 !=3D 0) { /* STZ2G */ is_pair =3D is_zero =3D true; index =3D op2 - 2; - break; + } else { + /* LDGV */ + if (s->current_el =3D=3D 0 || offset !=3D 0 || rt =3D=3D rn) { + goto do_unallocated; + } + is_load =3D is_tagv =3D true; + index =3D 1; } - goto do_unallocated; + break; =20 default: do_unallocated: @@ -3669,7 +3681,17 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) } =20 clean_addr =3D tcg_temp_new_i64(); - if (is_load) { + if (is_tagv) { + if (is_load) { + gen_helper_ldgv(cpu_reg(s, rt), cpu_env, dirty_addr); + } else { + gen_helper_stgv(cpu_env, dirty_addr, cpu_reg(s, rt)); + } + + /* Post-increment with dirty =3D align_up(dirty, 16*TAG_GRANULE). = */ + tcg_gen_ori_i64(dirty_addr, dirty_addr, (16 << LOG2_TAG_GRANULE) -= 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, 1); + } else if (is_load) { gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); } else if (is_pair) { gen_helper_st2g(clean_addr, cpu_env, dirty_addr); --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547429031577704.1816901212537; Sun, 13 Jan 2019 17:23:51 -0800 (PST) Received: from localhost ([127.0.0.1]:57268 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqyk-00065N-Hv for importer@patchew.org; Sun, 13 Jan 2019 20:23:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37150) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnW-0005uT-RC for qemu-devel@nongnu.org; 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Sun, 13 Jan 2019 17:12:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:18 +1100 Message-Id: <20190114011122.5995-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" R0085 specifies that exception handlers begin with tag checks overridden. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index df43deb0f8..1e9ccf0b2e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 - pstate_write(env, PSTATE_DAIF | new_mode); + pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); =20 --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 154742903193232.7806317191621; Sun, 13 Jan 2019 17:23:51 -0800 (PST) Received: from localhost ([127.0.0.1]:57274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqyk-00065y-Mt for importer@patchew.org; Sun, 13 Jan 2019 20:23:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqni-000653-38 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnZ-00016v-1M for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:21 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:37008) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnY-00016a-Rb for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:16 -0500 Received: by mail-pg1-x543.google.com with SMTP id c25so8739326pgb.4 for ; Sun, 13 Jan 2019 17:12:16 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QEnnJ0lnXGNqeUVPB5fOxxV2hOiG+cnB1X7vEWDXqS0=; b=DwWoYC8HbRPzOlRLwQsLFonSKFOPmWhpB51Y7KnksUeC/e7ZlwkyHiZo+qyZDNtKdq 4FL7XWzI8hQfYWMPgBaDFaaGMudBZyJEUdzbEZfUceONUkRyi3MrMhNVOi+fpY4g/NzB iAsL4wU1+haZCDKwNjEZZXn3rMzgmKtMvpTEY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QEnnJ0lnXGNqeUVPB5fOxxV2hOiG+cnB1X7vEWDXqS0=; b=GslDnE3Tmpxxfm/uHkAwPs7vZDr+p67ghaz42tMOUfbYCr46wrIvAXje95LWQZEn93 ruzUUVFnvycQtJ4Znzi/FdLkbOpwwIy+GKCzK5nuOsD8f+yh22Oc/1JfoO1FrMy6RJA6 X4M1BBjtJ2BJ99oJpD9O5kOqco7xEcD3+S3D6yR/pmydznoOpJjyY4M0hfFm9WMddOdS DAStOYg1qxgn1e6JJE8N1lkJ/kJ8u3lHBDi4jDPzCF3KsfPZiJQT78Tp/o0EjTOWxcLi Q52NPyfkP+eMbZYH726SyTc87BoYHBfsttNKWNH79b0cwy0h7n4hpgDpRrQozR6g96cY OLjw== X-Gm-Message-State: AJcUukc6e7ouH7ph/G2akX3dBf3TL7kakVT+q1UmrgnmiQT9OfO5seaH brgvV6NN1gSbzB+L/C0UANqC7xN7XqB+xQ== X-Google-Smtp-Source: ALg8bN66OXJWGvSAVCrlL1EtU1In3Q/hiLFlfXjmc3R1uj9i5ouZ8kGbSqSlY1kxv640KeDXJtrNXQ== X-Received: by 2002:a63:ed42:: with SMTP id m2mr21204447pgk.147.1547428335527; Sun, 13 Jan 2019 17:12:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:19 +1100 Message-Id: <20190114011122.5995-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 14/17] tcg: Introduce target-specific page data for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At the same time, remember MAP_SHARED as PAGE_SHARED. When mapping new pages, make sure that old target-specific page data is removed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 10 ++++++++-- linux-user/syscall.c | 4 ++-- 4 files changed, 46 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 117d2fbbca..92ec47dc79 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -244,10 +244,14 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 /* Invalidate the TLB entry immediately, helpful for s390x * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () */ -#define PAGE_WRITE_INV 0x0040 +#define PAGE_WRITE_INV 0x0020 +/* Page is mapped shared. */ +#define PAGE_SHARED 0x0040 +/* For use with page_set_flags: page is being replaced; target_data cleare= d. */ +#define PAGE_RESET 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif =20 #if defined(CONFIG_USER_ONLY) @@ -260,6 +264,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif =20 CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b2728..047cd2f50d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -111,6 +111,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2477,6 +2478,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; =20 /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2493,6 +2495,8 @@ void page_set_flags(target_ulong start, target_ulong = end, int flags) if (flags & PAGE_WRITE) { flags |=3D PAGE_WRITE_ORG; } + reset_target_data =3D !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &=3D ~PAGE_RESET; =20 for (addr =3D start, len =3D end - start; len !=3D 0; @@ -2506,10 +2510,34 @@ void page_set_flags(target_ulong start, target_ulon= g end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data =3D NULL; + } p->flags =3D flags; } } =20 +void *page_get_target_data(target_ulong address) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p =3D page_find(address >> TARGET_PAGE_BITS); + void *ret =3D NULL; + + if (p) { + ret =3D p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data =3D ret =3D g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 41e0983ce8..f83874b8c1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -562,7 +562,11 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, i= nt prot, } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + if ((flags & MAP_TYPE) =3D=3D MAP_SHARED) { + prot |=3D PAGE_SHARED; + } + prot |=3D PAGE_RESET | PAGE_VALID; + page_set_flags(start, start + len, prot); the_end: #ifdef DEBUG_MMAP printf("ret=3D0x" TARGET_ABI_FMT_lx "\n", start); @@ -754,9 +758,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong o= ld_size, new_addr =3D -1; } else { new_addr =3D h2g(host_addr); + /* FIXME: Move page flags (and target_data?) for each page. */ prot =3D page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 280137da8c..715101816d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3845,8 +3845,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_en= v, raddr=3Dh2g((unsigned long)host_raddr); =20 page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_SHARED | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); =20 for (i =3D 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547429256942474.79158394199203; Sun, 13 Jan 2019 17:27:36 -0800 (PST) Received: from localhost ([127.0.0.1]:58176 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gir2N-0000YH-To for importer@patchew.org; Sun, 13 Jan 2019 20:27:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37294) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnv-0006HP-26 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnt-0001GF-Qb for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:38 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:33365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnr-00017w-OG for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:37 -0500 Received: by mail-pf1-x444.google.com with SMTP id c123so9556670pfb.0 for ; Sun, 13 Jan 2019 17:12:19 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b0Bd53fbJ2LZjbAcwZlwr3sBleKyMI9LmM/ZZ1rSte4=; b=WCyHgWDAIYn6QlNQEIhK6gcSiY40uUcV1hNOf6SBpKYWzJDqka8LBgy0NEgANK8onY kNkRqmUJifrkwPxyvPTGgEHu7V4IRHboDJ9J/2Bt8wMJK+rspSSjR537oA+Qrx+yfMc+ NuXbQpDseVdO4qwH7t1U9AdxT11AI/HA1Q7Ww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b0Bd53fbJ2LZjbAcwZlwr3sBleKyMI9LmM/ZZ1rSte4=; b=BJqyUhTRIcqYTcg5aaVIIgp3ta6UV0WxD2L1fRlKbRgkVo/wEWpPIiL0fjloTyVu6C 5TMSGhqjDWr4cra+zFwb9uXXmn79GCrBEltWAUFOAzIvNfaWqSLTjzZwyKrce46+9y34 SVb2XBVGurOJp5jzYTVdf0kAVaL+RYTIW0PIV8ROcsfVJO4Sz3SdbMlfWzIUrENrrf1V qo4D3nhmkDND9vSgKUkubbF9xrcb9FYxFi+SaUOc1A+Uocw5WorBwWHkTm+Lqq8AEbJj iHv1vm9XPxOKQJFrZlCnkVr1INwHETE4SnzK/JjDP8L/AwSWS59zqROltZG2CR++p32T 026w== X-Gm-Message-State: AJcUukds8TxJGAR2GbZ6u2rYMgpFYTMV7/hM7SkxzrQ2LSSv7xNTETvH /O9WVlv5UhUiX8zRaSyvDsVvrUflBz2kFQ== X-Google-Smtp-Source: ALg8bN7bcP0iri0+CCXJOhymFvED7ac2gZzjN3C7j4Uz04JB8F46Jhpb4Y8N0yN1ovj42dRMFEx7+A== X-Received: by 2002:a63:d450:: with SMTP id i16mr18639708pgj.246.1547428338802; Sun, 13 Jan 2019 17:12:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:20 +1100 Message-Id: <20190114011122.5995-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 15/17] target/arm: Add allocation tag storage for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 82 +++++++++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 11 deletions(-) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index b125f49258..87328c7a9a 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,16 +25,72 @@ #include "exec/helper-proto.h" =20 =20 -static int get_allocation_tag(CPUARMState *env, uint64_t ptr) +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + uint64_t clean_ptr =3D extract64(ptr, 0, 56); + uint8_t *tags =3D page_get_target_data(clean_ptr); + + if (tags !=3D NULL) { + uintptr_t index =3D extract64(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - = 1); + return extract32(tags[index], (clean_ptr & 1) * 4, 4); + } else { + int flags =3D page_get_flags(clean_ptr); + + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return -1; + } else if (flags & PAGE_VALID) { + /* Page is good, but no tags have been written: all are 0. */ + return 0; + } else { + /* Page is invalid: SIGSEGV. */ + env->exception.vaddress =3D ptr; + cpu_restore_state(ENV_GET_CPU(env), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + } +#else /* Tag storage not implemented. */ return -1; +#endif } =20 -static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, int tag) +static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, + int tag, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + uint64_t clean_ptr =3D extract64(ptr, 0, 56); + uint8_t *tags =3D page_get_target_data(clean_ptr); + uintptr_t index; + + if (tags =3D=3D NULL) { + int flags =3D page_get_flags(clean_ptr); + size_t alloc_size; + + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return false; + } else if (!(flags & PAGE_VALID)) { + /* Page is invalid: SIGSEGV. */ + env->exception.vaddress =3D ptr; + cpu_restore_state(ENV_GET_CPU(env), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags =3D page_alloc_target_data(clean_ptr, alloc_size); + assert(tags !=3D NULL); + } + index =3D extract64(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + tags[index] =3D deposit32(tags[index], (clean_ptr & 1) * 4, 4, tag); + return true; +#else /* Tag storage not implemented. */ return false; +#endif } =20 static int allocation_tag_from_addr(uint64_t ptr) @@ -116,7 +172,7 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t p= tr) * access as unchecked. * This is similar to MemAttr !=3D Tagged, which are also unchecked. */ - mem_tag =3D get_allocation_tag(env, ptr); + mem_tag =3D get_allocation_tag(env, ptr, GETPC()); if (mem_tag < 0) { goto pass; } @@ -217,7 +273,7 @@ uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) int rtag =3D 0; =20 if (allocation_tag_access_enabled(env, el, sctlr)) { - rtag =3D get_allocation_tag(env, ptr); + rtag =3D get_allocation_tag(env, ptr, GETPC()); if (rtag < 0) { rtag =3D 0; } @@ -232,7 +288,7 @@ uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) =20 if (allocation_tag_access_enabled(env, el, sctlr)) { int tag =3D allocation_tag_from_addr(ptr); - set_allocation_tag(env, ptr, tag); + set_allocation_tag(env, ptr, tag, GETPC()); } =20 /* Clean the pointer for use by stgz. */ @@ -247,8 +303,10 @@ uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) =20 if (allocation_tag_access_enabled(env, el, sctlr)) { int tag =3D allocation_tag_from_addr(ptr); - if (set_allocation_tag(env, ptr, tag)) { - set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag); + uintptr_t ra =3D GETPC(); + + if (set_allocation_tag(env, ptr, tag, ra)) { + set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag, ra= ); } } =20 @@ -261,6 +319,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) { int el =3D arm_current_el(env); uint64_t sctlr =3D arm_sctlr(env, el); + uintptr_t ra =3D GETPC(); uint64_t ret; int rtag, i; =20 @@ -269,7 +328,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) } =20 ptr =3D QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); - rtag =3D get_allocation_tag(env, ptr); + rtag =3D get_allocation_tag(env, ptr, ra); if (rtag < 0) { /* The entire page does not have tags. */ return 0; @@ -278,7 +337,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) i =3D extract32(ptr, LOG2_TAG_GRANULE, 4); ret =3D (uint64_t)rtag << i; for (i++; i < 16; i++) { - rtag =3D get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE)); + rtag =3D get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), ra= ); ret |=3D (uint64_t)rtag << i; } =20 @@ -289,6 +348,7 @@ void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) { int el =3D arm_current_el(env); uint64_t sctlr =3D arm_sctlr(env, el); + uintptr_t ra =3D GETPC(); int rtag, i; =20 if (!allocation_tag_access_enabled(env, el, sctlr)) { @@ -297,13 +357,13 @@ void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uin= t64_t val) =20 rtag =3D allocation_tag_from_addr(ptr); ptr =3D QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); - if (!set_allocation_tag(env, ptr, rtag)) { + if (!set_allocation_tag(env, ptr, rtag, ra)) { /* The entire page does not have tags. */ return; } =20 i =3D extract32(ptr, LOG2_TAG_GRANULE, 4); for (i++; i < 16; i++) { - set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag); + set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag, ra); } } --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sun, 13 Jan 2019 17:12:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:21 +1100 Message-Id: <20190114011122.5995-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 16/17] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ??? It does not yet work for system mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5eff6995ee..aae30207b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -180,6 +180,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr =3D (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |=3D HCR_ATA; + env->cp15.scr_el3 |=3D SCR_ATA; + env->cp15.sctlr_el[1] |=3D SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |=3D 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 =3D 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 64fbe75eca..49fdad69ce 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -374,6 +374,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64pfr1; t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; --=20 2.17.2 From nobody Thu May 9 01:24:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1547429234225280.0262141583172; Sun, 13 Jan 2019 17:27:14 -0800 (PST) Received: from localhost ([127.0.0.1]:58029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gir1i-0008TO-Bo for importer@patchew.org; Sun, 13 Jan 2019 20:26:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnv-0006IC-OV for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnt-0001GQ-Qj for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:39 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:37888) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqns-0001Ak-Hq for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:37 -0500 Received: by mail-pl1-x641.google.com with SMTP id e5so9337421plb.5 for ; Sun, 13 Jan 2019 17:12:26 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RF1blEfpbrvZ+eBn0f+rgZeNzRwB/ONHSYLlKUEqtWI=; b=TER98Q5N6GjPCbtLDkMn3VrHvVgGRs+wB5pJFd9MMnkdgn7NxlUpK+XOaWcZtzBTxs pIG8UFDbpYYyaP6qHYjPWlofs7KADcBr7nUNlAckxouBHXDmpCReKjyhz4HdyH5HWQ6k yB9qzT+LbWtvG6kv9oXpdBs5Ka8gEh6y0qPSQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RF1blEfpbrvZ+eBn0f+rgZeNzRwB/ONHSYLlKUEqtWI=; b=Jw/Exn9dd8pthK+Wh9/ThzgKsn1cYksc7Zls0hrGVmKlfkEC6yXnAN/jmcJBZv6ees wh1L/fV/QfG2lmF4GUvAopRwQJy2O/zj79i8f/QIDEuAplMH1fHxE3pa0/kU8Xvw3g4t dhm0Rnykc9bhmJcxbNs/3eO1DnNAbs0iVVv5/PhMrPpY8UAKYqogz9UINiVDlqrw+xUN 47oquWsvlz9yB3EZ48qithRAw7EF0swJ5NM02VYgcfvQinYPuo8yRy7NIHr9c6tEzvo4 nh6OCpWPLDv6i3A8cMiIvNzqKru4HvvYj7RnZcLSIuX5m0+7TF2Y+Qz3U1NTCA+ep/ls bXhA== X-Gm-Message-State: AJcUukfcMFmarHxdDh1t6hmE4jCJJ30bzaoOF36+k6qzwIBGjsxQyNhr Mr68z5sZxbl3JXm30B12gb0Hz955AQmG7w== X-Google-Smtp-Source: ALg8bN7E8PPeetdEv90GbphRBsowAKTyzyrc3o05RzCUCWrRoRYuCcE8ZR/fhkyfdza4cjM+Bp7Ijg== X-Received: by 2002:a17:902:a5ca:: with SMTP id t10mr23323052plq.139.1547428345209; Sun, 13 Jan 2019 17:12:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:22 +1100 Message-Id: <20190114011122.5995-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ??? Requires a quite recent aarch64 assembler. Use .inst instead? Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++ tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++++ 3 files changed, 70 insertions(+) create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..740bf506f1 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,27 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +int main(int ac, char **av) +{ + int *p0 =3D data; + int *p1, *p2; + long c; + + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(1)); + assert(p1 !=3D p0); + asm("subp %0,%1,%2" : "=3Dr"(c) : "r"(p0), "r"(p1)); + assert(c =3D=3D 0); + + asm("stg [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=3Dr"(p2) : "r"(p0)); + assert(p1 =3D=3D p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..4d2004ab41 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,39 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include +#include +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +void pass(int sig) +{ + exit(0); +} + +int main(int ac, char **av) +{ + int *p0 =3D data; + int *p1, *p2; + long excl =3D 1; + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=3Dr"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl !=3D 1); + asm("irg %0,%1,%2" : "=3Dr"(p2) : "r"(p0), "r"(excl)); + assert(p1 !=3D p2); + + /* Store the tag from the first pointer. */ + asm("stg [%0]" : : "r"(p1)); + + *p1 =3D 0; + signal(SIGSEGV, pass); + *p2 =3D 0; + + assert(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 3d56e7c6ea..1c4ebe894c 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -19,4 +19,8 @@ AARCH64_TESTS +=3D bti-1 bti-1: LDFLAGS +=3D -nostartfiles -nodefaultlibs -nostdlib run-bti-1: QEMU +=3D -cpu max,guarded_pages=3Don =20 +AARCH64_TESTS +=3D mte-1 mte-2 +mte-%: CFLAGS +=3D -O -g +run-mte-%: QEMU +=3D -cpu max + TESTS:=3D$(AARCH64_TESTS) --=20 2.17.2