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[220.239.117.135]) by smtp.gmail.com with ESMTPSA id g28sm132656016pfd.100.2019.01.10.04.50.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Jan 2019 04:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lgpz8q+muFznxKLaWMgdH+QvhIvbcK4cjoZjSmcuDjg=; b=Uid/lklzKYYOiyR5eu4jRLu3OhCiA1mZLad+uRRHymK+MjTO8DluOYwhYf2RtypCIg bsFwJNHEpMkSERXwNegxN/1CmiGqmcUvmpoTvEZrcCyyA3Fmqur/xVNPlx0wQLuzGvrH kqBvygISLCZeey5lPk/xpoKJdMgaaqPfTBCdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lgpz8q+muFznxKLaWMgdH+QvhIvbcK4cjoZjSmcuDjg=; b=IyOGkUeCTlvd37XwWcBJ0iJ4fftvaV1/A4eIirfmseSo3O5oytC6+wtr0ti6w4z/7V W/bmSxiTMt7CLglzVIHiXcTuOJZXALrWYP70L6wGh2ZI6VtlsOs5ao7kmNKv8jS1ZTmQ SZGLGWGncweHoWqY4/laOoZvcC84jrXqKYFMmMQs5BH5XA6frbu6O3rvoMFYVZzeVLhJ GRR+RMCQcZn0aN0d+JOZmXLo71/B0I4KNle28AaTC4DMeIVePVil13kbAXbGaI/VMRsR V83AU6xvEv7yXjyvzNBXHr2v0+zTCXv+tYhn11/whfUl9e8JtksAWB/9pIJPvcGHvaN9 3jPA== X-Gm-Message-State: AJcUukekDqCiLP5zdBJCUsnALUxvQBfXOlyVKEdvLogLImeYcnNka5AG mSESdR1Ql5vyBxIJaWrLUP5MhRQ9gc+ZJw== X-Google-Smtp-Source: ALg8bN55fKvA+Z26RIz5UV5AUgouKTJXp4Z0uT6N1QlreWrGAzmfOXlZnSZtxewjW8CPJufv/wj+9g== X-Received: by 2002:a63:6346:: with SMTP id x67mr7060533pgb.183.1547124605250; Thu, 10 Jan 2019 04:50:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 Jan 2019 23:49:50 +1100 Message-Id: <20190110124951.15473-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190110124951.15473-1-richard.henderson@linaro.org> References: <20190110124951.15473-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Compute TB_FLAGS for TBI for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Enables, but does not turn on, TBI for CONFIG_USER_ONLY. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 21 --------------------- target/arm/helper.c | 13 ++++++------- 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d01a3f9f44..a4bd1becb7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -963,30 +963,9 @@ typedef struct ARMVAParameters { bool using64k : 1; } ARMVAParameters; =20 -#ifdef CONFIG_USER_ONLY -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx) -{ - return (ARMVAParameters) { - /* 48-bit address space */ - .tsz =3D 16, - /* We can't handle tagged addresses properly in user-only mode */ - .tbi =3D false, - }; -} - -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, - uint64_t va, - ARMMMUIdx mmu_idx, bool d= ata) -{ - return aa64_va_parameters_both(env, va, mmu_idx); -} -#else ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -#endif =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c28c6d044..0ceb1fa2b8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6549,7 +6549,7 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY =20 /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) @@ -8923,6 +8923,7 @@ void arm_cpu_do_interrupt(CPUState *cs) cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; } } +#endif /* !CONFIG_USER_ONLY */ =20 /* Return the exception level which controls this address translation regi= me */ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -9084,6 +9085,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) } } =20 +#ifndef CONFIG_USER_ONLY /* Translate section/page access permissions to page * R/W protection flags * @@ -9771,6 +9773,7 @@ static uint8_t convert_stage2_attrs(CPUARMState *env,= uint8_t s2attrs) =20 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; } +#endif /* !CONFIG_USER_ONLY */ =20 ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx) @@ -9841,6 +9844,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, return ret; } =20 +#ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -13087,11 +13091,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, *pc =3D env->pc; flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 -#ifndef CONFIG_USER_ONLY - /* - * Get control bits for tagged addresses. Note that the - * translator only uses this for instruction addresses. - */ + /* Get control bits for tagged addresses. */ { ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); @@ -13110,7 +13110,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); } -#endif =20 if (cpu_isar_feature(aa64_sve, cpu)) { int sve_el =3D sve_exception_el(env, current_el); --=20 2.17.2